JP3309905B2 - Semiconductor device including field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including an insulated gate field effect transistor with a high breakdown voltage.

[0002]

2. Description of the Related Art The present applicant has manufactured a composite or integrated semiconductor device shown in FIG. This semiconductor device has a first semiconductor element 1 composed of an insulated gate field effect transistor, and a second semiconductor element 2 having a smaller power capacity than the first semiconductor element 1. A silicon semiconductor substrate 3 for forming the first and second semiconductor elements 1 and 2;
Drain electrode 4, source electrode 5, gate insulating film 6, gate electrode 7, ground electrode 8, capacitively-coupled field plate structure 9 for first semiconductor element 1, electrode 10 for second semiconductor element 2 Etc.

A semiconductor substrate 3 includes a P-type (first conductivity type) substrate (base layer) region 11 and an N-type (second conductivity type) region.
First drain region 12 and first drain region 12
N ⁺ -type second drain region 1 having a higher impurity concentration than
3, a P-type channel forming region 14 surrounding the first drain region 12 in plan view, an N ^{+ -type} source region 15, and a semiconductor region 16 for the second semiconductor element 2. . The semiconductor region 16 for the second semiconductor element 2 includes a collector region 16a, a base region 16b, and an emitter region 1.
6c. Note that a high impurity concentration N ^{+ -type} contact region may be formed in the collector electrode 16a in order to obtain good ohmic contact with the collector electrode.
The substrate region 11 is formed so as to include the entire back surface (lower surface) of the plate-shaped semiconductor substrate 3. The first drain region 12 is based on a layer in which an N-type semiconductor is epitaxially grown on the substrate region 11, has a relatively large area in plan view, and contributes to a higher breakdown voltage of the FET. I have. N ⁺ -type second drain region 1
Reference numeral 3 denotes a region for making the drain electrode 3 satisfactorily in ohmic contact, and is arranged at the center of the first drain region 12. The N ⁺ -type second drain region 13 is formed by diffusing an N-type impurity into the first drain region 12 in an island shape.
Is formed relatively shallow so as not to reach. The P-type channel forming region 14 surrounds the first drain region 12 in plan view and also has a surface (upper surface) of the semiconductor substrate 3.
Are arranged so as to reach the P-type substrate region 11. Therefore, the channel formation region 14 not only contributes to the formation of the channel of the FET, but also contributes to the electrical isolation between the first and second semiconductor elements 1 and 2.
Note that the channel forming region 14 or the substrate region 11 and the channel forming region 14 together can be called a body region of the FET. The N + -type source region 15 is annularly arranged so as to surround the first drain region 12 via the channel forming region 14 when viewed in a plan view.
It is formed by diffusing into an island shape. As a semiconductor region 16 for the second semiconductor element 2, an N-type collector region 16a of the transistor is arranged on the substrate region 11 so as to be adjacent to the channel forming region 14 in plan view.

The drain electrode 4 is connected to an N ^{+ type} second drain region 13. Source electrode 5 is connected to N ^{+ type} source region 15. The gate insulating film 6 is disposed between the source region 15 and the first drain region 12 so as to cover the channel forming region 14 exposed on the surface of the semiconductor substrate 3. Gate electrode 7 is arranged on gate insulating film 6, and has source region 15 and first drain region 1.
2 is opposed to the channel forming region 14. The ground electrode or back gate electrode 8 is arranged apart from the gate electrode 7, connected to the substrate region 11 via the channel forming region 14,
This contributes to fixing 1 to the lowest potential. Note that the emitter electrode 5 and the ground electrode 8 may be formed integrally.

[0005] Capacitively coupled field plate assembly 9
A plurality of insulating films 17 made of a silicon oxide film formed on the surface of the first drain region 12 in a ring shape, a plurality of ring metal conductor layers 18 for field plates, a plurality of dielectric layers 19, It is composed of conductor layers 20a, 20b and 20c. As is clear from FIG. 2, the annular metal conductor layer 18
Constitutes a field plate facing the first drain region 12 via the insulating film 17. The dielectric layer 19 is disposed so as to cover each field plate conductor layer 18. Connection conductor layer 20a as first capacitive coupling means
Is opposed to the innermost field plate conductor layer 18 via a dielectric layer 19 and is connected to the drain electrode 4. The connection conductor layer 20b as the second capacitive coupling means is provided on the outermost field plate conductor layer 18 with the dielectric layer 19b.
And is connected to the ground electrode 8. The connection conductor layer 20c as the third capacitive coupling means faces the field plate conductor layer 18 and functions as a capacitor series connection member. Conductor layers 20a, 20
b, 20c, the dielectric material 19 and the five field plate conductor layers 18 constitute ten capacitors directly connected to each other, and a series circuit of the ten capacitors forms a series connection of the drain electrode 4 and the ground electrode 8. Connected between them.
The annular conductor layer 18 acts as a field plate,
By making the potential change of the first drain region 12 in the left-right direction in FIG. 1 gentle and giving a uniform electric field strength, it contributes to the improvement of the breakdown voltage.

In the FET as the first semiconductor element 1, when the potential of the drain electrode 4 is set higher than the potential of the source electrode 5, and a gate signal is applied between the gate electrode 7 and the source electrode 5, a channel is formed. An N-type channel is formed on the surface of region 14, and a drain current flows through a path including drain electrode 4, second drain region 13, first drain region 12, N-type channel, source region 15, and source electrode 5. . The first drain region 12 is formed to be relatively thick, has a higher impurity concentration than the P-type substrate region 11, and has the field plate structure 9, so that the drain electrode 4 and the source electrode 5 A relatively high voltage can be applied between
An OSFET can be provided.

[0007]

By the way, the potential of the drain electrode 4 is made higher than the potential of the source electrode 5, and the first PN junction 21 and the first PN junction 21 between the substrate region 11 and the first drain region 12 are formed. The second PN junctions 22 between the first drain region 12 and the channel formation region 14 are in reverse bias states, and a voltage is applied to the gate electrode 7 so that a current flows between the drain electrode 4 and the source electrode 5. When flowing, the two broken lines 23a and 23b in FIG.
A depletion layer is generated in a region sandwiched by. Since the first drain region 12 has a resistance, the potential in the first drain region 12 gradually increases from the channel forming region 14 toward the second drain region 13. Therefore, the depletion layer 23
a and 23b spread the most in the lower part of the first PN junction 21. As a result, the drain current path of the first drain region 12 near the second drain region 13 is greatly narrowed by the depletion layer 23b of the first drain region 12, the resistance of the drain current path increases, and the current Density increases. When a relatively large current flows through a high-resistance current path near the second drain region 13, the intensity of the electric field in this region increases, and when the intensity of the electric field exceeds the maximum electric field intensity of the semiconductor, N Shaped first drain region 12
A large number of electrons accelerated by a high electric field are generated therein, and these collide with crystal grains to generate more electrons, and the number of carriers (electrons) increases at an accelerated rate. The generated majority carriers are sucked into the P-type substrate region 11. Since the P-type substrate region 11 is shared by another adjacent semiconductor element 2, the N-type collector region 16a of the second semiconductor region 2, the P-type substrate region 11 and the P-type channel forming region 14 N-type first drain region 12
And an NPN-type parasitic transistor is formed.
Of majority carriers generated in the first drain region 12
The sink into the substrate region 11 acts as the base current of the parasitic transistor, the parasitic transistor is turned on, and a large current may continue to flow, causing the semiconductor device to be thermally damaged. The voltage at which this thermal breakdown occurs is
Since the voltage is generated at a drain-source voltage lower than a calculated (theoretical) voltage (withstand voltage) between the drain and source when no current flows through the transistor, a high withstand voltage structure as shown in FIG. Nevertheless, it was not possible to increase the withstand voltage in actual use when a current was applied. Such a problem is that when the first drain region 12 and the source region 15 are arranged concentrically around the second drain region 13 in a ring shape, the current density becomes high particularly near the second drain region 13. It becomes more noticeable.

An object of the present invention is to provide a semiconductor device capable of suppressing an increase in current density near the second drain region.

[0009]

SUMMARY OF THE INVENTION In order to solve the above problems and to achieve the above object, the present invention provides a first semiconductor device (1) and a second semiconductor device (1) formed on a common semiconductor substrate (3). Wherein the first semiconductor element (1) is an insulated gate field effect transistor, wherein the semiconductor substrate (3) has a first conductivity type substrate region. (11) and first and second drain regions (12, 1) of a second conductivity type opposite to the first conductivity type.
3), a first conductivity type channel forming region (14), a second conductivity type source region (15), a second conductivity type buried region (31 or 31a or 31b), and the second semiconductor. A semiconductor region (16) for the element (2),
The substrate region (11) is a common substrate for the first and second semiconductor elements (1, 2);
The first drain region (12) has an impurity concentration higher than the impurity concentration of the substrate region (11) and has a portion exposed on one main surface of the semiconductor substrate (3). The second drain region (13) is arranged to have a portion adjacent to the straight region (11), the second drain region (13) has an impurity concentration higher than that of the first drain region (12), and the semiconductor substrate (3) are arranged in an island shape in disposed to be exposed on one main surface and the first drain region (12) and
Central part of the first drain region (12) as viewed in plan
The channel forming region (14) has a portion exposed on one main surface of the semiconductor substrate (3), and is separated from the second drain region (13).
And the source region (15) is disposed adjacent to the drain region (12) of the channel formation region (14).
The channel shape is arranged in an island shape and viewed in plan.
The first drain region (1) through the formation region (14).
2) surrounding the buried region (31)
Has an impurity concentration higher than the impurity concentration of the first drain region (12), is disposed between the substrate region (11) and the first drain region (12), and A portion facing the second drain region (13) via the drain region (12) of
And the drain electrode (4) and the source electrode (5)
A rated voltage is applied between the gate electrode
A voltage is applied to (7) and the drain electrode (4) and the
When a current flows between the source electrode (5) and the source electrode (5),
The substrate region (11) and the buried region (3
A depletion layer formed due to the PN junction (32) between 1)
Is expanded toward the first drain region side by the embedding.
Between the first region (31) and the first drain region (12).
Formed at or near the boundary,
A drain electrode (4) is connected to the drain region (13), a source electrode (5) is connected to the source region (15), and the source region (15) on one main surface of the semiconductor substrate (3). A gate insulating film (6) is provided so as to cover between the first drain region (12) and the first drain region (12), and a gate electrode (7) is disposed on the gate insulating film (6). And a semiconductor device.

[0010] Note that the channel formation region (14) side of the area buried impurity concentration of the portion facing the second drain region of the buried region as shown in claims 2 and 3 (31) (13) (31) It is desirable that the impurity concentration be higher than the impurity concentration of the portion. Further, it is preferable to provide a plurality of field plate conductor layer via the insulating layer (17) over the first drain region as shown in claim 4 (12) (18).

[0011]

According to the invention of each claim, since the impurity concentration of the buried regions (31, 31a, 31b) is set higher than the impurity concentration of the first drain region (12), depletion here. The effect of limiting the spread of the layer is obtained,
The depletion layer does not spread significantly in the drain region (12), and the passage of the drain current in the first drain region (12) can be prevented from being narrowed. As a result,
An increase in current density near the second drain region (13) can be suppressed, and thermal destruction of the semiconductor device can be prevented. According to the second and third aspects of the present invention, the expansion of the depletion layer toward the first drain region can be satisfactorily achieved, and the depletion layer expanding toward the substrate region (11) can be smoothly reduced. can do. Thereby, prevention of thermal destruction and improvement of withstand voltage are achieved satisfactorily. Claims
According to the invention of the fourth aspect , the withstand voltage can be improved satisfactorily with the effect of the field plate.

[0012]

Embodiments and Examples Next, embodiments and examples of the present invention will be described with reference to FIGS. However, FIG.
11, the substantially same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted.

[0013]

FIG. 3 shows the surface of a semiconductor substrate 3 of a semiconductor device according to a first embodiment, and FIG.
It is sectional drawing which shows the part corresponding to the -A line. FIG. 3 shows an N-type collector region 16a, a P-type base region 16b, and an N-type emitter region 16 as semiconductor regions 16 for the second semiconductor device 2 having a smaller power capacity than the first semiconductor device 1.
c is shown. The semiconductor device of the first embodiment shown in FIG. 4 is different from the conventional semiconductor device of FIG.
The configuration is the same as that of FIG. 1 except that 1 is added. The buried region 31 is disposed between the first drain region 12 and the substrate region 11 as is apparent from FIG. 4, and has a second drain region 13 at the center thereof as shown in FIG. It is arranged to include all. More specifically, the buried region 31 is the first
And the second drain region 12, 13 and the source region 15 are arranged concentrically, and the outer peripheral edge is located between the second drain region 13 and the channel forming region 14. The buried region 31 is different from the substrate region 11 in the first region.
And is arranged so as to bite into the drain region 12. Such an arrangement is inevitably caused by diffusing an N-type impurity into a predetermined region on the main surface of the substrate region 11 and epitaxially growing N-type silicon thereon to obtain the first drain region 12.

The buried region 31 is provided to prevent the passage of the drain current in the first drain region 12 from being narrowed by the depletion layer. Therefore, when a rated voltage is applied between the drain electrode 4 and the source electrode 5 and a current flows, an N-type junction caused by a reverse bias of the PN junction 32 between the P-type substrate region 11 and the N-type buried region 31 is formed. The impurity concentration and the thickness (depth) of the N-type buried region 31 are set so that the extent of the expansion of the depletion layer indicated by the broken line 23c on the buried region 31 side is at or near the boundary between the first drain region 12 and the buried region 31. ) Has been determined. If the impurity concentration of the buried region 31 is too low, the depletion layer based on the PN junction 32 fills the buried region 31 and further spreads greatly to the first drain region 12. Passage is narrowed. If the thickness (depth) of the buried region 31 is too small, the buried region 31 is buried by the depletion layer even if the impurity concentration is relatively high, and the first depletion region is largely spread over the first drain region 12. The drain current path in the drain region 12 is narrowed. Therefore, in the present embodiment, the impurity concentration of the substrate region 11 is about 2.5 × 10 ¹⁴ cm ⁻³ , the impurity concentration of the first drain region 12 is about 1 × 10 ¹⁵ cm ⁻³ , and the impurity concentration of the buried region 31 is The concentration is set to about 1.2 × 10 ^{15 to} 2.5 × 10 ¹⁵ cm ⁻³ .

The distance between the extension plane 33 of the PN junction 21 and the second drain region 13 between the P-type substrate region 11 and the N-type first drain region 12 indicated by a broken line in FIG. The thickness (depth) of the first drain region 12 and the buried region 31 is set so that D2 / D1 falls within the range of 1/3 to 2/3 when the distance between the plane 33 and the upper surface of the buried region 31 is D2. Is set.

The N-type buried region 31 has first and second impurity concentration regions 34 and 35 as shown in FIG. The first impurity concentration region 34 at the center of the buried region 31 is arranged so as to face the second drain region 13, and has a circular planar shape. The second impurity concentration region 35 is arranged so as to annularly surround the first impurity concentration region 34,
Impurity concentration region 34 has a lower impurity concentration.
The impurity concentration of the first impurity concentration region 34 is about 2.
5 is a × 10 ¹⁵ cm ^-3, the impurity concentration of the second impurity concentration region 35 is approximately 1.2 × 10 ¹⁵ cm ^-3. In this embodiment, the impurity concentration of the buried region 31 is changed in two steps, but may be changed in three or more steps or continuously.

When forming the buried region 31a having an impurity concentration varying in three steps as shown in FIG. 7, for example, as shown in FIG. A first N-type impurity diffusion layer 41a for forming the first portion 41 is formed, and then a second N-type impurity diffusion layer 42a for obtaining the second portion 42 is formed as shown in FIG. 8A. Next, as shown in FIG. 8C, a third N-type impurity diffusion layer 43a for obtaining a third portion 43 is formed on the first and second N-type impurity diffusion layers 41a.
Is formed on the N-type impurity diffusion layers 41a and 42a.
Thereafter, an N-type semiconductor is epitaxially grown on the substrate region 11 to obtain the buried region 31a of FIG.

Since the depth and impurity concentration of the buried region 31a in FIG. 7 are determined in the same manner as in the buried region 31 in FIG. 4, the same effects as in the first embodiment can be obtained in the second embodiment. Can be.

[0022]

Third Embodiment The semiconductor device shown in FIG. 9 has the same structure as that of FIG. 4 except that the buried region 31 of FIG. 4 is changed to a buried region 31b. The buried region 31b of FIG.
Is composed of a set of a plurality of spherical semiconductor regions 51. Multiple N
The spherical semiconductor regions 51 each have substantially the same impurity concentration. However, the overlapping portions of the plurality of spherical semiconductor regions 51 have a higher impurity concentration than the non-overlapping portions. The plurality of spherical semiconductor regions 51 are densely arranged below the second drain region 13, and are coarsely arranged away from the second drain region 13. Therefore, the average impurity concentration is high in the central region below the second drain region 13, and the average impurity concentration decreases as the distance from the central region decreases. The average thickness (height) and the average impurity concentration of the buried region 31b in FIG. 9 are determined similarly to the buried region 31 of the first embodiment. Thus, the same effects as in the first embodiment can be obtained by the third embodiment in FIG.

[0023]

Fourth Embodiment The semiconductor device shown in FIGS.
A second semiconductor element 2a composed of an FET is provided in place of the second semiconductor element 2 of the first embodiment shown in FIG. 4, and the circular second drain region 13 of the first embodiment is formed into an annular shape. The structure is the same as that of the first embodiment except that the second drain region 13a is modified and the second semiconductor element 2a is disposed inside the second drain region 13a. The second schematically shown in FIGS. 10 and 11
The semiconductor element 2a has a P-type channel forming region 61, an N ^{+ -type} source region 62, an N ⁺ -type drain region 63, a gate insulating film 64, a source electrode 65, a drain electrode 66, and a gate electrode 67. The P-type channel formation region 61 is formed in the N-type first drain region 12 in an island shape.
The source region 62 and the drain region 63 are formed in the P-type channel formation region 61 in an island shape. Source electrode 6
5 is connected to the source region 62, the drain electrode 66 is connected to the drain region 63, and the gate electrode 67 is disposed on the gate insulating film 64. Even in the case of such a configuration, an increase in current density in the first drain region 12 is suppressed by configuring the first semiconductor element 1 in the same manner as in the first embodiment. Thereby, it is possible to prevent majority carriers from flowing from the first drain region 12 of the first semiconductor element 1 to the P-type channel formation region 61 of the second semiconductor element 2a, and the same as in the first embodiment. The effect is obtained.

[0024]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) In FIG. 9, the buried region 31b is composed of a combination of a large number of spherical semiconductor regions 51. Instead, the buried region 31b is composed of a combination of a plurality of planar semiconductor regions or a combination of a planar semiconductor region and a spherical semiconductor region. Can be configured. (2) In each embodiment, the buried regions 31, 31a, 31
b has the highest impurity concentration at the central portion facing the second drain region 13, and the impurity concentration decreases as the distance from the region increases, but all of the regions 31, 31 a, and 31 b are the same as these central portions. It can be an impurity concentration. (3) Although a remarkable effect can be obtained by adopting the cylindrical structure as in each embodiment, a structure in which the left half or the right half of the second drain region 13 is removed may be employed. (4) In the third embodiment shown in FIG. 9, instead of the spherical semiconductor region 51, the second drain region 1
An annular semiconductor region is provided around the center 3, and the cut surface of the annular semiconductor region can be made to coincide with the position of the spherical semiconductor region 51 in FIG. 9.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a conventional semiconductor device.

FIG. 2 is an enlarged sectional view showing a part of the field plate structure of FIG. 1;

FIG. 3 is a plan view showing a part of the surface of the semiconductor substrate of the semiconductor device according to the first embodiment of the present invention.

FIG. 4A of the semiconductor device according to the first embodiment of the present invention;
It is sectional drawing which expands and shows the part corresponding to the -A line.

FIG. 5 is a cross-sectional view illustrating an embedded region of FIG. 4 and its vicinity.

FIG. 6 is a cross-sectional view for explaining a method of forming a buried region in FIG.

FIG. 7 is a sectional view showing a semiconductor device according to a second embodiment of the present invention in the same manner as in FIG. 4;

8 is a cross-sectional view for explaining a method of forming the buried region in FIG.

FIG. 9 is a sectional view showing a semiconductor device according to a third embodiment of the present invention in the same manner as in FIG.

FIG. 10 is a plan view showing a second semiconductor element of a semiconductor substrate of a semiconductor device according to a fourth embodiment of the present invention and the vicinity thereof;

FIG. 11 is a cross-sectional view showing the second semiconductor element of the fourth embodiment and its vicinity at a portion corresponding to line BB in FIG. 10;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st semiconductor element 2 2nd semiconductor element 3 Semiconductor base 11 Substrate area 12 1st drain area 13 2nd drain area 14 Channel formation area 15 Source area 31 Embedded area

Continued on the front page (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/8234 H01L 27/088 H01L 29/78 H01L 21/336

Claims (4)

(57) [Claims] 1. A semiconductor device comprising: a first semiconductor element (1) and a second semiconductor element (2) formed based on a common semiconductor substrate (3), wherein the first semiconductor element (1) is insulated. A semiconductor device that is a gate type field effect transistor, wherein the semiconductor substrate (3) includes a substrate region (11) of a first conductivity type and a first region of a second conductivity type opposite to the first conductivity type.
And a second drain region (12, 13), a channel formation region (14) of the first conductivity type, a source region (15) of the second conductivity type, and a buried region (31 or 3) of the second conductivity type.
1a or 31b) and a semiconductor region (16) for the second semiconductor device (2), wherein the substrate region (11) is provided with the first and second semiconductor devices (1, 2). Wherein the first drain region (12) has an impurity concentration higher than the impurity concentration of the substrate region (11) and is exposed on one main surface of the semiconductor substrate (3). And the second drain region (13) has an impurity concentration higher than the impurity concentration of the first drain region (12). the look one is disposed so as to be exposed to the main surface are and are arranged in an island shape in said first drain region (12) and in a plan view of and the semiconductor body has a concentration (3) first The drain area
The channel forming region (14) is disposed in a central portion of the region (12),
The source region (15) is disposed so as to have a portion exposed to one of the main surfaces and to be separated from the second drain region (13) and adjacent to the first drain region (12). The channel forming region (1)
4) The channel is arranged in an island shape and viewed in plan.
The first drain region via a drain formation region (14).
The buried region (31) has an impurity concentration higher than that of the first drain region (12), and is embedded with the substrate region (11). The second drain region (13) is disposed between the first drain region (12) and the second drain region (13) via the first drain region (12).
Has a portion facing and said drain electrode (4)
When a rated voltage is applied between the source electrode (5) and the source electrode (5),
In both cases, a voltage is applied to the gate electrode (7),
A current flows between the in-electrode (4) and the source electrode (5).
When flowing, the substrate region (11) and the
Based on the PN junction (32) between the buried region (31)
Of the depletion layer generated in the first drain region side
The buried region (31) and the first drain
The shape should be limited to or near the boundary with the area (12).
Forming a drain electrode (4) on the second drain region (13).
Is connected to the source region (15), and a source electrode (5) is connected to the source region (15) and the first drain region (12) on one main surface of the semiconductor substrate (3). A gate insulating film (6) is provided so as to cover the gap, and a gate electrode (7) is formed on the gate insulating film (6).
Wherein the semiconductor device is disposed. 2. The buried region (31 or 31a or 31b) includes a channel forming region (14) and a second drain region in addition to a first portion facing the second drain region (13). (13) between the first
A second portion adjacent to the drain region (12),
The first portion of the average impurity concentration is characterized in that it is set higher than the average impurity concentration of said second portion Claim 1 Symbol mounting semiconductor device. 3. The buried region (31a or 31b)
Claim 2 in which the impurity concentration of the second portion of is characterized in that it decreases stepwise or continuously in the direction of the channel forming region from said second drain region (13) (14) 13. The semiconductor device according to claim 1. 4. A ground electrode (8) connected to a portion of the channel forming region (14) remote from a portion where the gate insulating film (6) is arranged; An insulating film (17) formed on a surface between a second drain region (13) and the channel forming region (14); and a plurality of field plate conductors disposed on the insulating film (17). A layer (18); first coupling means for capacitively coupling the one of the plurality of field plate conductor layers (18) closest to the drain electrode (4) to the drain electrode (4); Second coupling means for capacitively coupling one of the plurality of field plate conductor layers (18) farthest from the drain electrode (4) to the ground electrode (8); and the plurality of field plate conductors 4. The semiconductor device according to claim 1, further comprising third coupling means for sequentially capacitively coupling the layers.