JP3316537B2 - Method for manufacturing field effect transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor made of a compound semiconductor and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIG. 9 is a sectional view showing an example of the structure of a conventional field effect transistor made of a compound semiconductor.
In FIG. 9, this field-effect transistor is composed of an undoped InAlAs layer 82 having a thickness of 2000 °, an undoped InGaAs layer 83 having a thickness of 150 °, and an undoped film formed on a semi-insulating semiconductor substrate 81 formed of InP. 2
0 ° InAlAs layer 84 and 1 × 10 ¹⁹ cm ^{−3 of} Si
Doped n-type InAlAs layer 85 having a thickness of 50 °
And an undoped InAlAs layer 86 having a thickness of 150 °
And a 150 ° -thick InAlAs layer 87 doped with 1 × 10 ¹⁹ cm ^{−3 of} Si to form an n-type, and 1 × 10 ¹⁹ c of Si
m- ³ doped n-type InGaAs with a thickness of 150 °
The layers 88 are sequentially stacked to form a semiconductor multilayer structure.

In this semiconductor multilayer structure, a part of the semiconductor multilayer structure is at least InAlAs
The window-shaped gate region 9 is removed to a depth reaching the layer 86.
3 is formed, and a gate Schottky electrode (hereinafter, referred to as a gate electrode) 89 is formed on the bottom surface of the gate region 93.
Are formed, and a source ohmic electrode (hereinafter, referred to as a source electrode) 90 and a drain ohmic electrode (hereinafter, referred to as a drain electrode) 91 are formed on both sides of the gate electrode 89 on the InGaAs layer 88, respectively. .

In order to operate the field effect transistor having the above-described structure, the voltage applied to the gate electrode 89 is changed to change the concentration of electrons immediately below the gate electrode 89 so that the source electrode 90 is switched to the drain electrode. The flow rate of electrons flowing to 91, that is, the drain current is changed.

[0005]

However, the field effect transistor thus configured has the following problems. (1) As the drain voltage is increased, a phenomenon called a kink occurs in which the drain current sharply increases near a certain voltage. FIG. 10 is a cross-sectional view of a field-effect transistor for explaining the kink manifestation mechanism. First, as shown in FIG. 10A, a depletion layer 95 spreads over the surface of the undoped InAlAs layer 86 below the gate region 93, and the thickness of the depletion layer 95 can be changed by the voltage of the gate electrode 89.

Here, the source electrode 9 is connected to the drain electrode 91.
When a positive voltage (hereinafter referred to as a drain voltage) with respect to 0 is applied, electrons move from the source electrode 90 side to the drain electrode 9.
Although it is accelerated to the first side, the n-type doped InGaAs layer 88 and the n-type doped InAlAs layer 87 are also removed under the gate region 93, so that the channel resistance 97 is provided immediately below the gate, Area 92 on both sides
A source resistance 96 and a drain resistance 98 exist directly below the gate, respectively, to restrict the flow of electrons.

Here, as the drain voltage is increased, the accelerated electrons 99 have a high energy as shown in FIG.
Collisions with the valence electrons of the semiconductor atoms in the s layer 83 cause the free electrons 1
A pair of 00 and a hole 101 is generated. The free electrons 100 generated in this manner are supplied to the drain electrode 9
1 and goes out of the transistor, but the holes 101 are undoped InGa because the surroundings are n-type or semi-insulating.
It remains on the source electrode side, particularly under the gate electrode, in the As layer 83, and eventually recombines with electrons and disappears.

However, when the drain voltage is further increased, the frequency of generation of electron-hole pairs exceeds the frequency of holes that recombine with electrons and disappears, and as shown in FIG. The accumulation of holes 101 in layer 83 occurs. When the holes 101 accumulate in this manner, electrons in the channel increase due to a decrease in the electrostatic potential of the channel, the source resistance 96 decreases, and the threshold voltage also decreases. Kink occurs.

(2) If kink occurs, the drain withstand voltage decreases. This is due to the accumulation of holes described in (1) above,
Although the drain current increases, as a result, the generation of holes due to impact ionization increases, and the hole accumulation is further accelerated. This repetition causes the drain current to increase sharply,
The field effect transistor is destroyed.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a field effect transistor capable of avoiding a kink and a decrease in withstand voltage due to the accumulation of holes and a method of manufacturing the same. Is to provide.

[0011]

[Means for Solving the Problems]

In order to achieve the above object, a method of manufacturing a field effect transistor according to the present invention comprises a step of forming a compound semiconductor layer having an n-type conductive channel layer on a semi-insulating substrate, and a step of forming an entire surface of the compound semiconductor layer. Forming a high-melting-point metal thin film, etching a region that is to be a high-concentration p-type impurity region of the high-melting-point metal thin film, and introducing p-type impurities into the compound semiconductor layer using the high-melting-point metal thin film as a mask. Forming a high-concentration p-type impurity region, forming a high-melting point metal thin film into an electrode pattern of a source electrode and a drain electrode, forming a high-concentration p-type impurity region, a source electrode pattern, a drain electrode pattern, and an n-type Ohmic electrodes, source electrodes,
Forming a drain electrode and a gate electrode.

[0013]

According to the present invention, an n-type conductive channel layer is provided.
That the compound semiconductor layer is provided a high-concentration p-type impurity substance area, this high by providing the concentration p-type impurity substance area ohmic electrode in contact with a hole of a semi-insulating substrate generated in the n-type conductivity channel layer the high-concentration p-type impurity material with draw the side
Through realm, effectively taking out the semi-insulating substrate outside via an ohmic electrode.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings . Figure 1 is a diagram illustrating a first configuration example of a field-effect transistor manufactured Ri by the present invention, FIGS. 1 (a) plan view seen from above, FIG. 1 (b) FIGS. 1 (a) A-
It is sectional drawing of the A 'line. In FIG. 1, a semi-insulating substrate 1
An undoped InAlAs layer 2 and a p-type doped In
AlAs layer 3, undoped InAlAs layer 4, undoped InGaAs layer 5, undoped InAlAs layer 6, n
-Doped InAlAs layer 7, undoped InAlAs layer 8, n-doped InAlAs layer 9, and n-doped InAlAs
The GaAs layers 10 are sequentially stacked to form a semiconductor multilayer structure. Each of the layers 2 to 10 on the semi-insulating substrate 1 forms a compound semiconductor layer.

On the semiconductor multilayer structure, a part of the semiconductor multilayer structure is at least InAlA
A window-shaped gate region is formed by being removed to a depth reaching the s layer 8, and a gate Schottky electrode (hereinafter, referred to as a gate electrode) 11 is formed on the bottom surface of the gate region. Further, the gate electrode 1 on the InGaAs layer 10
A source ohmic electrode (hereinafter, referred to as a source electrode) 12 and a drain ohmic electrode (hereinafter, referred to as a drain electrode) 13 are formed at positions on both sides of 1. A part of the semiconductor multilayer structure has a high concentration of p-type impurity of about 1 × 10 ²⁰ cm ⁻³ by Zn diffusion or the like at a depth that penetrates these layers 4 to 10 from the surface and reaches the InAlAs layer 3. Highly doped p-type doped region 1
4, and an ohmic electrode 15 is formed on the high-concentration p-type doped region 14.

In order to operate the field effect transistor having the above-described structure, the voltage applied to the gate electrode 11 is changed to change the electron concentration immediately below the gate electrode 11, so that the source electrode 12 changes to the drain electrode 13. Change the drain current flowing to the At the same time, the ohmic electrode 15 connected to the high-concentration p-type doped region 14 is grounded, so that the accumulated holes can be emitted out of the field effect transistor.

According to such a configuration, the p-type doped In
By providing the AlAs layer 3, as shown in FIG. 2, the electrostatic potential A for electrons becomes larger on the semi-insulating substrate 1 side and smaller on the gate electrode 11 side as compared with the electrostatic potential B in the conventional configuration. Thereby, the holes 101 accumulated in the undoped InGaAs layer 5 where the conductive channel exists move to the p-type doped InAlAs layer 3 having a lower potential for the holes. Further, the ohmic electrode 1 in contact with the high-concentration p-type doped region 14
5 by applying a negative voltage to the p-type doped InA.
The holes that have moved into the lAs layer 3 are highly doped p-type doped regions 1.
4, the electrons are emitted from the ohmic electrode 15 to the outside of the field-effect transistor, and the accumulation of holes can be prevented.
Therefore, kink can be suppressed and a decrease in withstand voltage can be prevented.

FIG. 3 is a diagram showing the drain current-drain voltage characteristics of the field effect transistor thus configured. In the drawing, as shown by the dotted line, even at the threshold value where the kink has conventionally occurred in the drain current-drain voltage characteristic, good characteristics without kink can be obtained as shown by the solid line in the drawing. Further, a higher breakdown voltage can be obtained as compared with a conventional field effect transistor.

FIG. 4 is a diagram including a cross section and a partial plane in each step for explaining the embodiment of the method for manufacturing the field effect transistor described in FIG. In these figures,
First, as shown in FIG. 4A, after forming a semiconductor multilayer structure 32 on a semi-insulating substrate 31, a high melting point metal thin film 33 such as WSiN is deposited. Here, the semiconductor multilayer structure 32 is undoped as shown in FIG.
InAlAs layer 2 having a thickness of 100 ° and Be doped into a p-type by doping 1 × 10 ¹⁸ cm ^-3 to form an InAlAs layer 3 having a thickness of 100 °.
An undoped InAlAs layer having a thickness of 50 °, an undoped InGaAs layer having a thickness of 150 °, an undoped InAlAs layer having a thickness of 20 ° and Si having a thickness of 1 × 10 ¹⁹ cm ^−3.
A doped n-type InAlAs layer 7 having a thickness of 50 °
Undoped InAlAs layer 8 with a thickness of 150 °, n-type doped with 1 × 10 ¹⁹ cm ^{−3 of} Si to form n-type InAlAs layer 9 with 150 ° thickness and doped with 1 × 10 ¹⁹ cm ^{−3 of} Si to form an n-type The InGaAs layer 10 having a thickness of 150 ° is formed by laminating them in that order by, for example, the MBE method.

Next, as shown in FIG. 4B, the refractory metal thin film 33 deposited on the semiconductor multilayer structure 32 is formed on a portion corresponding to the high-concentration p-type doped region 14 by, for example, a reactive ion etching method. The window 34 is opened. Next, FIG.
As shown in (c), using the refractory metal thin film 33 having the window 34 as a mask, for example, about 1 × by Zn diffusion or the like.
A high concentration p-type doped region 35 is formed by doping a high concentration p-type impurity of 10 ²⁰ cm ^-3 . Next, as shown in FIG. 4D, the refractory metal thin film 33 is removed except for the necessary portions by, for example, reactive ion etching, and the source electrode pattern 33S and the drain electrode pattern 33D are removed.
To form Next, as shown in a sectional view of FIG. 4E and a plan view of FIG. 4F, isolation between elements is performed by, for example, wet etching.

Next, as shown in FIG. 4 (g), for example, Ti / Ti is formed on the semi-insulating substrate 31 on which the semiconductor multilayer structure 32 is formed.
Using a highly electron conductive metal such as Pt / Au, for example, by vapor deposition or the like, the source electrode pattern 33S and the drain electrode pattern 33D are brought into contact with the source electrode 36, the drain electrode 37 and the heavily doped p-type doped region 35, respectively, not shown. An ohmic electrode is formed. Next, a gate electrode 39 is formed between the source electrode pattern 33S and the drain electrode pattern 33D as shown in the sectional view of FIG. 4H and the plan view of FIG. At this time, a portion of the semiconductor multilayer structure 32 is at least partially removed from the surface by the In in FIG.
A window-shaped gate region is formed by being removed to a depth reaching the AlAs layer 8, and a gate electrode 39 is formed on the bottom surface of the gate region by using, for example, a highly electron conductive metal such as Ti / Pt / Au. It is formed by such as. In addition,
In FIG. 4I, reference numeral 38 denotes an ohmic electrode in contact with the high-concentration p-type doped region 35 formed in the previous step (shown in FIG. 4G).

FIG. 5 is a diagram illustrating a second configuration example of a field-effect transistor manufactured Ri by the present invention, FIGS. 5 (a)
5A is a plan view as viewed from above, and FIG.
FIG. 2 is a cross-sectional view taken along the line A ′, and the same portions as those in FIG. 1 described above are denoted by the same reference numerals, and description thereof will be omitted. 5 is different from FIG. 1 in that a high concentration p-type doped region 14 is formed under a source electrode 12 without being provided with an electrode in contact with the high concentration p-type doped region 14 and is electrically connected. ing. According to such a configuration, holes are generated in the source electrode 12.
Recombination with the electrons supplied from the substrate, and an effect of extracting holes can be expected.

FIGS. 6A to 6C are cross-sectional views showing steps of a method for manufacturing the field effect transistor shown in FIG. The manufacturing steps shown in these figures are almost the same as those in the above-described manufacturing method shown in FIG.

The tail, in the second configuration example described above, although the high-concentration p-type doped region 14 has been described the case of providing only under source electrode 12, a third configuration example of only under drain electrode 13 It may be provided, or may be provided under both the source electrode 12 and the drain electrode 13. Here, when the high-concentration p-type doped region 14 is provided only under the drain electrode 13, holes are injected, contrary to the second configuration example. become. Therefore, improvement of withstand voltage cannot be expected,
The occurrence of kink can be suppressed.

When the high-concentration p-type doped region 14 is provided under both the source electrode 12 and the drain electrode 13, there is an intermediate effect between the two. In other words, the suppression of kink and the improvement of the withstand voltage to some extent can be expected, and the source and drain have a symmetrical structure, so that an advantageous effect on the design of the integrated circuit pattern can be obtained.

To operate the field effect transistor thus configured, the voltage applied to the gate electrode 11 is changed to change the electron concentration immediately below the gate electrode 11, and the source electrode 12 to the drain electrode 13 Change the drain current flowing to the The accumulated holes can be released from the p-type doped InAlAs layer 3 to the outside of the field-effect transistor through the highly-doped p-type doped region 14 by diffusion.

The field effect transistor manufactured according to the present invention
In the fourth configuration example of the star , Be is 1 × 10 ¹⁸ c in FIG.
m- ³ doped p-type InAlAs with a thickness of 100 °
Layer 3 and undoped InAlAs layer 4 having a thickness of 50 °
Is a field-effect transistor having a structure from which is removed. According to such a configuration, the effect of releasing the accumulated holes is slightly reduced as compared with the third configuration example , but the high-concentration p-type doped region 14 can suppress the accumulation of holes.

Field Effect Transistor Made According to the Invention
In the fifth configuration example of the star , Be is 1 × 10 ¹⁸ c in FIG.
m- ³ doped p-type InAlAs with a thickness of 100 °
Layer 3 and undoped InAlAs layer 4 having a thickness of 50 °
Is a field-effect transistor having a structure from which is removed. According to such a configuration, the effect of releasing the accumulated holes is slightly reduced as compared with the second configuration example , but the high-concentration p-type doped region 14 can suppress the accumulation of holes.

[0029] (Reference Example 1) FIG. 7 is a sectional view showing a configuration of a reference example 1 related to field effect transistors fabricated Ri by the present invention. In FIG. 7, reference numeral 41 denotes a semi-insulating substrate such as GaAs;
Is, for example, a p-type doped layer doped with Be at 1 × 10 ¹⁷ cm ⁻³ , and 43 is, for example, n doped with Si at 1 × 10 ¹⁸ cm ^−3.
The n-type conductive channel 43 is in contact with the gate electrode 45. 44 is 5 × 1 of Si.
This is an n ⁺ layer doped with 0 ¹⁸ cm ⁻³ , and the n ⁺ layer 44 is in contact with the source electrode 46 and the drain electrode 47.
Under the source electrode 46, for example, Zn is 1 × 10 ^20.
A high concentration p-type doped region 48 doped with cm ^-3 is formed to a depth reaching the p-type doped layer 42.

FIGS. 8A to 8C are cross-sectional views illustrating steps in the method for manufacturing the field-effect transistor shown in FIG. In these figures, first, as shown in FIG. 8 (a), p
A p-type doped layer 52 is formed by doping a p-type impurity. Next, as shown in FIG. 8B, an n-type conductive channel 53 is formed on the p-type doped layer 52 by doping an n-type impurity by, for example, ion implantation. Next, as shown in FIG. 8C, a refractory metal thin film 54 such as WSiN is formed on the n-type conductive channel 53. Next, as shown in FIG. 8D, an opening 55 is formed in the refractory metal thin film 54 at a portion corresponding to the above-described high-concentration p-type doped region 48 by, for example, reactive ion etching.

Next, as shown in FIG.
The refractory metal thin film 54 on which
doping a high concentration p-type impurity by diffusion of n,
A heavily doped p-type doped region 56 is formed. Next, unnecessary portions of the refractory metal thin film 54 are removed by, for example, reactive ion etching or the like, and a gate electrode 57 is formed as shown in FIG. Next, as shown in FIG. 8 (g), an n-type impurity is doped by, for example, ion implantation or the like, and heat treatment is performed at about 800 ° C. to form an n ⁺ layer 58. Next, for example, as shown in FIG.
Source electrode 59 by, for example, vapor deposition using
And a drain electrode 60 is formed.

In order to operate the field effect transistor thus configured, the voltage applied to the gate electrode 45 is changed in FIG.
By changing the concentration of the electron immediately below, the drain current flowing from the source electrode 46 to the drain electrode 47 is changed. The accumulated holes are diffused into the p-type doped layer 42 by diffusion.
From the field effect transistor through the heavily p-doped region 48.

REFERENCE EXAMPLE 2 Reference example 2 is a field-effect transistor having the structure of reference example 1 (FIG. 7) except that the p-type doped layer 42 is omitted. According to such a configuration, the effect of releasing the accumulated holes is slightly reduced as compared with Reference Example 1 , but the high concentration p
The accumulation of holes can be suppressed by the mold doping region 48.

[0034]

As described above, according to the field effect transistor of the present invention, good characteristics without kink can be obtained even at the threshold at which kink has occurred in the drain current-drain voltage characteristics. Further, a field effect transistor having a higher withstand voltage than that of the conventional field effect transistor can be obtained. Therefore, it can be applied to various integrated circuits of high speed, high frequency and low noise.

[Brief description of the drawings]

1 (a) is a plan view illustrating a first configuration example of a field-effect transistor manufactured Ri by the present invention, (b) is a cross-sectional view of line A-A 'of (a).

2 is a diagram showing the band structure of the I Ri field effect transistors fabricated in the present invention.

[3] The drain current of I Ri field effect transistors fabricated in the present invention - is a diagram showing the drain voltage characteristic.

FIG. 4 is a cross-sectional view for explaining one embodiment of a method for manufacturing the field-effect transistor shown in FIG.

5 (a) is a plan view illustrating a second configuration example of a field-effect transistor manufactured Ri by the present invention, (b) is a cross-sectional view of line A-A 'of (a).

6 is a cross-sectional view for describing one embodiment of a method for manufacturing the field-effect transistor shown in FIG.

7 is a cross-sectional view illustrating the configuration of the reference example associated with the field-effect transistor manufactured Ri by the present invention.

8 is a cross-sectional view for explaining one example of a method for manufacturing the field-effect transistor shown in FIG.

FIG. 9 is a cross-sectional view illustrating a configuration of a conventional field-effect transistor.

FIG. 10 is a cross-sectional view illustrating a kink generation phenomenon in the field-effect transistor shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semi-insulating substrate, 2 ... Undoped InAlAs layer, 3
... p-type doped InAlAs layer, 4 ... undoped InAl
As layer, 5 ... undoped InGaAs layer, 6 ... undoped InAlAs layer, 7 ... n-type doped InAlAs layer, 8
... Undoped InAlAs layer, 9 ... n-type doped InAl
As layer, 10 n-type doped InGaAs layer, 11 gate electrode, 12 source electrode, 13 drain electrode, 14
... High-concentration p-type doped region, 15 ... Ohmic electrode, 31
... Semi-insulating substrate, 32 ... Semiconductor multilayer structure, 33 ... High melting point metal thin film, 33S ... Source electrode pattern, 33D ... Drain electrode pattern, 34 ... Window, 35 ... High concentration p-type doped region, 36 ... Source electrode, 37 ... Drain electrode, 38 ...
Ohmic electrode, 39 gate electrode, 41 semi-insulating substrate, 42 p-type doped layer, 43 n-type conductive channel, 4
4 ... n ⁺ layer, 45 ... gate electrode, 46 ... source electrode, 4
7 ... drain electrode, 48 ... high concentration p-type doped region, 51
... semi-insulating substrate, 52 ... p-type doped layer, 53 ... n-type conductive channel, 54 ... high melting point metal thin film, 55 ... opening, 56 ...
High-concentration p-type doped region, 57 gate electrode, 58 n ⁺
Layer, 59: source electrode, 60: drain electrode.

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-267345 (JP, A) JP-A-4-5833 (JP, A) JP-A-3-278544 (JP, A) 283553 (JP, A) JP-A-62-13063 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/338 H01L 29/778-29/812

Claims (1)

(57) [Claims] 1. A step of forming a compound semiconductor layer having an n-type conductive channel layer on a semi-insulating substrate, and forming a refractory metal thin film on the entire surface of the compound semiconductor layer.
Process and a high-concentration p-type impurity region of the refractory metal thin film
Etching the region, and the compound semiconductor layer using the refractory metal thin film as a mask.
To form a high concentration p-type impurity region by introducing a p-type impurity into
Step of forming the refractory metal thin film on a source electrode and a drain electrode.
Processing the electrode pattern, forming the high-concentration p-type impurity region, the source electrode pattern,
The in-electrode pattern and the n-type conductive channel layer
Ohmic electrode, source electrode, drain electrode and
Manufacturing a field effect transistor and having a step of forming a fine gate electrode
Method.