JP4836334B2 - Compound semiconductor device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a compound semiconductor device and a method for manufacturing the same, and particularly to a GaAs-based MESFET that is expected to be used as a high-power device for a base station in mobile communication.
[0002]
[Prior art]
High power is required for base station devices for mobile communications, and GaAs-based MESFETs are attracting attention as semiconductor devices that meet this demand.
In order to put this GaAs-based MESFET into practical use, it is necessary to improve the power characteristics, and various contrivances have been made to increase the withstand voltage. As specific examples, the following two types have been devised. Has been.
[0003]
(Conventional example 1)
FIG. 5 is a cross-sectional view showing a schematic configuration of a GaAs-based MESFET of Conventional Example 1.
This MESFET is a so-called GaAs LD-MESFET (Lateral-Diffused Semiconductor Field-Effect Transistors), adopts a structure such as Si LD-MOSFET, and draws holes generated by impact ionization from the source 101 side. It is configured. Thereby, it is possible to suppress the electric field concentration at the end of the gate 103 on the drain 102 side (see Japanese Patent Application Laid-Open No. 61-267369).
[0004]
(Conventional example 2)
FIG. 6 is a cross-sectional view showing a schematic configuration of a GaAs-based MESFET of Conventional Example 2.
In this MESFET, a field plate electrode 105 formed by sequentially stacking Pt and Au is provided on an insulating film 104 such as SiN formed between a gate 103 and a drain 102, and a negative voltage is applied to the field plate electrode 105. Is applied to widen the depletion layer. This suppresses electric field concentration at the end of the gate 103 on the drain 102 side and suppresses impact ionization to achieve high breakdown voltage (Asano et al. Extended Abstracts of Solid State Device and Materials, Hiroshima, Japan, 1998, p. 392).
[0005]
[Problems to be solved by the invention]
However, the conventional GaAs-based MESFET has the following problems.
[0006]
In the case of Conventional Example 1, since a high-density surface level exists on the GaAs surface, alloy ohmic contact must be adopted, and metal diffusion and different dopant sources (for example, AuGe, p to n-GaAs) Since it is necessary to use (AuZn) for -GaAs, it is necessary to form the p ⁺ layer 106 and the n ⁺ layer 107 apart from each other as shown in FIG. For this reason, in the case of Conventional Example 1, the transistor size is large, and there is a drawback in terms of high integration.
[0007]
According to Japanese Patent Application Laid-Open No. 61-267369, Au ⁺ can be contacted to the p ⁺ layer 106, which is a pn junction between the n ⁺ layer 107 doped with Ge and the p ⁺ layer 106. Since interface tunneling is used, the contact resistivity tends to be high, which is a problem.
[0008]
In the case of Conventional Example 2, since the interface state density of SiN / GaAs is high, a negative high voltage must be applied to widen the depletion layer. For this reason, there is a problem that power consumption increases and drain current and transconductance decrease.
[0009]
Here, if a field plate electrode is provided on an insulating film capable of reducing the interface state density, the channel layer under the electrode can be modulated at a low voltage, and power consumption can be reduced. In addition, if holes generated by impact ionization can be extracted from the field plate electrode, it is possible to suppress the electric field concentration, so that it is not necessary to widen the depletion layer as in the conventional case, thus reducing the required power, drain current, transconductance. Can be suppressed. However, as shown in FIG. 8, since the structure of the conventional field plate electrode provided in SiN / GaAs is a so-called type I structure, there is a problem that holes cannot be extracted.
[0010]
As described above, in the conventional GaAs-based MESFET, electric field relaxation is attempted by various means to achieve high breakdown voltage, but serious problems such as increase in device size and difficulty in extracting holes are caused. Yes.
[0011]
Therefore, the present invention has been made to solve the above-described problems. In addition to reducing the electric field and achieving a high breakdown voltage, the present invention further reduces the device size and facilitates the extraction of holes, thereby improving reliability. An object of the present invention is to provide an excellent compound semiconductor device having high performance and a method for manufacturing the same.
[0012]
[Means for Solving the Problems]
As a result of intensive studies, the present inventor has conceived the following aspects of the invention.
[0013]
The present invention is a compound semiconductor device in which a second compound semiconductor layer is formed on a first compound semiconductor layer, wherein the second compound semiconductor layer has a barrier against electrons in the conduction band and is positive. barrier to holes having a band structure is not in the valence band, the amorphous layer der made of a compound of 3 group element and 6 group element is, on the second compound semiconductor layer between the gate electrode and the drain electrode, A field plate electrode is provided, and the field plate electrode can extract only holes.
Further, the present invention is a compound semiconductor device in which a second compound semiconductor layer is formed on a first compound semiconductor layer, wherein the second compound semiconductor layer has a barrier against electrons in a conduction band, And an amorphous layer made of a compound of Group 3 and Group 6 elements having a band structure in which a barrier against holes is not in the valence band, and the first compound semiconductor layer has a p-type region and an n-type region. A first metal layer having an adjacent structure and having a high work function formed in a portion corresponding to the p-type region of the second compound semiconductor layer; and the second compound semiconductor layer an electrode having a second metal layer having a work function smaller than that of the first metal layer formed in a portion corresponding to the n-type region, wherein the electrode is mainly a source electrode Form as.
[0014]
In this case, specifically, the three group elements are preferably selected from one selected from Ga, In, and Al.
[0015]
Furthermore, it is preferable that the six group elements are one selected from S, Te, and Se.
[0018]
Furthermore, the present invention is also directed to a method of manufacturing the compound semiconductor device having each of the above configurations.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments to which the present invention is applied will be described in detail with reference to the drawings.
[0020]
(Main principles of the present invention)
First, the main principle of the present invention will be described.
The compound semiconductor device of the present invention has a band structure of a type II structure on the first compound semiconductor layer such as GaAs, in which the barrier to electrons is in the conduction band and the barrier to holes is not in the valence band. It has an amorphous layer made of a compound of a group element and a group 6 element. Here, for convenience, an amorphous GaS layer (a-GaS layer) is taken as an example of the amorphous layer.
[0021]
For example, when an a-GaS layer is formed on a GaAs layer using tertiary butyl gallium sulfacuben [(t-Bu) GaS] ₄ , this GaS / GaAs structure is shown in FIG. As shown, it has a type II structure and has no barrier to holes. For this reason, as shown in FIG. 1B, by using an electrode made of Pt or the like having a high work function, it is possible to secure a contact with the p-GaAs region of the GaAs layer even with non-alloy. Therefore, in this case, a non-alloy ohmic contact can be formed simultaneously (without separating the two) from the p-GaAs region and the n-GaAs region of the GaAs layer, and the transistor size can be greatly reduced.
[0022]
On the other hand, the a-GaS layer functions as an insulating film when the film thickness is 20 nm or more. As shown in FIG. 1A, since the conduction band discontinuity ΔEc is as high as about 1 eV, the a-GaS layer functions as a barrier against electrons, but the type II structure is formed as described above. It does not become a barrier against holes. Therefore, in this case, if a field plate electrode is provided on the a-GaS layer and a negative voltage is applied to the electrode, holes can be easily extracted while expanding the depletion layer as shown in FIG. It becomes.
[0023]
Each embodiment will be specifically described below based on the main principle of the present invention described above.
[0024]
(First embodiment)
In the present embodiment, a non-alloy ohmic GaAs-based LD-MESFET is exemplified as the compound semiconductor device. Here, for the sake of convenience, the structure of the LD-MESFET and its configuration will be disclosed.
[0025]
FIG. 2 is a cross-sectional view showing the method of manufacturing the non-alloy ohmic GaAs-based LD-MESFET according to the first embodiment in the order of steps.
In order to manufacture this LD-MESFET, first, as shown in FIG. 2A, a non-doped GaAs substrate 1 is prepared, and acceleration energy is 120 keV and a dose amount is 5 × 10 5 on the surface layer of the GaAs substrate 1. After ion-implanting Mg under the condition of ¹¹ / cm ² , Si is ion-implanted into the surface layer in the ion-implanted region under the condition of acceleration energy of 40 keV and dose amount of 5 × 10 ¹² / cm ² . Thereby, the p-GaAs region 2 and the n-GaAs region 3 are sequentially formed.
[0026]
Subsequently, the gate electrode 4 is formed. Specifically, a tungsten silicide (WSi) layer (not shown) is deposited and formed by sputtering, and the WSi layer is processed by photolithography and subsequent dry etching. As shown in FIG. The gate electrode 4 is patterned on the GaAs region 3.
[0027]
Subsequently, a photoresist is applied, and a resist mask (not shown) covering a predetermined region on the n-GaAs region 3 including the gate electrode 4 is formed by photolithography. Then, using this resist mask, as shown in FIG. 2C, the acceleration energy is set to 90 keV and the dose to the exposed surface layers of the p-GaAs region 2 and the n-GaAs region 3 (here, the regions serving as ohmic regions). After ion-implanting Si under the condition of 2 × 10 ¹³ / cm ² , activation is performed by applying rapid thermal annealing (RTA) for 10 seconds at 800 ° C., and a pair of n ⁺ -GaAs regions 5 Form.
[0028]
At this time, it is preferable that a predetermined resist mask is formed, and Mg ions are implanted only into a portion serving as a source region under the conditions of an acceleration energy of 90 keV and a dose amount of 2 × 10 ¹³ / cm ² .
[0029]
Thereafter, the surface of the GaAs substrate 1 is irradiated with trisdimethylaminoarsenic in an MBE (molecular beam epitaxial growth) chamber, and the pre-oxide film on the surface is removed at a substrate temperature of 500 ° C.
[0030]
Subsequently, as shown in FIG. 2D, the substrate temperature is set to 350 ° C. in the MBE chamber, and the surface of the GaAs substrate 1 is irradiated with [(t-Bu) GaS] ₄ so as to cover the surface. An a-GaS layer 6 having a thickness of about 15 nm is formed. At this time, the surface of the gate electrode 4 is exposed as shown.
[0031]
Subsequently, the source electrode 7 and the drain electrode 8 are formed.
Specifically, as shown in FIG. 2E, after patterning by photolithography, the Ti film 11, the Pt film 12, and the Au film 13 are evaporated and lifted off, that is, the parts that become the source region and the drain region, that is, a The Ti film 11, the Pt film 12, and the Au film 13 are left in a portion corresponding to each n ⁺ -GaAs region 5 on the −GaS layer 6.
[0032]
Thereafter, the GaAs substrate 1 is annealed at 300 ° C. for 10 minutes. Thereby, a contact resistance of about 10 ⁻⁶ Ω / cm ² is obtained, and ohmic contact with the n ⁺ -GaAs region 5 in the source / drain regions is ensured.
[0033]
Subsequently, as shown in FIG. 2 (f), after patterning by photolithography, the Pt film 14 and the Au film 15 are evaporated and lifted off from the Ti film 11, the Pt film 12 and the Au film 13 only on the source region side. The Pt film 14 and the Au film 15 are left so as to have a shape covering the laminated body and one side surface. At this time, the Pt film 14 and the Au film 15 are laminated only on the portion corresponding to the p-GaAs region 2 on the a-GaS layer 6, and thereby the ohmic contact with the p-GaAs region 2 in the source region. Is secured.
[0034]
Through the above process, the source electrode 7 formed by integrally connecting the stacked body of the Ti film 11, the Pt film 12, and the Au film 13 and the stacked body of the Pt film 14 and the Au film 15 is formed in the drain region in the source region. A drain electrode 8 made of a laminate of a Ti film 11, a Pt film 12, and an Au film 13 is formed.
[0035]
Thereafter, a non-alloy ohmic GaAs-based LD-MESFET is completed through various processes such as formation of a predetermined interlayer insulating film and contact holes.
[0036]
As described above, in the LD-MESFET of the present embodiment, the GaS / GaAs structure is a type II structure and there is no barrier against holes, so that ohmic contact with the p-GaAs region 2 has a high work function Pt. The film 14 is used as an ohmic contact with the n-GaAs region (n ⁺ -GaAs region 5) using the Ti film 11 having a small work function, and the Pt film 14 and the Ti film 11 are brought into contact with each other without being separated from each other. Electrode 7 can be formed. That is, it is possible to sufficiently meet the demand for higher integration by realizing a reduction in transistor size while stably securing ohmic contacts to the p-GaAs region and the n-GaAs region in the source region. Become.
[0037]
(Second Embodiment)
In the present embodiment, an insulating field plate type GaAs MESFET is exemplified as the compound semiconductor device. Here, for the sake of convenience, the structure of the MESFET and its configuration will be disclosed.
[0038]
FIG. 3 is a cross-sectional view showing the method of manufacturing the insulating field plate type GaAs MESFET according to the second embodiment in the order of steps. For the sake of convenience, the same components as those in FIG.
In order to manufacture this LD-MESFET, first, as shown in FIG. 3A, a non-doped GaAs substrate 1 is prepared, the acceleration energy is 40 keV and the dose amount is 4 × 10 4 on the surface layer of the GaAs substrate 1. Si is ion-implanted under the condition of ¹² / cm ² . Thereby, the n-GaAs region 3 is sequentially formed.
[0039]
Subsequently, the gate electrode 4 is formed. Specifically, a tungsten silicide (WSi) layer (not shown) is deposited and formed by sputtering, and the WSi layer is processed by photolithography and subsequent dry etching. As shown in FIG. The gate electrode 4 is patterned on the GaAs region 3.
[0040]
Subsequently, a photoresist is applied, and a resist mask (not shown) covering a predetermined region on the n-GaAs region 3 including the gate electrode 4 is formed by photolithography. Then, using this resist mask, as shown in FIG. 2C, an acceleration energy of 90 keV and a dose amount of 2 × 10 ¹³ are applied to the exposed surface layer of the n-GaAs region 3 (here, a region serving as an ohmic region). After Si is ion-implanted under the condition of / cm ² , a rapid thermal annealing (RTA) treatment is performed for 10 seconds under the condition of 800 ° C. to form a pair of n ⁺ -GaAs regions 5.
[0041]
Thereafter, the surface of the GaAs substrate 1 is irradiated with trisdimethylaminoarsenic in an MBE (molecular beam epitaxial growth) chamber, and the pre-oxide film on the surface is removed at a substrate temperature of 500 ° C.
[0042]
Subsequently, as shown in FIG. 3 (d), the substrate temperature is set to 350 ° C. in the MBE chamber, and the surface of the GaAs substrate 1 is irradiated with [(t-Bu) GaS] ₄ so as to cover the surface. In order to ensure insulation, the a-GaS layer 21 is formed to be relatively thick, and here has a thickness of about 30 nm. At this time, the surface of the gate electrode 4 is exposed as shown.
[0043]
Subsequently, the source electrode 22 and the drain electrode 23 are formed.
Specifically, as shown in FIG. 3 (e), first, wet etching is performed on the portions corresponding to the source region and the drain region of the a-GaS layer 21 using an acid, and the n ⁺ -GaAs region 5 in the portion is subjected to wet etching. To expose the surface.
[0044]
Next, AuGeNi is vapor-deposited as a material on the exposed portion of each n ⁺ -GaAs region 5, and the AuGeNi is alloyed at 450 ° C. At this time, a source electrode 22 and a drain electrode 23 are formed in which ohmic contact is ensured with each n ⁺ -GaAs region 5 in the source region and the drain region.
[0045]
Subsequently, a field plate electrode 24 is formed on the a-GaS layer 21 between the gate electrode 4 and the drain electrode 23.
Specifically, a Pt film 25 and an Au film 26 are sequentially laminated and subjected to photolithography and subsequent dry etching, so that only the Pt film 25 and the Au film 26 are provided between the gate electrode 4 and the drain electrode 23. And the field plate electrode 24 is formed.
[0046]
Thereafter, an insulating field plate type GaAs MESFET is completed through various processes such as formation of a predetermined interlayer insulating film and contact holes.
[0047]
When a negative voltage V is applied to the field plate electrode 24, only holes can be extracted due to the type II structure while expanding the depletion layer. In addition, since holes are pulled out, if the same withstand voltage as in the prior art is sufficient, it is not necessary to widen the depletion layer as in the prior art, so that it can be controlled at a low voltage and low power consumption can be realized. Also, if the depletion layer does not spread much, the drain current and transconductance can be increased.
[0048]
As mentioned above, although each embodiment of the present invention was described, the present invention is not limited to these aspects. For example, the structure of the MESFET of the first embodiment and the structure of the MESFET of the second embodiment are combined. It is also possible.
[0049]
An example of this is shown in FIG.
Here, an a-GaS layer 21 having a thickness of about 30 nm is formed, and a laminated body of a Ti film 11, a Pt film 12, and an Au film 13 and a laminated body of a Pt film 14 and an Au film 15 are integrated in the source region. A source electrode 7 connected to the drain electrode 8 and a drain electrode 8 made of a laminate of a Ti film 11, a Pt film 12, and an Au film 13 are formed in the drain region.
[0050]
In this case, the Pt film 14 having a high work function is used for the ohmic contact with the p-GaAs region 2, and the Ti film 11 having a low work function is used for the ohmic contact with the n-GaAs region (n ⁺ -GaAs region 5). The source electrode 7 is formed by contacting the Pt film 14 and the Ti film 11 without separating them.
[0051]
Further, a field plate electrode 24 made of a laminate of a Pt film 25 and an Au film 26 is formed on the a-GaS layer 21 between the gate electrode 4 and the drain electrode 23.
[0052]
According to this example, in addition to the effects exhibited by the MESFETs according to the first and second embodiments, it is possible to further increase the breakdown voltage.
[0053]
Hereinafter, various aspects of the present invention will be collectively described as supplementary notes.
[0054]
(Appendix 1) A compound semiconductor device in which a second compound semiconductor layer is formed on a first compound semiconductor layer,
The second compound semiconductor layer is an amorphous layer made of a compound of Group 3 and Group 6 elements having a band structure in which a barrier to electrons is in the conduction band and a barrier to holes is not in the valence band. A compound semiconductor device characterized by the above.
[0055]
(Supplementary note 2) The compound semiconductor device according to supplementary note 1, wherein the Group 3 element is one selected from Ga, In, and Al.
[0056]
(Additional remark 3) The said compound 6 element is 1 type chosen from S, Te, Se, The compound semiconductor device of Additional remark 1 or 2 characterized by the above-mentioned.
[0057]
(Supplementary Note 4) The first compound semiconductor layer has a structure in which a p-type region and an n-type region are adjacent to each other,
A first metal layer having a large work function formed in a portion corresponding to the p-type region of the second compound semiconductor layer, and a portion corresponding to the n-type region of the second compound semiconductor layer; 4. The compound semiconductor device according to any one of appendices 1 to 3, further comprising an electrode including the formed second metal layer having a small work function.
[0058]
(Supplementary note 5) The compound semiconductor device according to supplementary note 4, wherein the electrode is a source electrode.
[0059]
(Supplementary Note 6) The compound according to any one of Supplementary Notes 1, 2, 3, and 5, wherein a field plate electrode is provided on the second compound semiconductor layer between the gate electrode and the drain electrode. Semiconductor device.
[0060]
(Supplementary note 7) A method of manufacturing a compound semiconductor device, wherein a second compound semiconductor layer is formed on a first compound semiconductor layer,
The second compound semiconductor layer is an amorphous layer made of a compound of Group 3 and Group 6 elements having a band structure in which a barrier to electrons is in the conduction band and a barrier to holes is not in the valence band. A method for manufacturing a compound semiconductor device.
[0061]
(Supplementary note 8) The method for manufacturing a compound semiconductor device according to supplementary note 7, wherein the Group 3 element is one selected from Ga, In, and Al.
[0062]
(Supplementary note 9) The method of manufacturing a compound semiconductor device according to supplementary note 7 or 8, wherein the element belonging to Group 6 is one selected from S, Te, and Se.
[0063]
(Supplementary Note 10) When forming the first compound semiconductor layer so that the p-type region and the n-type region are adjacent to each other,
A first metal layer having a large work function is provided at a portion corresponding to the p-type region of the second compound semiconductor layer, and a work function is provided at a portion corresponding to the n-type region of the second compound semiconductor layer. The compound semiconductor device according to any one of appendices 7 to 9, wherein a small second metal layer is formed to constitute an electrode having the first and second metal layers. Production method.
[0064]
(Additional remark 11) The manufacturing method of the compound semiconductor device of Additional remark 10 characterized by using the said electrode as a source electrode.
[0065]
(Supplementary note 12) The field plate electrode is formed on the second compound semiconductor layer between the gate electrode and the drain electrode, according to any one of Supplementary notes 7, 8, 9, and 11 A method for manufacturing a compound semiconductor device.
[0066]
【The invention's effect】
According to the present invention, in addition to reducing the electric field and realizing a high breakdown voltage, it is possible to further reduce the device size and facilitate the extraction of holes, thereby realizing an excellent compound semiconductor device with high reliability.
[Brief description of the drawings]
FIG. 1 is a band diagram for explaining the main principle of the present invention.
FIG. 2 is a cross-sectional view showing the method of manufacturing the non-alloy ohmic GaAs-based LD-MESFET according to the first embodiment in the order of steps.
FIG. 3 is a cross-sectional view showing a method of manufacturing an insulating field plate type GaAs MESFET according to a second embodiment in the order of steps.
FIG. 4 is a cross-sectional view showing an example in which the structure of the MESFET of the first embodiment and the structure of the MESFET of the second embodiment are combined.
5 is a cross-sectional view showing a schematic configuration of a GaAs-based MESFET of Conventional Example 1. FIG.
6 is a cross-sectional view showing a schematic configuration of a GaAs-based MESFET of Conventional Example 2. FIG.
7 is a cross-sectional view showing a state in which a p ⁺ layer and an n ⁺ layer are formed apart from each other in the GaAs-based MESFET of Conventional Example 1. FIG.
FIG. 8 is a band diagram for explaining a problem of a GaAs-based MESFET according to Conventional Example 2;
[Explanation of symbols]
1 GaAs substrate 2 p-GaAs region 3 n-GaAs region 4 gate electrode 5 n ⁺ -GaAs region 6, 21 a-GaS layer 7, 22 source electrode 8, 23 drain electrode 11 Ti film 12, 14, 25 Pt film 13 , 15, 26 Au film 24 Field plate electrode

Claims (9)

A compound semiconductor device in which a second compound semiconductor layer is formed on a first compound semiconductor layer,
It said second compound semiconductor layer is in the barrier conduction band for electrons and a barrier against holes having a band structure is not in the valence band, Ri amorphous layer der made of a compound of 3 group element and 6 group elements ,
A field plate electrode is provided on the second compound semiconductor layer between the gate electrode and the drain electrode,
The compound semiconductor device , wherein the field plate electrode can extract only holes . A compound semiconductor device in which a second compound semiconductor layer is formed on a first compound semiconductor layer,
It said second compound semiconductor layer is in the barrier conduction band for electrons and a barrier against holes having a band structure is not in the valence band, Ri amorphous layer der made of a compound of 3 group element and 6 group elements ,
The first compound semiconductor layer has a structure in which a p-type region and an n-type region are adjacent to each other,
A first metal layer having a large work function formed in a portion corresponding to the p-type region of the second compound semiconductor layer, and a portion corresponding to the n-type region of the second compound semiconductor layer; A compound semiconductor device comprising: an electrode including a formed second metal layer having a work function smaller than that of the first metal layer . The compound semiconductor device according to claim 2 , wherein the electrode is a source electrode. 4. The compound semiconductor device according to claim 1, wherein the Group 3 element is one selected from Ga, In, and Al. 5. The 6 group element is S, Te, compound semiconductor device according to any one of claims 1-4, characterized in that the one selected from Se. A method of manufacturing a compound semiconductor device, wherein a second compound semiconductor layer is formed on a first compound semiconductor layer,
The second compound semiconductor layer is an amorphous layer composed of a compound of Group 3 elements and Group 6 elements having a band structure in which a barrier to electrons is in the conduction band and a barrier to holes is not in the valence band ,
Forming a field plate electrode on the second compound semiconductor layer between the gate electrode and the drain electrode;
The method of manufacturing a compound semiconductor device, wherein the field plate electrode is capable of extracting only holes . A method of manufacturing a compound semiconductor device, wherein a second compound semiconductor layer is formed on a first compound semiconductor layer,
The second compound semiconductor layer is an amorphous layer composed of a compound of Group 3 elements and Group 6 elements having a band structure in which a barrier to electrons is in the conduction band and a barrier to holes is not in the valence band ,
In forming the first compound semiconductor layer so that the p-type region and the n-type region are adjacent to each other,
A first metal layer having a large work function is provided at a portion corresponding to the p-type region of the second compound semiconductor layer, and the first metal layer is provided at a portion corresponding to the n-type region of the second compound semiconductor layer. A method of manufacturing a compound semiconductor device , wherein a second metal layer having a work function smaller than that of the first metal layer is formed, and an electrode having the first and second metal layers is formed . 8. The method of manufacturing a compound semiconductor device according to claim 6 , wherein the Group 3 element is one selected from Ga, In, and Al. The method of manufacturing a compound semiconductor device according to claim 6, wherein the element belonging to Group 6 is one selected from S, Te, and Se.

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