JP3316779B2 - Sequence controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequence controller for exchanging input / output information between an I / O space and an internal memory, and more particularly to a sequence controller for not only a real I / O space but also a virtual I / O space.
The present invention relates to a sequence controller capable of accessing the O space.

[0002]

2. Description of the Related Art Conventionally, in the field of factory automation (FA), a sequence controller (programmable controller) for automatically controlling a production system or the like according to a created program has been widely used. The sequence controller includes a system for directly exchanging input / output information with actual input / output devices (hereinafter, referred to as actual I / O) such as switches, relay contacts, motors, and valves. There is a method in which input / output information is exchanged with the internal memory for each scan, and the actual operation is performed on the internal memory. In general, the latter method (this is called a batch refresh method) is mainly used. ing.

In such a batch refresh method, it is necessary to set the correspondence between the internal memory and the real I / O. As a method of setting this correspondence, an actual I / O
According to a method of fixedly determining a correspondence relationship depending on where an I / O card having an interface function with O is mounted in an I / O connector which is an input / output terminal of a controller, and a mounting order of the I / O card. There are a method of determining the value and a method of determining the value based on a mapping table that stores the correspondence between the internal memory and the real I / O. In the method in which the correspondence is fixedly determined according to the mounting position of the I / O card, if the I / O card is mounted in an intermittent manner, the corresponding internal memory position becomes uneven and becomes difficult to handle. . In addition, the method of determining the order of mounting I / O cards allows efficient use of the internal memory. However, if a card is removed in the middle or a card is added later, the correspondence needs to be changed. turn into.

In order to facilitate the setting of the correspondence between the internal memory and the real I / O, a method has been proposed in which a mapping table for storing the correspondence is stored inside the sequence controller. However, in any of the above-mentioned methods, input / output information is exchanged between the internal memory and the real I / O based on the above-mentioned correspondence relationship. I / O
If it was not connected, it could not operate as a controller.

[0005]

As described above, the conventional sequence controller has a problem that unless an actual input / output device is connected, it cannot operate and cannot perform a simulation. . The present invention has been made to solve the above problems, and has as its object to provide a sequence controller capable of performing a simulation without an actual input / output device.

[0006]

SUMMARY OF THE INVENTION A sequence controller according to the present invention comprises a real I / O address for giving an I / O address of an actual I / O device and a virtual I / O for giving an I / O address of a virtual I / O device. address, the virtual I / O address is valid flag that indicates whether valid, as well as have a mapping table for storing a memory address corresponding to the real I / O address and the virtual I / O address, the virtual I /
Ladder program for simulation as O address
Data that functions as virtual I / O devices by executing
Memory address, special instruction for simulation
Work RA functioning as a virtual input / output device by execution
M address or stain equivalent to actual I / O device
The address of the real I / O to which the
It can be set .

[0007]

According to the present invention, input / output information is normally exchanged between an actual input / output device and an I / O memory based on the correspondence between an actual I / O address and a memory address. Then, when the valid flag indicates that the virtual I / O address is valid, the virtual I / O device and the I / O device are connected based on the correspondence between the virtual I / O address and the memory address.
Input / output information is exchanged with the memory.

[0008]

FIG. 1 is a block diagram of a sequence controller showing one embodiment of the present invention. 1 is a program memory that stores a sequence program (ladder program), 2 is a CPU that executes the sequence program stored in the memory 1 and implements a function as a controller,
3 is the internal memory, 3a is the internal memory 3
I / O where input / output information exchanged with O is written
The O memory 3b is a data memory which is also used in executing the sequence program in the memory 3.

Reference numeral 4 denotes a work RAM used when executing a special instruction stored in a ROM (not shown), 5 denotes an I / O connector which is an input / output terminal of a controller, and 6 denotes an I / O connector.
4 is a mapping table that stores a correspondence between an O space and an internal memory.

Next, the operation of such a sequence controller will be described. FIG. 2 is a diagram showing a state where the correspondence between the I / O space and the internal memory is set on the mapping table 6. A is a position on the real I / O space (actually, I / O
A real I / O address indicating the connector number of the O connector 5), and a virtual I indicating a position in a virtual I / O space described later.
/ O address, C is real I / O address A and virtual I / O
An internal memory address indicating a position on the I / O memory 3a corresponding to the address B, and F is a valid flag indicating whether the virtual I / O address B is valid.

Normally, the CPU 2 of the sequence controller performs the real I / O based on the correspondence between the real I / O address A set in the mapping table 6 and the internal memory address C.
The input / output information is exchanged between the / O and the I / O memory 3a. Input information obtained from the real I / O indicated by the real I / O address A, that is, information obtained from input devices such as switches and relay contacts connected to an I / O card (not shown) attached to the I / O connector 5 Is read every scan, and the I / I indicated by the corresponding internal memory address C
The data is written to the position of the O memory 3a. Thus, the CPU
2 can obtain input information from real I / O.

The output information given to the real I / O indicated by the address A, that is, the I / O attached to the connector 5
Information given to output devices such as motors and valves connected to the card is stored in the I / O memory 3 indicated by the memory address C.
The data is written to the position a for each scan and output to the I / O connector 5 indicated by the corresponding address A. Thus, the output information is provided from the sequence controller to the real I / O.

In such exchange of input / output information, when the valid flag F becomes significant (for example, “1”), C
PU2 determines that the virtual I / O address B has become valid. Then, instead of the real I / O address A, the virtual I / O
Using the O address B, the virtual I / O space and the I / O memory 3
The input / output information is exchanged with a. As the virtual I / O space, the data memory 3b, the work RAM 4, the real I / O
O space (here, I / O attached to the I / O connector 5)
A simulator module, which is a type of O card, can be set.

For example, the virtual I /
The address of the data memory 3b is set as the O address B, and a ladder program for simulation such that the data memory 3b functions as a virtual input / output device is stored in the program memory 1. This allows the CPU
2 causes the program stored in the memory 1 to execute,
The input / output information of the virtual input / output device appears on the data memory 3b.

Here, if the valid bit F is made significant, C
The PU 2 has a data memory 3b, which is a virtual I / O, and an I / O
The input / output information is exchanged with the memory 3a. By operating the data memory 3b as a virtual input / output device in this manner, a simulation can be performed only by the CPU 2 of the controller even when the real I / O is not connected to the I / O connector 5.

Similarly, the address of the work RAM 4 is set as the virtual I / O address B,
Stores in the ROM a special instruction for simulation that functions as a virtual input / output device. The special instruction is provided by the maker of the sequence controller as firmware, and the work RAM is a memory used when executing the special instruction and cannot be directly accessed from a ladder program created by a user. Thus, if the valid bit F is made significant while causing the CPU 2 to execute this instruction, the same effect as described above can be obtained.

Further, a simulator module which operates in the same manner as the real I / O is mounted on the I / O connector
The number of the I / O connector 5 to which the simulator module is attached is set as the / O address B. In this case, only by making the valid bit F significant, the CPU 2
Input / output information is exchanged between the simulator module and the I / O memory 3a. As a result, it is possible to perform a simulation assuming an actual operation without changing the sequence program stored in the memory 1, and to debug the program.

[0018]

According to the present invention, the mapping table is extended so that the virtual I / O address and the valid flag can be stored.
Since input / output information is exchanged between the virtual input / output device indicated by the virtual I / O address and the I / O memory indicated by the memory address, a simulation can be performed without an actual input / output device. .

[Brief description of the drawings]

FIG. 1 is a block diagram of a sequence controller showing one embodiment of the present invention.

FIG. 2 is a diagram showing a state where a correspondence between an I / O space and an internal memory is set on a mapping table.

[Explanation of symbols]

1 ... program memory, 2 ... CPU, 3 ... internal memory,
3a I / O memory, 3b data memory, 4 work RAM, 5 I / O connector, 6 mapping table, A actual I / O address, B virtual I / O address,
C: Internal memory address, F: Valid flag.

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-7-56500 (JP, A) JP-A-7-28521 (JP, A) JP-A-6-318106 (JP, A) JP-A-6-318106 289913 (JP, A) JP-A-4-318606 (JP, A) JP-A-63-223903 (JP, A) JP-A-62-99807 (JP, A) (58) Fields investigated (Int. ⁷ , DB name) G05B 19/04-19/05

Claims (1)

(57) [Claims] An input / output device between an input / output device and an I / O memory based on a correspondence relationship between an I / O address indicating a connection position of the input / output device and a memory address indicating a position on the I / O memory. In a sequence controller for exchanging information, a real I / O address giving an I / O address of an actual I / O device, a virtual I / O address giving an I / O address of a virtual I / O device, and a virtual I / O A mapping table for storing a valid flag indicating whether the address is valid, and a memory address corresponding to the real I / O address and the virtual I / O address, wherein the virtual I / O address is
As a virtual input / output device by executing a ladder program
Functioning data memory address, for simulation
Function as virtual I / O devices by executing
Work RAM address or actual input / output device
Real I / O with simulator module equivalent to
Can be set, and when the valid flag indicates that the virtual I / O address is valid , the virtual I / O address is used instead of the real I / O address.
A sequence controller characterized by using an address.