JP3321092B2 - Power semiconductor module - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor module in which a plurality of power semiconductor chips such as diodes, thyristors, transistors and the like are mounted on one metal base.

[0002]

2. Description of the Related Art Welders, uninterruptible power supplies, communication power supplies,
Power supplies such as a charger, a plating power supply, and a motor control rectify an AC power supply using a diode or a thyristor, and convert the rectified DC into a bipolar transistor
High-frequency AC is converted by an inverter using a transistor such as an OSFET or IGBT as a control element. Further, when obtaining a direct current at the output, the high-frequency alternating current is transformed by a transformer, and the transformed alternating current is rectified again using a diode to obtain a direct current. As a result, the power supply device has the feature of being reduced in size.

[0003] In these power supply devices, power semiconductor elements such as diodes, thyristors, and transistors are housed in a single module in the form of a plurality of chips, and are used as power semiconductor modules. FIG. 2 shows a schematic plan view of the power semiconductor module. Numeral 4 is an insulating plate made of ceramics or the like. A wiring pattern of copper foil is formed on one surface of the insulating plate 4 in advance, and copper foil is formed on the entire surface of the other surface. Reference numeral 2 denotes a metal base, on which a solder chip is mounted, and an insulating plate 4 is mounted on the solder chip. Further, cream solder is applied to necessary portions of the wiring pattern of the insulating plate 4, and the power semiconductor chips 26a to 26d, 28a
28d, 30a and 30b are placed and soldered by a reflow furnace.

[0004]

However, a plurality of power semiconductor chips 26a to 26d, 28a to 28d, 30
The area of the insulating plate 4 on which a and 30b are mounted becomes large. Therefore, when soldering the insulating plate 4 and the metal base 2, air or gas does not escape from between the insulating plate 4 and the metal base 2, and as shown by a broken line in FIG. Voids 32a and 32b are generated where solder is not soldered. When the power semiconductor chips 26a, 26b, 28d are located above the voids 32a, 32b, the power semiconductor chips 26
a, 26b, and 28d are generated by the voids 32a and 32d.
b cannot be released through the metal base 2. This causes a problem that the power semiconductor chips 26a, 26b, 28d are damaged.

[0005]

A power semiconductor module according to the present invention comprises a metal base, an insulating plate provided on the metal base and having a wiring pattern formed on one surface thereof, and a soldering to the wiring pattern. A plurality of power semiconductor chips to be used, a resin case bonded to an end of the metal base, and a sealant injected into the resin case and sealing the power semiconductor chip. In the semiconductor module, a high-temperature solder bump equivalent to or slightly larger than the size of the power semiconductor chip is provided on the other surface of the insulating plate below the power semiconductor chip, and the metal base and the insulating plate are connected to each other. The solder is soldered with a low-temperature cream solder lower than the high-temperature solder forming the bumps.

That is, a bump made of high-temperature solder is provided on the other surface of the insulating plate below the power semiconductor chip, and its size is about the same as or slightly larger than the power semiconductor chip. In between, the generation of voids is suppressed. Also, even if voids occur in this part,
Since the bump is small, the void is also small. Furthermore, since the solder between the bump and the metal base is soldered with low-temperature solder, during the soldering between the bump and the metal base, excess solder under the bump is pushed out of the bump to the outside, and voids are not generated. Is suppressed.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described with reference to FIG. 1 showing an embodiment thereof. In FIG. 1, 2 is a metal base, and 4 is an insulating plate. The insulating plate 4 has a wiring pattern 8a made of copper foil on one surface and a copper foil 8b formed on the entire surface of the other surface. Numeral 6 denotes a power semiconductor chip, on the other surface of the insulating plate 4 below the wiring pattern 8a to which the power semiconductor chip 6 is to be soldered, having a size equal to or about 1.5 times the size of the power semiconductor chip 6a. A slightly large high-temperature solder bump 12 is formed.

Then, cream solder having a lower temperature than the high-temperature solder is applied to the metal base 2, and an insulating plate 4 is mounted thereon. A cream solder 10 having a lower temperature than the high-temperature solder is applied to necessary portions of the wiring pattern 8a of the insulating plate 4, and the power semiconductor chip 6 is mounted on the cream solder 10. At this time, although not shown, the external lead terminals are also mounted on the wiring pattern, the power semiconductor chip 6 is soldered on the wiring pattern 8a by a reflow furnace, and the terminals are also soldered on other wiring patterns. . The power semiconductor chip 6 includes power semiconductor chips 26a to 26d, 28a to 28d, as shown in FIG.
A plurality of 30a and 30b are soldered on the wiring pattern.

Thereafter, the power semiconductor chip and the terminal are connected to each other by wire bonding, a resin case (not shown) is bonded to an end of the metal base, and a sealing agent such as silicon gel is injected into the resin case. The power semiconductor chip is sealed to form a power semiconductor module.

In the power semiconductor module thus formed, the bumps 12 are arranged below the power semiconductor chip 6, have a sufficiently smaller area than the insulating plate 4, and are equal to or smaller than the power semiconductor chip. Since it is slightly larger than five times, the generation of voids between the bump 12 and the copper foil 8b on the other surface is suppressed. If a void occurs, the void will be small. Further, the solder between the bump 12 and the metal base 2 thereunder is thin, and the cream solder under the bump 12 is replaced by the cream solder at the time of soldering.
Is extruded outward from the lower part, and the generation of voids is suppressed. Even if voids are generated, the voids are small and the thickness is small. Therefore, heat loss due to voids when mounting the power semiconductor module is small, and the heat generated by the power semiconductor chip 6 is reliably released from the metal base.

In the above embodiment, the high-temperature solder bump is formed on the insulating plate, but the high-temperature solder bump may be formed on the metal base side.

[0012]

According to the power semiconductor module of the present invention, the generation of voids is suppressed between the insulating plate below the power semiconductor chip and the metal base. Since the power semiconductor module is thin, heat of the power semiconductor chip when the power semiconductor module is mounted is reliably released from the metal base, and damage to the power semiconductor module is avoided.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing an embodiment of a power semiconductor module of the present invention.

FIG. 2 is a schematic plan view of the internal structure of the power semiconductor module.

[Explanation of symbols]

 2 Metal Base 4 Insulating Plate 6 Power Semiconductor Chip 8a Wiring Pattern 8b Copper Foil 10, 14 Low Temperature Solder 12 (High Temperature Solder) Bump

────────────────────────────────────────────────── ─── Continuing from the front page Examiner Kenji Kitajima (56) References JP-A-4-192340 (JP, A) JP-A-6-152094 (JP, A) (58) Fields investigated (Int. Cl. ⁷⁾ , DB name) H01L 21/52

Claims (1)

(57) [Claims] A metal base; an insulating plate provided on the metal base and having a wiring pattern formed on one surface thereof;
A plurality of power semiconductor chips to be soldered to the wiring pattern; a resin case bonded to an end of the metal base; and a sealing agent injected into the resin case to seal the power semiconductor chip. And a high-temperature solder bump having a size equal to or slightly larger than the size of the power semiconductor chip is provided on the other surface of the insulating plate below the power semiconductor chip. And the insulating plate is soldered with a low-temperature cream solder lower than the high-temperature solder forming the bump.