JP3324501B2 - Arithmetic processing device using parallel operation by divided ALU system, filter calculation method, and recording medium - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic processing device, a filter calculating method, and a recording medium using a parallel arithmetic processing by a divided ALU system.

[0002]

2. Description of the Related Art In recent years, as a microprocessor, a microprocessor having a divided ALU (Arithmetic and Logic Unit) type operation instruction has been known. Split AL
A U-type operation instruction divides one ALU into a plurality of ALUs and uses the ALU.
(Single Instruction stream, Multiple Datastream)
Perform type parallel processing. For example, as shown in FIG. 17, a 64-bit ALU is divided into four 16-bit ALUs,
The four 16-bit data are processed in parallel using the divided ALU. The parallel processing technology using such a divided ALU system is described in "MMX Technology Extension to the
Intel Architecture, IEEE MICRO, Vol.16, No.4, pp4
2-50, August 1996, '' The Design of the Microarchit
ecture of UltraSPARC (TM) -I, Proceedings of The
IEEE, Vol. 83, No. 12, pp1653-1663, December 1995 ",
`` Digital, MIPS Add Multimedia Extensions, Microp
rocessor Report, Vol.10, No.15, pp24-28, 1996.11
Month '' and `` Subword Parallelism with MAX-2, IEEE
MICRO, Vol. 16, No. 4, pp. 51-59, August 1996 ". By using the parallel processing technique using the divided ALU system disclosed in these documents, it is possible to process signal processing data with high data parallelism at high speed.

As a typical signal processing, FIR (Finite
Digital filter processing using an Impulse Response) filter is known. Filter processing (filter calculation) by the FIR filter is generally represented by Expression 1.

[0004]

(Equation 1) x (n): input data at time n y (n): output data at time n n: time (n = 0, 1, 2,...) a (k): filter coefficient (k = 0, 1, 2) , ..., M
-1) M: Number of filter taps (filter length)

[0005] The filter calculation shown in Equation 1 is performed by M (the number of taps of the filter) operations (product-sum operation). The number of taps indicates a filter length. In FIG.
The combination of the input data and the filter coefficient at each time of such filter calculation is shown. For example, the output data y (n) at the time n is the filter coefficients a (0) to a (0)
It is represented by the sum of (M−1) multiplied by the input data x (n) at time n to the past input data x (n−M + 1). That is, the output data y (n) is y
(N) = a (0) × x (n) + a (1) × x (n−1)
+ A (2) × x (n−2) +... + A (M−1) × x
It is represented by (n-M + 1).

A technique for speeding up filter processing (filter calculation) by an FIR filter using the divided ALU method is described in "Using MMX (TM) Instructions to Compute a 16".
-Bit Real FIR Filter, Intel APPLICATION NOTE AP-5
59, March 1996 ". Hereinafter, the filtering process (filter calculation) by the FIR filter using the divided ALU system disclosed in this document will be described with reference to the drawings.

FIG. 19 shows an FI using the split ALU system.
FIG. 3 is a block diagram illustrating a configuration of an arithmetic processing device that performs a filter process (filter calculation) using an R filter. The arithmetic processing device includes an input device 101 for inputting data and a data processing device 10 for performing a filter calculation on the input data.
2, a storage device 103 for storing input data and filter coefficients, and an output device 104 for outputting output data.

The storage device 103 includes an input data storage unit 10
5 and a filter coefficient storage unit 106. As shown in FIG. 20, the input data storage unit 105 arranges the first input data acquired from the input device 101 at an address of a multiple of 8 in the input data storage unit 105, and stores the subsequent input data from the lower address to the higher address. They are arranged and stored successively toward the address. The reason why the first input data is arranged at an address that is a multiple of 8 is that the data processor 102 loads the 64-bit (four data) input data from the input data storage unit 105 into the data register 108 at high speed. To do so. This is because the number of clocks required for execution is generally smaller when the data processing device 102 loads from an address that is a multiple of 8 than when it loads from an address that is not a multiple of 8. It is.

Returning to FIG. 19, the filter coefficient storage unit 10
Reference numeral 6 stores a preset filter coefficient. In addition,
The arrangement of the filter coefficients in the filter coefficient storage unit 106 will be described later.

[0010] The data processing device 102 is a parallel processing device 1
07, a data register 108, a filter coefficient register 109, an accumulation register 110, a data head pointer 111, a data pointer 112, a filter coefficient head pointer 113, and a filter coefficient pointer 114.

The data register 108 comprises a 64-bit register, and stores the data stored in the input data storage unit 105.
Load input data for data. The filter coefficient register 109 is a 64-bit register, and loads the filter coefficients for four taps stored in the filter coefficient storage unit 106. The accumulation register 110 is a 64-bit register and sequentially accumulates intermediate results of the product-sum operation by the parallel operation device 107.

A data head pointer 111 indicates a head address of an area for storing input data set in the input data storage unit 105 in advance. The data pointer 112 indicates an address for loading the input data stored in the input data storage unit 105 into the data register 108. The filter coefficient head pointer 113 is
The start address of an area for storing a filter coefficient set in advance in the filter coefficient storage unit 106 is shown.
The filter coefficient pointer 114 indicates an address for loading the filter coefficients stored in the filter coefficient storage unit 106 into the filter coefficient register 109.

The parallel operation unit 107 performs a 4-parallel product-sum operation as shown in FIG. 21 by the divided ALU method. First, the parallel operation device 107 sets the four 16-bit data a0, a1, a2, a
3 and four 16-bit data b0, b1, b2, and b3 loaded in the filter coefficient register 109 are respectively combined to perform four 16-bit multiplications in parallel. Next, the parallel operation device 107 calculates the operation results of the four 16-bit multiplications and the four 1-bit multiplications stored in the accumulation register 110.
6-bit data c0, c1, c2, and c3 are added in four parallels. The parallel operation device 107 stores the operation result of the 4-parallel product-sum operation in the accumulation register 110.

The data processing device 102 causes the parallel operation device 107 to sequentially execute such a 4-parallel multiply-accumulate operation in order to calculate the output y (n) at the time n as shown in Expression 1, and Let 110 perform a filter calculation that sums the accumulated values. Hereinafter, a basic filter calculation at time n shown in FIG. 22 will be described.

First, the data processing device 102
As shown in (a), the input data for the first four data is loaded from the input data storage unit 105 to the data register 108, and the filter coefficients for the first four taps are stored in the filter coefficient register 109 from the filter coefficient storage unit 106. To load. The parallel operation device 107 executes a 4-parallel product-sum operation and stores the operation result in the accumulation register 110.

Next, the data processing device 102
As shown in (b), the input data for the next four data is loaded from the input data storage unit 105 to the data register 108, and the filter coefficients for the next four taps are stored in the filter coefficient register 109 from the filter coefficient storage unit 106. To load. The parallel operation device 107 executes a 4-parallel product-sum operation,
The operation result is added to the accumulation register 110 and stored.

As described above, the data processing device 102 sequentially loads the input data and the filter coefficient into the register, and causes the parallel operation device 107 to execute the 4-parallel multiply-accumulate operation. After performing the product-sum operation for all the tap numbers, that is, M times, the data processing device 102 sums up the respective values accumulated in the accumulation register 110 to calculate output data y (n).

If the number of taps of the filter is not a multiple of four, as shown in FIG.
0 is set in the remainder of 6. The data processing device 102 loads the filter coefficient including the filter coefficient set to 0 into the filter coefficient register 109,
The parallel arithmetic unit 107 is caused to execute a 4-parallel product-sum operation.

The data processing device 102 has been devised to perform the filter calculation with four consecutive times as one cycle in order to process such a filter calculation at a higher speed as a whole. Hereinafter, the filter calculation at four consecutive times will be described.

As shown in FIG. 25, at time n, the data processing device 102 starts a 4-parallel product-sum operation of input data and filter coefficients from input data x (n) and outputs data y (n). Further, at time n + 1, a 4-parallel product-sum operation of the input data and the filter coefficient is started from the input data x (n + 1), and the output data y (n
+1) is calculated. That is, the data processing device 102 performs the arithmetic processing by shifting the filter coefficient by one tap with respect to the input data at each time.

As described above, the filter coefficients are arranged and stored in the filter coefficient storage unit 106 as shown in FIG. Note that the number of taps of the filter is a minimum multiple of 4 which is equal to or greater than the actual number of taps M obtained by Expression 2 in consideration of the case where the tap is not a multiple of 4 as described above and that the filter is used at four consecutive times. Let K be +1.
At this time, 0 is set to a filter coefficient which is larger than the actual tap number M in the tap number K.

[0022]

(Equation 2) K: Number of filter taps for 4-parallel multiply-accumulate operation M: Actual number of filter taps

Further, K, which is a multiple of 4 + 1, is supplemented by three filter coefficients in which 0 is set to be a multiple of 4, and a filter coefficient represented by Expression 3 is set for one time, and They are arranged and stored in the coefficient storage unit 106.

[0024]

(Equation 3) K: Number of filter taps for 4-parallel multiply-accumulate operation M: Actual number of filter taps

Finally, as shown in FIG. 26, the filter coefficients for four consecutive times (CF (0) to CF (3)) are arranged and stored in the filter coefficient storage unit 106. The first time filter (CF (0)) is arranged in the filter coefficient storage unit 106 such that the filter coefficient a (0) is located at an address position that is a multiple of 8, and a (1), a (1)
(2),..., A (K−1) are arranged and stored in order from the upper address to the lower address. Also,
The filter for the second time (CF (1)) has an array in which the filter coefficients at the first time are shifted by one tap.
Is stored in the upper address of the time filter. Similarly, the third and fourth time filters (CF (2), C
F (3)) is that the filter coefficients for the first time are 2 and 3
The array is shifted by taps and stored in the upper address of the filter for the second time. The arrangement of the filter coefficients based on the address of a multiple of 8 is based on the same reason as the arrangement of the input data described above.

The data processing device 102 performs a filter calculation at four consecutive times as shown in FIG. 27 using the filter coefficients stored in the filter coefficient storage unit 106. That is, the data processing device 102 uses the first time filter (CF (0)) at time 4j, and the second time filter (CF) at time 4j + 1.
(1)), at time 4j + 2, a third time filter (CF (2)) is used, and at time 4j + 3, the fourth
, And each filter calculation is performed using the time filter (CF (3)).

FIG. 28 shows the operation of the data processor 102 for calculating the filter when the input data and the filter coefficient are arranged in the input data storage unit 105 and the filter coefficient register 106 as shown in FIG.
This will be described with reference to FIG. FIG. 28 shows the data processing device 102.
6 is a flowchart showing the operation of the filter calculation of FIG.

First, the data processing device 102 clears the value of the accumulation register 110 to zero (step S10).
1).

The data processing device 102 sets an initial value at time j in the data pointer 112 (step S102). That is, at time j, the data processing device 102
08, an initial value (ADFRD) indicating an address for loading input data is obtained using Expression 4, and the obtained initial value is set in the data pointer 112.

[0030]

ADRD = SD + 8 × j ADRD: Initial value of data pointer 112 SD: Value of data head pointer j: Time (j = 0, 1, 2,...)

The data processing device 102 sets an initial value at time i (i = 0, 1, 2, 3) in the filter coefficient pointer 114 (step S103). That is, at time i, the data processing apparatus 102 sets the initial value (ADR) indicating the address for loading the filter coefficient from the filter coefficient storage unit 106 to the filter coefficient register 109.
F) is calculated using Expression 5, and the obtained initial value is set in the filter coefficient pointer 114. Note that the initial value (AD
RF) is the head address of the filter coefficient CF (i).

[0032]

ADRF = SF + (K + 3) × 2 ×
(I + 1) -8 ADRF: Initial value of filter coefficient pointer 114 SF: Value of filter coefficient leading pointer 113 K: Number of taps of filter for 4-parallel multiply-accumulate operation i: Time (i = 0, 1, 2, 3)

The data processing device 102 loads, from the input data stored in the input data storage unit 105, input data for four data stored at the address indicated by the data pointer 112 into the data register 108 (step S104). ).

The data processing device 102 converts the filter coefficients for four taps stored at the address indicated by the filter coefficient pointer 114 from the filter coefficients stored in the filter coefficient storage unit 106 into the filter coefficient register 10.
9 (step S105).

The parallel operation unit 107 includes a data register 1
A 4-parallel multiply-accumulate operation is performed with the input data of 4 data loaded into the register 08 and the filter coefficients of 4 taps loaded into the filter coefficient register 109, and the operation result is added and stored in the accumulation register 110 (step). S106).

The data processor 102 loads the data pointer 112 and the filter coefficient in order to load the input data for the next four data and the filter coefficient for the four taps into the data register 108 and the filter coefficient register 109 and perform a product-sum operation. The pointers 114 are updated (steps S107 and S108). That is, the data processing device 102
Are the data pointer 112 and the filter coefficient pointer 1
The data pointer 112 is set so that the address indicated by 14 indicates the input data and the filter coefficient arranged below the input data storage unit 105 and the filter coefficient storage unit 106.
Then, 8 (for 4 data, 4 taps) is subtracted from the value of the filter coefficient pointer 114 and updated with the value after the subtraction.

The data processing device 102 determines whether or not processing for all filter taps has been completed (step S109). If the data processing apparatus 102 determines that the processing for all the filter taps has not been completed, the processing returns to step S104, and the processing returns to step S104 to step S10.
9 is repeated (product-sum calculation loop S100).

On the other hand, when the data processing device 102 determines that the processing for all the filter taps has been completed, the data processing device 102 calculates the total sum (c0) of the four 16-bit numbers stored in the accumulation register 110.
+ C1 + c2 + c3) (step S11)
0). That is, when the processing of all the filter taps is completed, the accumulation calculation result of the filter of all the taps is divided into four 16-bit numerical values (c0 to c3) in the accumulation register 110. The data processing device 102 calculates the sum (c0 + c1 + c2 + c3) of the four 16-bit numerical values, and sets the sum as the output data after the filter calculation.

The data processing device 102 outputs the obtained output data to the output device 104 (step S111).

[0040]

[Problems to be solved by the invention] However, "Using MMX
(TM) Instructions to Compute a 16-Bit Real FIR F
ilter, Intel APPLICATION NOTE AP-559, March 1996 ''
However, such an arithmetic processing device disclosed in Japanese Patent Application Laid-Open No. H11-157572 has a problem that the memory capacity of the input data storage unit 102 increases because all the input data is continuously stored in the input data storage unit 102. Further, since it is necessary to set and store the value of the filter coefficient to 0, there is a problem that the memory capacity of the filter coefficient storage unit 106 increases. Further, since unnecessary product-sum operation is performed using the filter coefficient of the value 0 set in the filter coefficient storage unit 106, the total operation amount of the filter calculation increases,
There is a problem that the processing speed is reduced.

The present invention has been made in view of the above situation, and in an arithmetic processing device utilizing parallel arithmetic processing by a divided ALU system, an arithmetic processing device which can efficiently use a memory and can execute arithmetic processing at high speed. It is an object to provide a filter calculation method and a recording medium. Another object of the present invention is to provide an arithmetic processing device, a filter calculation method, and a recording medium that can execute a calculation process of a filter calculation using filter coefficients of different arrangements in accordance with a calculation required for each output data. That is.

[0042]

In order to achieve the above object, an arithmetic processing device according to a first aspect of the present invention is provided for filtering input data in parallel arithmetic processing using an ALU of a divided ALU system. And a parallel processing means for executing a parallel operation of the input data and the filter coefficient in parallel, wherein the input data is sequentially stored in a storage area having a circular structure in which a head and an end are logically connected. An input data storage unit, a filter coefficient storage unit in which a storage area is filled with filter coefficients arranged in one-to-one correspondence with each input data stored in the input data storage unit, In order for the arithmetic means to perform parallel arithmetic processing, input data temporary storage means for reading input data of a predetermined data amount from the input data storage means and temporarily storing the input data; In order for the parallel operation means to perform parallel operation processing, a filter coefficient temporary storage means for reading and temporarily storing a filter coefficient of a predetermined data amount from the filter coefficient storage means, and the parallel operation means, The input data read into the input data temporary storage means and the filter coefficient read into the filter coefficient temporary storage means are subjected to a product-sum operation to filter the input data.

According to the present invention, since the input data storage means sequentially stores the input data in the storage area having the annular structure in which the head and the end are logically connected, the input data is efficiently overwritten on the used data. Can store input data.
The filter coefficient storage means needs to store the filter coefficients which are arranged in a one-to-one correspondence with the respective input data stored in the input data storage means so as to fill the storage area and store 0 for filling the interval. Therefore, the filter coefficients can be efficiently stored. The input data temporary storage unit reads, from the input data storage unit, input data of a predetermined data amount necessary for the parallel operation unit to perform the parallel operation processing, and temporarily stores the input data. The filter coefficient temporary storage means reads from the filter coefficient storage means a filter coefficient of a predetermined data amount necessary for the parallel operation means to perform the parallel operation processing, and temporarily stores the filter coefficient. The parallel operation unit performs a product-sum operation on the input data read into the input data temporary storage unit and the filter coefficient read into the filter coefficient temporary storage unit, and filters the input data.
As a result, the memory can be efficiently used, and the arithmetic processing can be performed at high speed without performing unnecessary arithmetic.

The input data storage means arranges the input data in accordance with a predetermined start position at which the input data temporary storage means starts reading the input data, and the filter coefficient storage means stores the filter coefficient temporary data. The filter coefficients may be arranged in a storage area having a circular structure in which the head and the end are logically connected in accordance with a predetermined start position at which the storage means starts reading the filter coefficients. As a result, since the input data and the filter coefficient can be read into the respective temporary storage units at a high speed, the arithmetic processing can be executed at a high speed.

In order to achieve the above object, an arithmetic processing unit according to a second aspect of the present invention comprises an ALU of a divided ALU system.
An arithmetic processing device comprising parallel operation means for executing an operation of input data and a filter coefficient in parallel in order to filter the input data in a parallel operation process using Input data storage means for sequentially storing data in a storage area having a ring structure in which the input data is connected to the end, and one to n (n is a natural number of 2 or more) corresponding to each input data stored in the input data storage means. The filter coefficient storage means in which the storage area is filled with the filter coefficients arranged as described above, and one input data string having a predetermined data amount for the parallel calculation means to perform parallel calculation processing. Input data temporary storage means for reading and temporarily storing the input data from the input data storage means; and temporarily storing the input data in the input data temporary storage means for the parallel operation means to perform parallel operation processing. Filter coefficient temporary storage means for reading from the filter coefficient storage means and temporarily storing the n-th filter coefficient string having a data amount of n times the input data string of one row, wherein the parallel operation means comprises: A product-sum operation is performed in a predetermined order on the one input data string read into the input data temporary storage means and the n filter coefficient strings read into the filter coefficient temporary storage means,
Filtering input data.

According to the present invention, since the input data storage means sequentially stores the input data in the storage area having the annular structure where the head and the end are logically connected, the input data is efficiently overwritten on the used data. Can store input data.
The filter coefficient storage means fills the storage area with filter coefficients arranged corresponding to each input data stored in the input data storage means in a one-to-n (n is a natural number not less than 2) storage, and stores Since there is no need to store 0 for filling in, the filter coefficient can be stored efficiently. The input data temporary storage means reads one input data string having a predetermined data amount from the input data storage means and temporarily stores the input data string in order for the parallel operation means to perform the parallel operation processing. The filter coefficient temporary storage means stores n filter coefficient strings having an n-times data amount of one input data string temporarily stored in the input data temporary storage means in order for the parallel operation means to perform parallel operation processing. It is read from the filter coefficient storage means and temporarily stored. The parallel operation means performs a product-sum operation of the one input data string read into the input data temporary storage means and the n filter coefficient strings read into the filter coefficient temporary storage means in a predetermined order, Filter data. As a result, the memory can be efficiently used, and the arithmetic processing can be performed at high speed without performing unnecessary arithmetic.

The filter coefficient temporary storage means may read the n-th filter coefficient sequence once while the input data temporary-storage means reads one column of the input data sequence n times. As a result, the number of times that the filter coefficients are read into the respective filter coefficient temporary storage units can be reduced, so that the arithmetic processing can be executed at a high speed.

To achieve the above object, an arithmetic processing unit according to a third aspect of the present invention comprises an ALU of a divided ALU system.
In order to filter the input data in a parallel operation process using an arithmetic processing device, the arithmetic processing device includes parallel operation means for executing the operation of the input data and the filter coefficient in parallel, and sequentially stores the input data in a storage area. A storage area for storing input data storage means, and filter coefficients arranged corresponding to each input data stored in the input data storage means and an operation required to calculate output data from each input data; A filter coefficient storage unit that is filled and stored, and an input data temporary unit that reads and temporarily stores input data of a predetermined data amount from the input data storage unit so that the parallel operation unit performs a parallel operation process. A storage unit that stores a filter coefficient of a predetermined data amount in the filter coefficient storage unit so that the parallel operation unit performs a parallel operation process; Filter coefficient temporary storage means for reading and temporarily storing, wherein the parallel operation means calculates a product sum of the input data read in the input data temporary storage means and the filter coefficient read in the filter coefficient temporary storage means. Calculating and filtering input data.

According to the present invention, the input data stored in the input data storage means and the filter coefficients arranged corresponding to the operations required to calculate the output data from each input data are stored in the storage area. From the filter coefficient storage means filled and stored, the input data is filtered by performing the product-sum operation using the filter coefficients read into the filter coefficient temporary storage means, so that the output is performed without changing the operation procedure. Filter processing using a different filter coefficient for each data can be executed.

In order to achieve the above object, a filter calculation method according to a fourth aspect of the present invention employs a split ALU type A
What is claimed is: 1. A filter calculation method comprising a parallel operation step of executing an operation of input data and a filter coefficient in parallel in order to filter input data in a parallel operation process using an LU, wherein the input data is logically processed. An input data storage step of sequentially storing data in a storage area having a ring structure in which a head and an end are connected; and input data of a predetermined amount of data logically executed in order to perform parallel operation processing in the parallel operation step. An input data temporary storage step of temporarily reading and storing from a storage area having a ring structure in which a head and an end are connected, and a filter coefficient of a predetermined data amount for performing parallel operation processing in the parallel operation step. Filter data arranged in a one-to-one correspondence with each input data stored in the input data storage step is satisfied and stored. A filter coefficient temporary storage step of reading from the stored storage area and temporarily storing the filter coefficient, wherein the parallel operation step includes: the input data read into the input data temporary storage area in the input data temporary storage step; The sum of the filter coefficient and the filter coefficient read into the filter coefficient temporary storage area in the storage step is calculated to filter the input data.

According to the present invention, in the input data storing step, the input data is sequentially stored in the storage area having a ring structure in which the head and the end are logically connected. Can store input data. The input data temporary storage step reads input data of a predetermined data amount from the storage area stored in the input data storage step and temporarily stores the input data in order to perform parallel operation processing in the parallel operation step. In the filter coefficient temporary storage step, a filter coefficient of a predetermined data amount is arranged in a one-to-one correspondence with each input data stored in the input data storage step in order to perform the parallel operation processing in the parallel operation step. Is read from a storage area where the set filter coefficients are satisfied and stored, and temporarily stored. In the parallel operation step, the input data read in the input data temporary storage area in the input data temporary storage step and the filter coefficient read in the filter coefficient temporary storage area in the filter coefficient temporary storage step are subjected to a product-sum operation. Filter data. As a result, the memory can be efficiently used, and the arithmetic processing can be performed at high speed without performing unnecessary arithmetic.

In the parallel operation step, the input data read into the input data temporary storage area in the input data temporary storage step is stored between a reading start position of the storage area and an end position of the storage area. And the filter coefficient read into the filter coefficient temporary storage area in the filter coefficient temporary storage step are divided into a case where the filter coefficient is stored from the head position of the storage area to a reading start position and a product-sum operation. Then, the input data may be filtered.

In order to achieve the above object, a filter calculation method according to a fifth aspect of the present invention employs a split ALU method A
What is claimed is: 1. A filter calculation method comprising a parallel operation step of executing an operation of input data and a filter coefficient in parallel in order to filter input data in a parallel operation process using an LU, wherein the input data is logically processed. An input data storage step of sequentially storing data in a storage area having a ring structure in which a head and an end are connected; and a column of input data having a predetermined data amount for performing parallel operation processing in the parallel operation step An input data temporary storage step of reading and temporarily storing a column from a storage area having a circular structure in which a head is logically connected to the end, and the input data temporary storage for performing parallel operation processing in the parallel operation step In the input data storage step, n filter coefficient sequences having n times the data amount of one input data sequence temporarily stored in the step are stored. Each input data and the one-to-n stored Ri
A filter coefficient temporary storage step of temporarily reading and storing from a storage area in which the filter coefficients arranged corresponding to are satisfied and stored, and wherein the parallel operation step includes the step of input data temporary storage in the input data temporary storage step. Performing a product-sum operation in a predetermined order on the input data string of one column read into the temporary storage area and the n filter coefficient rows read into the filter coefficient temporary storage area in the filter coefficient temporary storage step; It is characterized by the following.

According to the present invention, in the input data temporary storage step, the input data is sequentially stored in the storage area having a circular structure in which the head and the end are logically connected. Can well store input data. In the input data temporary storage step, in order to perform the parallel operation processing in the parallel operation step, one input data string having a predetermined data amount is read from the storage area stored in the input data storage step and temporarily stored. Remember. The filter coefficient temporary storage step is an n-column filter coefficient sequence that has n times the data amount of one column of the input data sequence temporarily stored in the input data temporary storage step in order to perform the parallel operation processing in the parallel operation step. Is read from a storage area in which filter coefficients arranged in a one-to-n correspondence with each input data stored in the input data storage step are stored and temporarily stored. The parallel operation step includes one input data string read into the input data temporary storage area in the input data temporary storage step and n filter coefficient strings read into the filter coefficient temporary storage area in the filter coefficient temporary storage step. Are calculated in a predetermined order. As a result, the memory can be efficiently used, and the arithmetic processing can be performed at high speed without performing unnecessary arithmetic.

In order to achieve the above object, a filter calculation method according to a sixth aspect of the present invention employs a split ALU system A
What is claimed is: 1. A filter calculation method comprising a parallel operation step of executing an operation of input data and a filter coefficient in parallel in order to filter input data in a parallel operation process using an LU, wherein the input data is stored in a storage area. An input data storage step for sequentially storing, and a storage area having a ring structure in which input data of a predetermined data amount is logically connected to the beginning and end in order to perform parallel operation processing in the parallel operation step. An input data temporary storage step of reading and temporarily storing, and each input data stored in the input data storage step with a filter coefficient of a predetermined data amount for performing a parallel operation process in the parallel operation step, The filter coefficients arranged corresponding to the operations required to calculate the output data from each input data are satisfied. A filter coefficient temporary storage step of reading from a stored storage area and temporarily storing the input data and the filter coefficient, wherein the parallel operation step includes the input data read into the input data temporary storage area in the input data temporary storage step and the filter coefficient In the temporary storage step, a product-sum operation is performed on the filter coefficient read into the filter coefficient temporary storage area and the input data is filtered.

According to the present invention, filter data arranged in correspondence with each input data stored in the input data storage step and an operation required to calculate output data from each input data is stored in the storage area. In order to filter the input data by performing a multiply-accumulate operation using the filter coefficients read into the filter coefficient temporary storage area in the filter coefficient temporary storage step from the filter coefficient storage area stored by filling in Filter processing using a different filter coefficient for each output data can be performed without changing.

In order to achieve the above object, a recording medium according to a seventh aspect of the present invention is a computer-readable recording medium for recording a program for causing a computer to function as an arithmetic processing unit. Input data storage means for sequentially storing data in a storage area having a ring structure in which data is logically connected to the beginning and end;
Each input data stored in the input data storage means and 1
Filter coefficient storage means in which storage areas are filled with filter coefficients arranged in a one-to-one correspondence, and input data of a predetermined data amount for the parallel operation means to perform parallel operation processing. An input data temporary storage unit for reading and temporarily storing the input data from the input data storage unit; and a filter coefficient of a predetermined data amount being read from the filter coefficient storage unit and temporarily stored in order for the parallel operation unit to perform a parallel operation process. The filter coefficient temporary storage means for storing the input data read into the input data temporary storage means and the filter coefficient read into the filter coefficient temporary storage means for filtering the input data by the ALU of the divided ALU system. A program that functions as a parallel operation means that executes the product-sum operation in parallel by using the parallel operation processing is described. Characterized in that it.

In order to achieve the above object, a recording medium according to an eighth aspect of the present invention is a computer-readable recording medium for recording a program for causing a computer to function as an arithmetic processing unit. Input data storage means for sequentially storing data in a storage area having a ring structure in which data is logically connected to the beginning and end;
Each input data stored in the input data storage means and 1
The filter coefficient storage means in which the storage area is filled with the filter coefficients arranged corresponding to the pair n (n is a natural number of 2 or more) and the parallel operation means perform parallel operation processing in advance. An input data temporary storage means for reading a temporary input data string having a predetermined data amount from the input data storage means and temporarily storing the input data string; Filter coefficient temporary storage means for reading from the filter coefficient storage means and temporarily storing n filter coefficient strings having a data amount n times as large as one input data string temporarily stored in the means; 1 loaded into the means
In order to filter the input data between the input data sequence of the column and the n-th filter coefficient sequence read into the filter coefficient temporary storage means, a predetermined order is determined in a parallel operation process using an ALU of a divided ALU system. A program that functions as a parallel operation means that executes the product-sum operation in parallel.

To achieve the above object, a recording medium according to a ninth aspect of the present invention is a computer-readable recording medium for recording a program for causing a computer to function as an arithmetic processing unit. An input data storage means for sequentially storing data in a storage area, and each input data stored in the input data storage means are arranged in correspondence with an operation required to calculate output data from each input data. The filter coefficient storage means in which the storage area is filled with the stored filter coefficients, and the parallel operation means for executing parallel operation processing by reading input data of a predetermined data amount from the input data storage means. Input data temporary storage means for temporarily storing, and predetermined data for the parallel operation means to perform parallel operation processing. Filter coefficient temporary storage means for reading the filter coefficient from the filter coefficient storage means and temporarily storing the same, input data read into the input data temporary storage means and filter coefficients read into the filter coefficient temporary storage means In order to filter data, a program is recorded that functions as a parallel operation unit that executes a product-sum operation in parallel in a parallel operation process using an ALU of the divided ALU system.

[0060]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an arithmetic processing device according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram illustrating a configuration of the arithmetic processing device according to the first embodiment of the present invention. The arithmetic processing device includes an input device 1 for inputting data, a data processing device 2 for performing a filter calculation on the input data, a storage device 3 for storing input data and filter coefficients, and an output device for outputting output data. And 4.

The storage device 3 comprises a ring memory 15 for storing input data and a filter coefficient storage section 16 for storing filter coefficients. The ring memory 15 and the filter coefficient storage unit 16 will be described later.

The data processing device 2 includes a parallel operation device 7 and
A data register 8, a filter coefficient register 9, an accumulation register 10, a ring memory head pointer 17,
It comprises a ring memory end pointer 18, a write pointer 19, a read pointer 20, a filter coefficient head pointer 21, and a filter coefficient pointer 22.

The parallel operation unit 7 performs a 4-parallel product-sum operation by the divided ALU method. That is, the input data for four data loaded in the data register 8 and the filter coefficient for four taps loaded in the filter coefficient register 9 are multiplied in four parallels, and the multiplication result is added to the accumulation register 10. Store.

The data register 8 comprises a 64-bit register, and loads the input data of four data stored in the ring memory 15. Filter coefficient register 9
Consists of a 64-bit register, and loads filter coefficients for four taps stored in the filter coefficient storage unit 16. The accumulation register 10 is a 64-bit register and sequentially accumulates intermediate results of the product-sum operation by the parallel operation device 7.

The ring memory start pointer 17 indicates a start address of an area for storing input data set in the ring memory 15 in advance.

The ring memory end pointer 18 indicates the end address of an area for storing input data set in the ring memory 15 in advance.

The write pointer 19 indicates the address of the latest input data stored in the ring memory 15 at the start of the filter calculation.

The read pointer 20 indicates an address for loading the input data stored in the ring memory 15 into the data register 8.

The filter coefficient start pointer 21 indicates a start address of an area for storing a filter coefficient set in the filter coefficient storage section 16 in advance.

The filter coefficient pointer 22 indicates an address for loading the filter coefficient stored in the filter coefficient storage section 16 into the filter coefficient register 9.

As shown in FIG. 2, the ring memory 15 has a ring shape in which a head and an end are logically connected by a ring memory head pointer 17, a ring memory end pointer 18, a write pointer 19, and a read pointer 20. It has a structure and stores input data obtained from the input device 1. That is, the data processing device 2 is the input device 1
Are sequentially stored in the ring memory 15. At this time, the address indicated by the write pointer 19 is sequentially stored in the ring memory 15 while being added by 2 bytes (1 data). The data processing device 2 sets the value of the write pointer 19 to the ring memory end pointer 18
When the value becomes larger than the value of, the value of the write pointer 19 is set to the value of the ring memory head pointer 17, and the input data is subsequently stored in the ring memory 15. In addition,
With the address in the ring memory 15 indicated by the ring memory head pointer 17, the data processing device 2 performs a process of loading the input data of 64 bits (for 4 data) from the ring memory 15 into the data register 8 at high speed. , 8.

The ring memory 15 has such a logical ring structure, and can store new input data by overwriting old input data that is no longer necessary for filter calculation. Well available.

The filter coefficient storage unit 16 stores four continuous time points (CF (0) to CF (3)) as shown in FIG.
Are stored. In consideration of the case where the actual tap number M of the filter coefficient is not a multiple of 4, Equation 6
As shown in (1), L which is not less than M and a multiple of 4 is set as the number of taps of the filter coefficient. Note that 0 is set to the filter coefficient of the difference between M and L.

[0074]

(Equation 6) L: Number of taps of filter for 4-parallel multiply-accumulate operation M: Number of taps of actual filter

First time filter (CF (0))
Indicates that the filter coefficient a (0) is stored in the filter coefficient storage unit 10
., A (L−1),... A (2), a
(1),... Are arranged and stored in order from the lower address to the upper address. The filter coefficient has a ring structure in which the head and the end are theoretically connected like the ring memory 15. With such an annular structure, no free space is generated, so that a memory for storing filter coefficients can be used efficiently. The filter (CF (1)) for the second time is
The filter coefficients at the first time are arranged in an array shifted by one tap, and are stored in the upper address of the filter for the first time. Similarly, the third and fourth time filters (CF
(2), CF (3)) are arranged such that the filter coefficients for the first time are shifted by 2 and 3 taps, and are stored in the upper address of the filter for the second time.

It should be noted that the number of taps for the four parallel product-sum operations of the filter coefficients at each time is L
Becomes The number of taps L for 4-parallel product-sum operation of filter coefficients obtained by Expression 6 is the number of taps K + 3 for 4-parallel product-sum operation of filter coefficients obtained by conventional Expression 3.
Is equal to the case where the actual value of the number of taps M is a multiple of 4 + 1, and in other cases, it is decreased by 4.

Further, in order to generate a filter coefficient array for four consecutive times as a whole, the total tap number L × 4 for the four parallel multiply-accumulate operations of the filter coefficients obtained by the equation (6)
4 is the filter coefficient 4 obtained by the conventional equation 3.
When compared with the total tap number (K + 3) × 4 for the parallel multiply-accumulate operation, it is equal to the case where the actual tap number M is a multiple of 4 + 1.
Otherwise, it is reduced by 16. Therefore, it is possible to reduce the memory capacity required to hold the filter coefficients.

The data processing device 2 uses the filter coefficients stored in the filter coefficient storage unit 16 to perform a filter calculation at four consecutive times as shown in FIG. That is, the data processing device 2 at time 4j
A filter for the first time (CF (0)) is used, a filter for the second time (CF (1)) is used at time 4j + 1, and a filter for the third time (CF (1)) is used at time 4j + 2. C
F (2)), and at time 4j + 3, a filter for the fourth time (CF (3)) is used to calculate each filter.

Hereinafter, the operation of the filter calculation of the data processing apparatus 2 in a state where the input data and the filter coefficient are arranged in the ring memory 15 and the filter coefficient storage unit 16 as shown in FIG. 4 will be described with reference to FIG. Will be explained. FIG. 5 is a flowchart illustrating an operation of the filter calculation of the data processing device 2.

First, the data processing device 2 clears the value of the accumulation register 10 to zero (step S201).

The data processing device 2 stores the input data acquired from the input device 1
The data is written and stored in the address of the memory 15 (step S202).

The data processing device 2 has a read pointer 2
The initial value at time j is set to 0 (step S2).
03). That is, at time j, the data processing device 2
Write pointer 19 serving as an initial value for loading input data from ring memory 15 to data register 8
The value of the maximum multiple of 8 that does not exceed the value of the address of the latest input data indicated by the write pointer 19, that is, a value obtained by setting the lower 3 bits of the value indicated by the write pointer 19 to zero is set to the read pointer 2
Set to 0.

The data processing device 2 sets an initial value at time i (i = 0, 1, 2, 3) in the filter coefficient pointer 22 (step S204). That is, the data processing device 2 obtains the initial value (ADRF) indicating the address for loading the filter coefficient from the filter coefficient storage unit 16 to the filter coefficient register 9 at time i by using Expression 7. Initial value is set to filter coefficient pointer 22
Set to. Note that the initial value (ADRF) is the head address of the filter coefficient CF (i).

[0084]

ADRF = SF + L × 2 × i ADRF: Initial value of filter coefficient pointer 22 SF: Value of filter coefficient head pointer 21 L: Number of taps of filter for 4-parallel product-sum operation i: Time (i = 0, 1, 2, 3)

The data processing device 2 includes a ring memory 15
From the input data stored in the
The input data of 4 data stored at the address indicated by 0 is loaded into the data register 8 (step S20).
5).

The data processing device 2 loads the filter coefficients for four taps stored at the address indicated by the filter coefficient pointer 22 from the filter coefficients stored in the filter coefficient storage section 16 into the filter coefficient register 9 ( Step S206).

The parallel operation device 7 performs four parallel multiply-accumulate operations on the input data for four data loaded in the data register 8 and the filter coefficients for four taps loaded in the filter coefficient register 9, and accumulates the operation results. The result is added to and stored in the arithmetic register 10 (step S207).

The data processing device 2 updates the read pointer 20 in order to load the next four pieces of input data into the data register 8 (step S208). That is, the data processing device 2 sets the value of the read pointer 20 to 8 so that the address indicated by the read pointer 20 indicates the input data arranged at the upper position of the ring memory 15.
(For 4 data) are added and updated with the value after the addition.

The data processing device 2 determines whether or not the value of the read pointer 20 after the update is larger than the value of the ring memory end pointer 18 (step S209). That is, when the initial value of the read pointer 20 is not the same value as the ring memory head pointer 17 at the start of the filter calculation, the read pointer 20 reaches the end of the ring memory during the filter calculation. For this reason, the data processing device 2 compares the read pointer 20 after updating with the ring memory end pointer 18 by comparing the read pointer 20 with the ring memory end pointer 18 or the like.
Is determined to have reached the end of the ring memory 15.

When the data processing device 2 determines that the updated read pointer 20 is larger than the value of the ring memory end pointer 18,
7 is substituted for the value of the read pointer 20 and updated (step S210). Thus, the ring memory 1
5 constitutes a logical ring structure.

The data processing device 2 updates the filter coefficient pointer 22 to load the filter coefficients for the next four taps into the filter coefficient register 9 (step S).
211). That is, the data processing device 2 stores the address indicated by the filter coefficient pointer 22 in the filter coefficient storage unit 16.
8 (for 4 taps) is added to the value of the filter coefficient pointer 22 so as to indicate the filter coefficient arranged at a higher position than
Update with the value after addition.

The data processing device 2 determines whether or not processing for all filter taps has been completed (step S2).
12). If the data processing device 2 determines that the processing for all the filter taps has not been completed, step S205
Then, the processing of steps S205 to S212 is repeated (product-sum calculation loop S200).

On the other hand, when the data processing device 2 determines that the processing for all the filter taps has been completed, the data processing device 2 sums the four 16-bit numbers stored in the accumulation register 10 (c0 + c1).
+ C2 + c3) is calculated (step S213). That is, when the processing of all the filter taps is completed, the accumulation register 110 stores the four 16
Bit values (c0 to c3) are stored separately. The data processing device 2 calculates the sum of the four 16-bit numerical values (c
0 + c1 + c2 + c3) is calculated and used as output data after filter calculation.

The data processing device 2 outputs the obtained output data to the output device 4 (Step S214).

The data processing device 2 updates the write pointer 19 for the filter calculation at the next time (step 215). That is, the data processing device 2 adds the address of 2 bits (for one data) to the write pointer 19 and updates it with the value after the addition.

The data processing device 2 determines whether or not the value of the updated write pointer 19 is larger than the value of the ring memory end pointer 18 (step S216). That is, the data processing device 2 updates the write pointer 1
Whether the write pointer 19 has reached the end of the ring memory 15 is determined by comparing the size of the ring memory 15 with the ring memory end pointer 18 or the like.

When the data processing device 2 determines that the updated write pointer 19 is larger than the value of the ring memory end pointer 18,
The value of 7 is substituted for the value of the write pointer 19 and updated (step S217).

As described above, according to the first embodiment of the present invention, the input data is stored in the ring memory 15 having a logical ring structure,
New input data can be stored by overwriting old input data that is no longer needed for filter calculation.
Memory can be used efficiently. In addition, by storing the filter coefficients in the filter coefficient storage unit 16 as a logical annular structure, the occurrence of free space is suppressed, and the memory for storing the filter coefficients can be used efficiently. Furthermore, since the filter coefficient of 0 is set to be suppressed in the filter coefficient storage unit 106, the entire calculation amount of the filter calculation is reduced, and high-speed calculation can be performed.

Next, an arithmetic processing device according to a second embodiment of the present invention will be described with reference to the drawings. The second embodiment is different from the first embodiment in that the process for performing the product-sum calculation is divided into two processes. That is,
In the second embodiment, a process for performing the sum-of-products calculation is a loop for processing input data stored from the initial position of the read pointer 20 to the end of the ring memory 15, and a read pointer 20 from the top of the ring memory. And a loop for processing the input data stored up to the position just before the initial position.

The configuration of the second embodiment is the same as the configuration of the first embodiment shown in FIG. Hereinafter, the operation of the filter calculation of the data processing device 2 in a state where the input data and the filter coefficient are arranged in the ring memory 15 and the filter coefficient register 16 will be described with reference to FIG. FIG. 6 is a flowchart illustrating an operation of the filter calculation of the data processing device 2. In the flowchart shown in FIG. 6, the product-sum calculation loop (S200) shown in the flowchart of FIG. 2 is different from the product-sum calculation loop 1 (S300).
And a product-sum calculation loop 2 (S301).

First, the data processing device 2 clears the value of the accumulation register 10 to zero (step S302). The data processing device 2 writes the input data acquired from the input device 1 to the address of the ring memory 15 indicated by the write pointer 19 and stores it (step S303).

The data processing device 2 has a read pointer 2
The initial value at time j is set to 0 (step S3).
04). The data processing device 2 includes a filter coefficient pointer 2
An initial value at time i (i = 0, 1, 2, 3) is set to 2 (step S305).

The data processing device 2 includes a ring memory 15
From the input data stored in the
The input data for four data stored at the address indicated by 0 is loaded into the data register 8 (step S30).
6). The data processing device 2 loads the filter coefficients for four taps stored at the address indicated by the filter coefficient pointer 22 from the filter coefficients stored in the filter coefficient storage unit 16 into the filter coefficient register 9 (step S307). .

The parallel operation device 7 performs four parallel multiply-accumulate operations on the input data for four data loaded in the data register 8 and the filter coefficients for four taps loaded in the filter coefficient register 9, and accumulates the operation results. The result is added and stored in the arithmetic register 10 (step S308).

The data processing device 2 updates the read pointer 20 to load the next four pieces of input data into the data register 8 (step S309). The data processing device 2 updates the filter coefficient pointer 22 to load the filter coefficients for the next four taps into the filter coefficient register 9 (Step S310).

The data processor 2 determines whether or not the updated value of the read pointer 20 is larger than the value of the ring memory end pointer 18 (step S311). When the data processing device 2 determines that the value of the read pointer 20 after the update is smaller than the value of the ring memory end pointer 18, the process returns to step S306 and returns to step S3.
The processing from 06 to step S311 is repeated (product-sum calculation loop 1S300).

On the other hand, the data processor 2 sets the value of the read pointer 20 after the update to the ring memory end pointer 1
8 is determined to be larger than the value of the data processing device 2
Determines whether or not the processing for all filter taps has been completed (step S312).

If the data processing device 2 determines that the processing for all the filter taps has been completed,
Proceeding to 320, the sum of the four 16-bit numbers stored in the accumulation register 10 is calculated. On the other hand, the data processing device 2
When it is determined that the processing for all the filter taps has not been completed, the value of the ring memory head pointer 17 is substituted for the value of the read pointer 20 and updated (step S).
313).

The data processing device 2 includes a ring memory 15
From the input data stored in the
The input data of four data stored at the address indicated by 0 is loaded into the data register 8 (step S31).
4). The data processing device 2 loads the filter coefficients for four taps stored at the address indicated by the filter coefficient pointer 22 from the filter coefficients stored in the filter coefficient storage unit 16 into the filter coefficient register 9 (step S315). .

The parallel operation device 7 performs four parallel multiply-accumulate operations on the input data for four data loaded in the data register 8 and the filter coefficients for four taps loaded in the filter coefficient register 9, and accumulates the operation results. The result is added and stored in the arithmetic register 10 (step S316).

The data processing device 2 updates the read pointer 20 in order to load the next four pieces of input data into the data register 8 (step S317). The data processing device 2 updates the filter coefficient pointer 22 to load the filter coefficients for the next four taps into the filter coefficient register 9 (Step S318).

The data processing device 2 determines whether or not the updated value of the read pointer 20 is larger than the initial value of the read pointer 20 (Step S319). When the data processing device 2 determines that the value of the read pointer 20 after the update is smaller than the initial value of the read pointer 20,
Returning to step S314, the processes of steps S314 to S319 are repeated (the product-sum calculation loop 2S30
1).

On the other hand, when the data processing device 2 determines that the value of the read pointer 20 after the update is larger than the initial value of the read pointer 20, the data processor 2 sums the four 16-bit numbers stored in the accumulation register 10 (c0 + c1 + c2 + c
3) is calculated and used as output data after the filter calculation (step S320). The data processing device 2 outputs the obtained output data to the output device 4 (Step S321).

The data processing device 2 updates the write pointer 19 for the filter calculation at the next time (step 322). The data processing device 2 determines whether or not the value of the updated write pointer 19 is larger than the value of the ring memory end pointer 18 (Step S323).

When the data processing device 2 determines that the updated write pointer 19 is larger than the value of the ring memory end pointer 18,
The value of 7 is assigned to the value of the write pointer 19 and updated (step S324).

As described above, according to the invention of the second embodiment, the input data stored from the initial position of the read pointer 20 to the end of the ring memory 15 and the input data stored in the ring memory 15 The input data stored from the beginning to a position before the initial position of the read pointer 20 is processed by another product-sum calculation loop. For this reason,
It becomes unnecessary to determine whether the read pointer has reached the end of the ring memory and move the read pointer to the top of the ring memory in the product-sum calculation loop. Also,
Since the product-sum calculation loop is repeatedly executed, the processing amount of the entire filter calculation is greatly reduced by reducing the termination processing of the ring memory 15 in the product-sum calculation loop, and high-speed operation can be performed.

Next, an arithmetic processing device according to a third embodiment of the present invention will be described with reference to the drawings. In the third embodiment, in a product-sum operation loop, filter calculation is performed simultaneously on four common times using four time-dependent filter coefficients for one common input data. It is characterized by. FIG. 7 shows a third embodiment of the present invention.
FIG. 2 is a block diagram illustrating a configuration of an arithmetic processing device according to the embodiment. The arithmetic processing device includes an input device 1 for inputting data, a data processing device 2 for performing a filter calculation on the input data, a storage device 3 for storing input data and filter coefficients, and an output device for outputting output data. And 4.

The storage device 3 comprises a ring memory 15 for storing input data and a filter coefficient storage unit 23 for storing filter coefficients. Ring memory 15
Has the same logical annular structure as in the first embodiment. As shown in FIG. 8, the filter coefficient storage unit 23 stores four filter coefficient registers 25 (FR (0) to
The filter coefficients (CF (0) to CF (0)) for the first to fourth times shown in FIG. 3 are divided by four taps so that the filter coefficients can be sequentially loaded into FR (3)). Is remembered.

Returning to FIG. 7, the data processing device 2 includes a parallel operation device 7, a data register 8, a filter coefficient register 25, an accumulation register 26, a ring memory start pointer 17, a ring memory end A pointer 18;
It comprises a write pointer 19, a read pointer 20, a filter coefficient head pointer 27, and a filter coefficient pointer 28.

The parallel operation device 7 and the data register 8
This is the same as the first embodiment. The ring memory start pointer 17, the ring memory end pointer 18, the write pointer 19, and the read pointer 20 are the same as those in the first embodiment, like the ring memory 15.

The filter coefficient register 25 has four 64
It is composed of bit registers (FR (0) to FR (3)), and loads filter coefficients for 4 × 4 taps stored in the filter coefficient storage unit 23. The accumulation register 26 includes four 64-bit registers (AR (0) to AR (3)), and sequentially accumulates intermediate results of four 4-parallel multiply-accumulate operations by the parallel operation device 7.

The filter coefficient start pointer 27 indicates a start address of an area for storing a filter coefficient set in the filter coefficient storage section 23 in advance. The filter coefficient pointer 28 stores the filter coefficient stored in the filter coefficient storage unit 23 in the filter coefficient register 25 (FR
(0) to FR (3)).

Hereinafter, four consecutive product-sum operations performed by the data processing device 2 will be described with reference to the drawings. As shown in FIG. 9, four consecutive times (time 4j to 4j +
The combination of the input data and the filter coefficient for which the product-sum operation is performed in 3) is the same except for the combination at the head as shown in FIG.
The input data is the same. That is, as shown in FIG. 10, except for the product-sum operation of the first combination (combination including the latest input data) in FIG. 9, the product-sum operation using the filter coefficient at each time is performed on the common input data. Becomes possible. Therefore, the data processing device 2 loads the input data into the data register 8 and
5 (FR (0) to FR (3)) are loaded with the first to fourth time filter coefficients, and four consecutive 4-parallel multiply-accumulate operations are performed. Each product-sum operation result is added to and stored in the accumulation register 26 (AR (0) to AR (3)). As a result, the data processing device 2 can reduce the number of times that the input data is loaded into the data register 8, so that the processing speed can be increased as a whole.

The operation of the data processor 2 for calculating the filter in a state where the filter coefficients are arranged in the filter coefficient storage unit 23 as shown in FIG. 8 will be described below with reference to FIG. FIG. 11 is a flowchart illustrating an operation of the filter calculation of the data processing device 2.

First, the data processing device 2 clears the values of the four registers (AR (0) to AR (3)) of the accumulation register 26 to zero (step S402).

The data processing device 2 has a read pointer 2
Initial values are set to 0 and the filter coefficient pointer 28 (step S404, step S405). The initial value of the read pointer 20 includes the write pointer 19
Set the value of.

Next, the data processing device 2 processes the first sum-of-products operation in which input data is not common in the four successive times of sum-of-products operations (first 4-tap processing 40).
0). First, the data processing device 2 performs a product-sum operation at time n. The data processing device 2 writes the input data obtained from the input device 1 to the address of the ring memory 15 indicated by the write pointer 19 and stores it (step S4).
06).

The data processing device 2 includes a ring memory 15
From the input data stored in the
The input data of 4 data stored at the address indicated by 0 is loaded into the data register 8 (step S40).
7).

The data processing device 2 converts the filter coefficients for four taps stored at the address indicated by the filter coefficient pointer 28 from the filter coefficients stored in the filter coefficient storage unit 23 into the filter coefficient register 26 (FR
(0)) (step S408).

The parallel operation device 7 performs a 4-parallel multiply-accumulate operation on the input data for 4 data loaded in the data register 8 and the filter coefficient for 4 taps loaded in the filter coefficient register 26 (FR (0)). Then, the operation result is stored in the accumulation register 26 (AR (0)) (step S40).
9).

The data processing device 2 similarly operates at time n +
The first product-sum operation is performed at 1, time n + 2, and time n + 3 (S410 to S421). Note that the data processing device 2
At time n + 1, the filter coefficient register 25 (FR
In (1)), the address indicated by the filter coefficient pointer 28+
8 is loaded, and at time n + 2, FR
In (2), the address indicated by the filter coefficient pointer 28 + 1
6, and at time n + 3, FR
(3) the address indicated by the filter coefficient pointer 28 + 2
Load the filter coefficients of 4. In addition, the parallel operation device 7
Is the accumulation register 26 (AR
The calculation result is stored in (1)), and at time n + 2, A
The calculation result is stored in R (2), and at time n + 3, A
The calculation result is stored in R (3).

The data processing device 2 determines whether or not processing for all filter taps has been completed (step S4).
22). When the data processing device 2 determines that the processing for all the filter taps has been completed, the data processing device 2 performs step S43 described later.
5 and the four 16s stored in the accumulation register 26
Calculate the sum of the number of bits.

On the other hand, if the data processing device 2 determines that the processing for all the filter taps has not been completed, the read pointer 20 stores 8 (4) in order to load the input data for 4 data into the data register 8. (For data) and updates with the value after the addition (step S423).

The data processing device 2 determines whether the value of the read pointer 20 after the update is larger than the value of the ring memory end pointer 18 (step S424). The value of 17 is substituted for the value of the read pointer 20 and updated (step S425).

The data processing device 2 adds 32 (for 4 × 4 taps) to the filter coefficient pointer 28 to load the filter coefficients for the next 4 × 4 taps into the filter coefficient register 25, and Update with value (Step S
426).

The data processing device 2 includes a ring memory 15
From the input data stored in the
The input data of 4 data stored at the address indicated by 0 is loaded into the data register 8 (step S42).
7).

The data processing device 2 converts the filter coefficients for 4 × 4 taps stored at the address indicated by the filter coefficient pointer 28 from the filter coefficients stored in the filter coefficient storage unit 23 into the filter coefficient register 25 (F
R (0) to FR (3)) (step S42).
8).

The parallel operation device 7 performs four parallel multiply-accumulate operations on the input data for four data loaded in the data register 8 and the filter coefficient loaded in the filter coefficient register 25, and stores the operation result in the accumulation register 26. Are added and stored (step S429). That is, the parallel operation device 7 adds the operation result of the input data and FR (0) to AR (0), stores the result, and stores the input data and FR (1).
Is added to AR (1) and stored, the operation result of input data and FR (2) is added to AR (2) and stored, and the operation result of input data and FR (3) is stored. AR
Add to (3) and store.

The data processing device 2 adds 8 (for 4 data) to the read pointer 20 to load the input data for the next 4 data into the data register 8 and updates the read pointer 20 with the value after the addition (step). S430).

The data processing device 2 determines whether or not the value of the updated read pointer 20 is greater than the value of the ring memory end pointer 18 (step S431). The value of 17 is assigned to the value of the read pointer 20 and updated (step S432).

The data processing device 2 adds 32 (for 4 × 4 taps) to the filter coefficient pointer 22 to load the filter coefficients for the next 4 × 4 taps into the filter coefficient register 25, and The value is updated with the value (step S433).

The data processing device 2 determines whether or not processing for all filter taps has been completed (step S4).
34). If the data processing device 2 determines that the process for all filter taps has not been completed, the process proceeds to step S427.
Then, the processing of steps S427 to S434 is repeated (product-sum calculation loop S401).

On the other hand, when the data processing device 2 determines that the processing for all the filter taps has been completed, the four 16-bit numbers stored in the accumulation registers 26 (AR (0) to AR (3)) respectively. Is calculated as the output data after the filter calculation (step S435).

The data processing device 2 sequentially outputs the obtained output data to the output device 4 (step S436).

The data processing device 2 adds 8 (for 4 data) to the write pointer 19 for the filter calculation for the next four times and updates it with the value after the addition (step S4).
37).

The data processing device 2 determines whether or not the value of the updated write pointer 19 is larger than the value of the ring memory end pointer 18 (step S438). The value of 17 is assigned to the value of the write pointer 19 and updated (step S439).

As described above, according to the invention of the third embodiment, the input data loaded in the data register 8 is used for the filter calculation at a plurality of times, so that the total number of times of loading can be reduced. And speed up the process. Also, in the filter coefficient register 25,
By loading the filter coefficients for four consecutive times at once, it is possible to reduce the total number of times of loading and speed up the processing. Further, by performing the product-sum operation processing at four consecutive times in the product-sum calculation loop 401, the number of entire loops can be reduced and the processing can be speeded up.

In the third embodiment, the end of the ring memory is performed each time in the product-sum calculation loop 401. However, the product-sum loop is divided into two as in the second embodiment. May be.

Next, an arithmetic processing unit according to a fourth embodiment of the present invention will be described with reference to the drawings. In the fourth embodiment, as in the third embodiment, the product-sum operation at eight consecutive times is performed in the product-sum operation loop. The calculation is performed. FIG. 12 is a block diagram illustrating a configuration of an arithmetic processing device according to the fourth embodiment of the present invention. The arithmetic processing device includes an input device 1 for inputting data, a data processing device 2 for performing a filter calculation on the input data, a storage device 3 for storing input data and filter coefficients, and an output device for outputting output data. 4
It is composed of

The storage device 3 comprises a ring memory 15 for storing input data and a filter coefficient storage unit 23 for storing filter coefficients. The ring memory 15 and the filter coefficient storage unit 23 are the same as in the third embodiment.

The data processing device 2 comprises a parallel operation device 7,
A data register 29, a filter coefficient register 25,
Accumulation register 30 and ring memory head pointer 17
, A ring memory end pointer 18, a write pointer 19, a read pointer 20, a filter coefficient head pointer 27, and a filter coefficient pointer 28.

The data processing device 2 includes a data register 29
And only the accumulation register 30 is different from the third embodiment of FIG. The data register 29 includes two 64-bit registers (DR (0), DR (1)), and loads input data of 2 × 4 data stored in the ring memory 15. The accumulation register 30 includes eight 64-bit registers (AR (0) to AR (7)).
, The intermediate results of eight 4-parallel multiply-accumulate operations are sequentially accumulated.

Hereinafter, eight consecutive product-sum operations performed by the data processing device 2 will be described with reference to the drawings. FIG.
As shown in FIG. 8, eight consecutive times (time 4j to 4j +
Regarding the combination of the input data and the filter coefficient for which the product-sum operation is performed in 7), the input data is the same except for the first combination. Furthermore, the first four times (time 4j to 4j +
At 3) and the remaining four times (time 4j + 4 to 4j + 7), as shown by the thick frame, the filter coefficients are the same with a shift of 4 taps. That is, as shown in FIG. 14, it is possible to perform a product-sum operation using a common filter coefficient after the elapse of four times. Therefore, the data processing device 2 loads the input data of 2 × 4 data into the data register 29 (DR (0), DR (1)), and loads the filter coefficient register 25 (F
R (0) to FR (3)) are loaded with filter coefficients for 4 × 4 taps, and eight consecutive 4-parallel multiply-accumulate operations are performed. Each product-sum operation result is stored in the accumulation register 30 (A
R (0) to AR (7)). As a result, the data processing device 2
9 and the number of times of loading input data and filter coefficients into the filter coefficient register 25 can be reduced.
As a whole, the processing can be speeded up.

Hereinafter, the operation of the filter calculation of the data processing device 2 in a state where the filter coefficients are stored in the filter coefficient storage unit 23 will be described with reference to FIG. FIG. 15 is a flowchart showing the operation of the filter calculation of the data processing device 2.

First, the data processing device 2 clears the values of the eight registers (AR (0) to AR (7)) of the accumulation register 30 to zero (step S503).

The data processing device 2 has a read pointer 2
Initial values are set to 0 and the filter coefficient pointer 28 (step S504, step S505).

Next, in the product-sum operation at eight consecutive times, the data processing device 2 processes the first product-sum operation in which input data is not common (first 4-tap processing S50).
0).

The data processing device 2 converts the filter coefficients for 4 × 4 taps stored at the address indicated by the filter coefficient pointer 28 from the filter coefficients stored in the filter coefficient storage section 23 into the filter coefficient register 26 (F
R (0) to FR (3)) (step S50).
6). Note that the filter coefficients loaded in FR (0) to FR (3) are used again in the product-sum operation after four times, so once loaded, they are used in the product-sum operation at eight consecutive times. It becomes possible.

The data processing device 2 writes the input data obtained from the input device 1
The data is written and stored at the address of the memory 15 (step S507).

At time n, the data processing device 2
From the input data stored in the memory 15, the input data for four data stored at the address indicated by the read pointer 20 is loaded into DR (1) of the data register 29 (step S508).

The parallel operation device 7 includes a data register 29
Four parallel multiply-accumulate operations are performed on the input data for four data loaded in (DR (1)) and the filter coefficients for four taps loaded in the filter coefficient register 26 (FR (0)). It is stored in the arithmetic register 30 (AR (0)) (step S509).

Similarly, the parallel operation device 2 operates at time n + 1,
The first product-sum operation at time n + 2 and time n + 3 is performed (steps S510 to S512). Note that the parallel operation device 7
At time n + 1, the accumulation register 26 (AR (1))
And at time n + 2, AR (2)
And at time n + 3, AR (3)
To store the operation result.

The data processing device 2 adds 8 (for 4 data) to the write pointer 19 for the product-sum operation for the next four times, and updates it with the value after the addition (step S51).
3).

The data processing device 2 determines whether or not the value of the updated write pointer 19 is larger than the value of the ring memory end pointer 18 (step S514). The value of 17 is assigned to the value of the write pointer 19 and updated (step S515).

The data processing device 2 has a read pointer 2
0 is set to the value of the write pointer 19 (step S
516).

The data processing device 2 writes the input data acquired from the input device 1
The data is written to the address of the memory 15 and stored. Time n +
4, the data processing device 2 loads the input data for four data stored at the address indicated by the read pointer 20 into the DR (0) of the data register 29 from the input data stored in the ring memory 15. (Step S517). The input data loaded to DR (0) is supplied to a sum-of-products calculation loop 501 described later from time n to time n.
This is used as data for +3. Here, by loading first, the subsequent time n + 4 to time n +
Even if the contents of the ring memory 15 are overwritten by the input data of 7, the product-sum operation can be performed.

At time n + 4, the data processor 2 converts the input data of four data stored at the address indicated by the read pointer 20 from the ring memory 15 into the DR.
(1), a 4-parallel product-sum operation is performed with the filter coefficient loaded in FR (0), and the operation result is stored in AR (4) (step S518).

The data processing device 2 similarly operates at time n +
5. The first product-sum operation is performed at time n + 6 and time n + 7 (steps S518 to S521). Note that, at time n + 5, the parallel operation device 7 sets the accumulation register 26 (AR
The calculation result is stored in (5)), and at time n + 6, A
The calculation result is stored in R (6), and at time n + 7, A
The calculation result is stored in R (7).

The data processing device 2 adds 32 (for 4 × 4 taps) to the filter coefficient pointer 28 to load the filter coefficients for the next 4 × 4 taps into the filter coefficient register 25, and Update with value (Step S
522).

The data processing device 2 determines whether or not processing for all filter taps has been completed (step S5).
23). When the data processing device 2 determines that the processing for all filter taps has been completed, the data processing device 2 performs step S53 described later.
3 to the eight 16 stored in the accumulation register 30.
Calculate the sum of the number of bits.

On the other hand, if the data processing device 2 determines that the processing for all the filter taps has not been completed, the data processing device 2 calculates the filter coefficients from the filter coefficients stored in the filter coefficient storage unit 23.
The filter coefficients for 4 × 4 taps stored at the address indicated by the filter coefficient pointer 28 are loaded into the filter coefficient registers 26 (FR (0) to FR (3)) (step S524).

The parallel operation device 2 calculates time n, time n + 1,
The product-sum operation at time n + 2 and time n + 3 is performed (step S
525). That is, the parallel operation device 2 adds the operation result to AR (0) and stores it at time n, adds the operation result to AR (1) at time n + 1, and stores the operation result at time n + 2. Is added to AR (2) and stored, and at time n + 3,
The calculation result is added to AR (3) and stored.

The data processing device 2 adds 8 (for 4 data) to the read pointer 20 and loads the read pointer 20 with the value after the addition in order to load the input data for the next 4 data into the data register 8 (step). S526).

The data processing device 2 determines whether or not the value of the read pointer 20 after the update is larger than the value of the ring memory end pointer 18 (step S527). The value of 17 is assigned to the value of the read pointer 20 and updated (step S528).

The data processing device 2 includes a ring memory 15
From the input data stored in the
The input data for four data stored at the address indicated by 0 is loaded into DR (0) of the data register 29 (step S529).

The parallel operation device 2 calculates the time n + 4, the time n +
5, a product-sum operation at time n + 6 and time n + 7 is performed (step S530). That is, the parallel operation device 2 calculates the time n + 4
Is added to AR (4), and the result is stored at time n +
5, the arithmetic result is added to AR (5) and stored.
The arithmetic result is added to AR (6) and stored at +6, and the arithmetic result is added to AR (7) and stored at time n + 7.

The data processing device 2 adds 32 (for 4 × 4 taps) to the filter coefficient pointer 22 in order to load the filter coefficients for the next 4 × 4 taps into the filter coefficient register 25, and The value is updated with the value (step S531).

The data processing device 2 determines whether or not the processing for all filter taps has been completed (step S53).
2). If the data processing device 2 determines that the processing for all filter taps has not been completed, the process returns to step S524, and repeats the processing of steps S524 to S532 (product-sum calculation loop S501).

On the other hand, when the data processing device 2 determines that the processing for all the filter taps has been completed, the four 16-bit numbers stored in the accumulation registers 30 (AR (0) to AR (7)) respectively. Is calculated and used as output data after the filter calculation (step S533).

The data processing device 2 sequentially outputs the obtained output data to the output device 4 (step S534).

The data processing device 2 adds 8 (for 4 data) to the write pointer 19 for the product-sum operation for the next first four times, and updates the value with the added value (step S).
535).

The data processing device 2 determines whether or not the value of the updated write pointer 19 is larger than the value of the ring memory end pointer 18 (step S536). The value of 17 is assigned to the value of the write pointer 19 and updated (step S537).

As described above, according to the fourth embodiment, in addition to using the input data loaded in the data register 29 for the product-sum operation at a plurality of times, the filter coefficient register By using the filter coefficients loaded in the block 25 for the multiply-accumulate operation at a plurality of times, the overall number of loads can be reduced and the processing can be sped up. Further, by loading the filter coefficients for eight consecutive times into the filter coefficient register 25 at one time, the total number of times of loading can be reduced and the processing speed can be increased. Further, in the product-sum calculation loop 501, 84
By performing the product-sum operation at two consecutive times,
The number of entire loops can be reduced, and the processing can be speeded up.

In the fourth embodiment, the termination of the ring memory is performed every time in the product-sum calculation loop 501. However, the product-sum loop is divided into two as in the second embodiment. May be.

Next, an arithmetic processing unit according to a fifth embodiment of the present invention will be described with reference to the drawings. Here, a case will be described as an example where a complex FIR filter calculation in which each of input data, output data, and filter coefficients has a real part and an imaginary part is performed. The complex number FIR filter is represented by x in the FIR filter shown in Equation 1.
(N), y (n) and a (k) are each converted to a complex number xc
(N), yc (n), ac (k),
It is represented by Expression 8.

[0186]

(Equation 8) xc (n): input data (complex number) at time n yc (n): output data (complex number) at time n n: time (n = 0, 1, 2,...) ac (k): filter coefficient (complex number) ) (K = 0, 1,
2,..., M-1) M: Number of filter taps (filter length)

The complex numbers xc (n), yc (n), a
c (k) is expressed by Expressions 9 to 11.

[0188]

Xc (n) = xr (n) + xi (n) · j xc (n): input data (complex number) at time n xr (n): real part xi (n): imaginary part j: imaginary number Unit (j × j = -1)

[0189]

Yc (n) = yr (n) + yi (n) · jic (n): output data (complex number) at time n yr (n): real part yi (n): imaginary part j: imaginary number Unit (j × j = -1)

[0190]

[Mathematical formula-see original document] ac (k) = ar (k) + ai (k) .jac (k): filter coefficient (complex number) (k = 0, 1,
2,..., M-1) ar (n): real part ai (n): imaginary part j: imaginary unit (j × j = −1)

Therefore, the complex FIR filter shown in Expression 8 can be modified by Expressions 9 to 11, and is expressed by Expression 12.

[0192]

(Equation 12) xc (n): input data at time n (complex number) yc (n): output data at time n (complex number) ac (k): filter coefficient (complex number) (k = 0, 1,
2,..., M-1) xr (n), yr (n), ar (n): real part xi (n), yi (n), ai (n): imaginary part j: imaginary unit (j × j = -1)

Hereinafter, the complex FIR filter will be specifically described. The input data is xr (0), xi
(0), xr (1), xi (1), xr (2), xi
(2), suppose that the real part and the imaginary part are inputted alternately. In this case, as shown in Expression 12, the real part yr (n) of the output data yc (n) is ar
(0), -ai (0), ar (1), -ai (1), a
It can be obtained by a 2M tap FIR filter using r (2), -ai (2),... as coefficients. Similarly, the imaginary part yi (n) of the output data yc (n) is ai
(0), ar (0), ai (1), ar (1), ai
(2), 2M taps with ar (2),.
Can be obtained by the following FIR filter.

The complex number FIR filter has a function of yr (0), yi in the same manner as the input of the real part and the imaginary part in the input data.
(0), yr (1), yy (1), yr (2), yy
(2) To output the real part and the imaginary part alternately as shown in FIG. 16, the coefficient for the real part calculation and the coefficient for the imaginary part calculation calculate each output data as shown in FIG. Are arranged alternately in four types of coefficient sequences corresponding to the operations required to perform the operations. That is, the odd-numbered output filters include ar (0), -ai (0), and ar, which are coefficients for calculating the real part.
(1), -ai (1), ar (2), -ai (2),
・ ・ Is arranged. On the other hand, even-numbered output filters include ai (0), ar, which are coefficients for calculating an imaginary part.
(0), ai (1), ar (1), ai (2), ar
(2),... Are arranged.

The arithmetic processing apparatus according to the fifth embodiment is characterized in that filter calculations are performed using filter coefficients having different arrangements in correspondence with calculations required for each output data. Therefore, the arithmetic processing device according to the fifth embodiment can also be realized in an arithmetic processing device having a conventional configuration as shown in FIG. At that time, the filter coefficient storage unit 106 stores in advance filter coefficients having different arrangements in correspondence with calculations required for each output data. That is, when performing a filter calculation using a complex FIR filter, the arithmetic processing device previously stores filter coefficients as shown in FIG. 16 in the filter coefficient storage unit 106, as described above.

Hereinafter, the filter coefficients shown in FIG. 16 will be described in detail. The filter coefficient sequence CFc (0) is
, 4i + 1 (i is an integer equal to or greater than 0) are the filter coefficients used for calculating the output, and therefore the coefficients for the real part calculation are stored. On the other hand, since the filter coefficient sequence CFc (1) is a filter coefficient used for calculating the second, sixth, ten,..., 4i + 2nd outputs,
Stores coefficients for imaginary part calculation. Filter coefficient sequence CFc
(2) stores a coefficient sequence obtained by shifting each coefficient of CFc (0) by two coefficients. Similarly, the filter coefficient sequence CFc
(3) stores a coefficient sequence obtained by shifting each coefficient of CFc (1) by two coefficients. This is because, as described in the description of the related art, loading from an address that is a multiple of 8 can be executed faster than loading from an address that is not a multiple of 8. 2
As shown in FIG. 6, the same effect as storing four types of coefficient sequences in which the position of each coefficient is shifted in the filter coefficient storage unit 106 is obtained.

The arithmetic processing unit sequentially performs a filter calculation on input data to which a real part and an imaginary part are input alternately according to the flowchart of FIG. 28 to calculate output data composed of the real part and the imaginary part. As described above, the arithmetic processing device according to the fifth embodiment can be realized by merely changing the filter coefficient array to, for example, an array of complex FIR filters without changing the configuration of the device and the operation flow of the data processing device. , Required output data consisting of a real part and an imaginary part can be calculated.

As described above, according to the invention of the fifth embodiment, the arrangement of the filter coefficients stored in advance in the filter coefficient storage unit 106 corresponds to the calculation required for each output data. By setting the filter coefficients different from each other, filter calculations required for each output data can be executed.

In the above-described fifth embodiment, the configuration of the arithmetic processing unit and the flow of operation of the data processing unit have been described as being the same as in the conventional technology. However, these need not be the same as in the conventional technology. Instead, for example, the configuration of the arithmetic processing device and the operation flow of the data processing device described in the first embodiment of the present invention can be used. In this case, the arrangement of the filter coefficients stored in the filter coefficient storage unit 16 has a circular structure in which the head and the end are logically connected as described in the first embodiment of the present invention.

In the above embodiment, a 64-bit ALU is used.
The filter calculation was performed by a 4-parallel multiply-accumulate operation in which four 16-bit multiply-accumulate operations are performed in parallel using the divided ALU method using the parallel arithmetic unit 7 consisting of Optional. For example, a 32-bit ALU may be used to perform filter calculation by two-parallel product-sum operation.
Also, an ALU that obtains the results of four 16-bit multiply-accumulate operations by two 32-bit numerical values may be used. ALU
When the number of bits of the register is changed, the bit of each register
The numbers shall also change.

Further, in the above embodiment, in the data processing device 2, the memory (such as the ring memory 15) of the address of a multiple of 8 is used to change the register (such as the data register 8).
Has been described in the case of fast loading to the
This load address is arbitrary. For example, a register may be loaded at a high speed from a memory having an address which is a multiple of four. When the load address is changed, the arrangement of data stored in the memory (such as the ring memory 15) is also changed accordingly.

The arithmetic processing unit according to the present invention can be realized using a general computer system without using a dedicated system. For example, by installing a computer from a medium (a floppy disk, a CD-ROM, or the like) storing a program for executing the above-described operation, an arithmetic processing unit that executes the above-described processing can be configured. .

The medium for supplying the program to the computer may be a communication medium (a medium that temporarily and fluidly holds the program, such as a communication line, a communication network, or a communication system). For example, the program may be posted on a bulletin board (BBS) of a communication network and distributed via the network. Then, by starting this program and executing it in the same manner as other application programs under the control of the OS, the above-described processing can be executed.

[0204]

As described above, in an arithmetic processing device utilizing the parallel arithmetic processing of the divided ALU system, it is possible to efficiently use the memory and execute the arithmetic processing at a high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an arithmetic processing device according to a first embodiment of the present invention.

FIG. 2 is a schematic diagram illustrating an array of input data of a ring memory 15;

FIG. 3 is a schematic diagram illustrating an array of filter coefficients in a filter coefficient storage unit 16;

FIG. 4 is a schematic diagram illustrating an array of input data of a ring memory 15 and a filter coefficient of a filter coefficient storage unit 16;

FIG. 5 is a flowchart illustrating a filter calculation process of the arithmetic processing device according to the first embodiment of the present invention;

FIG. 6 is a flowchart illustrating a filter calculation process of an arithmetic processing device according to a second embodiment of the present invention;

FIG. 7 is a block diagram illustrating a configuration of an arithmetic processing device according to a third embodiment of the present invention;

8 is a schematic diagram illustrating an array of filter coefficients in a filter coefficient storage unit 23. FIG.

FIG. 9 is a schematic diagram illustrating an array of input data of a ring memory 15 and a filter coefficient of a filter coefficient storage unit 23;

FIG. 10 is a schematic diagram illustrating a product-sum operation of input data and a filter coefficient.

FIG. 11 is a flowchart illustrating a filter calculation process of an arithmetic processing device according to a third embodiment of the present invention;

FIG. 12 is a block diagram illustrating a configuration of an arithmetic processing device according to a fourth embodiment of the present invention.

FIG. 13 is a schematic diagram illustrating an array of input data of a ring memory 15 and a filter coefficient of a filter coefficient storage unit 23.

FIG. 14 is a schematic diagram illustrating a product-sum operation of input data and a filter coefficient.

FIG. 15 is a flowchart illustrating a filter calculation process of an arithmetic processing device according to a fourth embodiment of the present invention.

FIG. 16 is a schematic diagram illustrating an example of a filter coefficient stored in a filter coefficient storage unit of an arithmetic processing device according to a fifth embodiment of the present invention.

FIG. 17 is a schematic diagram illustrating parallel processing of the divided ALU system.

FIG. 18 is a schematic diagram illustrating a combination of a filter coefficient and input data.

FIG. 19 is a block diagram showing a configuration of a conventional arithmetic processing device.

20 is a schematic diagram illustrating an array of input data in an input data storage unit 105. FIG.

FIG. 21 is a schematic diagram illustrating a 4-parallel multiply-add operation of the divided ALU system.

FIG. 22 is a schematic diagram illustrating a combination of input data and a filter coefficient.

FIG. 23 is a schematic diagram illustrating data loading of a data register and a filter coefficient register.

FIG. 24 is a schematic diagram illustrating a fractional part of a filter coefficient when the sum of the filter coefficients stored in the filter coefficient storage unit is not a multiple of four;

FIG. 25 is a schematic diagram for explaining a state where a position of the data register for loading input data for each time changes.

FIG. 26 is a schematic diagram illustrating an array of filter coefficients in a filter coefficient storage unit 16;

FIG. 27 is a schematic diagram illustrating a combination of input data and a filter coefficient.

FIG. 28 is a flowchart illustrating a filter calculation process of a conventional arithmetic processing device.

[Explanation of symbols]

 Reference Signs List 1 input device 2 data processing device 3 storage device 4 output device 7 parallel operation processing device 8 data register 9 filter coefficient register 10 accumulation register 15 ring memory 16 filter coefficient storage unit 17 ring memory head pointer 18 ring memory end pointer 19 Write Pointer 20 Read Pointer 21 Filter Coefficient Top Pointer 22 Filter Coefficient Pointer 23 Filter Coefficient Storage Unit 25 Filter Coefficient Register 26 Accumulation Register 27 Filter Coefficient Top Pointer 28 Filter Coefficient Pointer 29 Data Register 30 Accumulation Register 101 Input Device 102 Data Processing Device 103 Storage device 104 Output device 107 Parallel operation processing device 108 Data register 109 Filter coefficient register 110 Accumulation register 111 Ring memo 112 filter coefficient storage unit 113 ring memory head pointer 114 ring memory end pointer

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 7/00 G06F 17/10 H03H 17/02 635

Claims (12)

(57) [Claims] 1. A division ALU (Arithmetic and Logic Uni)
t) An arithmetic processing device comprising parallel arithmetic means for executing an arithmetic operation on input data and a filter coefficient in parallel in order to filter input data in a parallel arithmetic processing using an ALU of the t) type. Input data storage means for sequentially storing the input data in a storage area having a circular structure in which a head and an end are logically connected, and each input data stored in the input data storage means
Filter coefficient storage means in which storage areas are filled with filter coefficients arranged in a one-to-one correspondence, and input of a predetermined data amount required for the parallel operation means to perform parallel operation processing Input data temporary storage means for reading and temporarily storing data from the input data storage means; and a filter coefficient storage means for storing a filter coefficient of a predetermined data amount required for the parallel operation means to perform parallel operation processing. And a filter coefficient temporary storage means for reading and temporarily storing the input data from the input data read from the input data temporary storage means and the filter coefficient read into the filter coefficient temporary storage means. An arithmetic processing device for performing a sum operation and filtering input data. 2. The input data storage means arranges input data in accordance with a predetermined start position at which the input data temporary storage means starts reading input data, and the filter coefficient storage means comprises: The filter coefficients are arranged in a storage area having a ring structure in which a head and an end are logically connected according to a predetermined start position at which the coefficient temporary storage means starts reading the filter coefficients. The arithmetic processing device according to claim 1. 3. An arithmetic processing device having parallel arithmetic means for executing an arithmetic operation on input data and a filter coefficient in parallel in order to filter input data in a parallel arithmetic processing using an ALU of a divided ALU system. Input data storage means for sequentially storing input data in a storage area having a circular structure in which a head and an end are logically connected; and each of the input data stored in the input data storage means
Filter coefficient storage means in which storage areas are filled with filter coefficients arranged corresponding to pairs n (n is a natural number of 2 or more); and An input data temporary storage unit that reads one input data sequence having a determined data amount from the input data storage unit and temporarily stores the input data sequence; and the input data temporary storage unit so that the parallel operation unit performs a parallel operation process. A filter coefficient temporary storage means for reading from the filter coefficient storage means and temporarily storing the n filter coefficient strings having a data amount of n times the input data string of one column temporarily stored in the means; The calculating means predicts one input data string read into the input data temporary storage means and n filter coefficient strings read into the filter coefficient temporary storage means. And product-sum operation in a defined order to filter the input data, it arithmetic processing unit according to claim. 4. The filter coefficient temporary storage means, wherein the input data temporary storage means stores one input data string as m (m
4. The arithmetic processing device according to claim 3, wherein, while reading (n is a natural number of 2 or more) times, n filter coefficient sequences are read once. 5. 5. An arithmetic processing unit having parallel arithmetic means for executing an arithmetic operation on input data and a filter coefficient in parallel in order to filter input data in a parallel arithmetic processing using an ALU of the divided ALU system. Input data storage means for sequentially storing input data in a storage area; each input data stored in the input data storage means;
Filter coefficient storage means in which a storage area is filled with filter coefficients arranged in correspondence with an operation required to calculate output data from each input data, and the parallel operation means executes parallel operation processing. Input data temporary storage means for reading input data of a predetermined data amount necessary for performing the input data storage means from the input data storage means and temporarily storing the input data; A filter coefficient temporary storage means for reading and temporarily storing a filter coefficient of a predetermined data amount from the filter coefficient storage means, wherein the parallel operation means includes input data read into the input data temporary storage means and Multiply and accumulate with the filter coefficient read into the filter coefficient temporary storage means and filter the input data. Arithmetic processing unit. 6. A filter calculation method comprising a parallel operation step of executing an operation of input data and a filter coefficient in parallel in order to filter input data in a parallel operation process using an ALU of the divided ALU system. An input data storage step of sequentially storing input data in a storage area having a circular structure in which a head and an end are logically connected; and a predetermined processing required for performing parallel operation processing in the parallel operation step. An input data temporary storage step of reading input data of the obtained data amount from the storage area stored in the input data storage step and temporarily storing the input data, and a parallel operation step required for performing the parallel operation processing in the parallel operation step. The filter coefficient of the determined data amount is one-to-one with each input data stored in the input data storage step. A filter coefficient temporary storage step of reading from a storage area in which the correspondingly arranged filter coefficients are satisfied and temporarily storing the filter coefficient, and the parallel operation step includes a step of temporarily storing input data in the input data temporary storage step. A filter calculation method, comprising: performing a product-sum operation on the input data read into the storage area and the filter coefficient read into the filter coefficient temporary storage area in the filter coefficient temporary storage step to filter the input data. 7. The parallel operation step, wherein the input data read into the input data temporary storage area in the input data temporary storage step is stored between a reading start position of the storage area and an end position of the storage area. The filter coefficient is stored in the filter coefficient temporary storage step in the filter coefficient temporary storage step. 7. The filter calculation method according to claim 6, wherein a sum operation is performed and the input data is filtered. 8. A filter calculation method comprising a parallel operation step of executing an operation of input data and a filter coefficient in parallel in order to filter input data in a parallel operation process using an ALU of the divided ALU system. An input data storage step of sequentially storing input data in a storage area having a circular structure in which a head and an end are logically connected, and in order to perform parallel operation processing in the parallel operation step,
An input data sequence of one column having a predetermined data amount is
An input data temporary storage step of reading from a storage area stored in the input data storage step and temporarily storing the input data, and performing a parallel operation process in the parallel operation step.
An n-number of filter coefficient strings, which are n times as large as the one-row input data string temporarily stored in the input data temporary storing step, are arranged in a one-to-n relationship with each input data stored in the input data storing step. A filter coefficient temporary storage step of reading from a storage area in which the correspondingly arranged filter coefficients are satisfied and temporarily storing the filter coefficient, and the parallel operation step includes a step of temporarily storing input data in the input data temporary storage step. Performing a product-sum operation in a predetermined order between the one input data string read into the storage area and the n filter coefficient strings read into the filter coefficient temporary storage area in the filter coefficient temporary storage step. A filter calculation method characterized by the following. 9. A filter calculation method comprising a parallel operation step of executing an operation of input data and a filter coefficient in parallel in order to filter input data in a parallel operation process using an ALU of the divided ALU system. An input data storage step of sequentially storing input data in a storage area; and a predetermined data amount of input data required for performing a parallel operation process in the parallel operation step. The input data storage step of temporarily storing the input data by reading from the storage area stored by the input data storage unit, and a filter coefficient of a predetermined data amount required for performing the parallel operation processing in the parallel operation step. Required to calculate output data from each input data stored in each step and each input data And a filter coefficient temporary storage step of temporarily reading and storing from a storage area in which the filter coefficients arranged corresponding to the calculation are satisfied, and wherein the parallel operation step is performed in the input data temporary storage step. A filter for performing a product-sum operation on the input data read into the input data temporary storage area and the filter coefficient read into the filter coefficient temporary storage area in the filter coefficient temporary storage step to filter the input data. Method of calculation. 10. A computer-readable recording medium for recording a program for causing a computer to function as an arithmetic processing unit, the computer comprising: a storage area having an annular structure in which input data is logically connected to a head and an end. Input data storage means for sequentially storing the input data stored in the input data storage means, and filter coefficient storage means for storing filter coefficients arranged in a one-to-one correspondence with each input data stored in the input data storage means. An input data temporary storage unit that reads a predetermined amount of input data from the input data storage unit and temporarily stores the input data so that the parallel operation unit performs the parallel operation process; In order to perform, a filter coefficient of a predetermined data amount is read from the filter coefficient storage means and temporarily stored. A filter coefficient temporary storage means, and an ALU of a divided ALU system for filtering input data between the input data read into the input data temporary storage means and the filter coefficient read into the filter coefficient temporary storage means. A computer-readable recording medium in which a program for functioning as a parallel operation means for executing a product-sum operation in parallel in a parallel operation process is recorded. 11. A computer-readable recording medium for recording a program for causing a computer to function as an arithmetic processing unit, the computer comprising: a storage area having an annular structure in which input data is logically connected to a head and an end. , And a storage area filled with filter coefficients arranged in a one-to-n (n is a natural number of 2 or more) correspondence with each input data stored in the input data storage means. A filter coefficient storage means stored in advance and an input for temporarily storing one input data string having a predetermined data amount from the input data storage means in order for the parallel operation means to perform parallel operation processing. The temporary data storage means and the input data of one column temporarily stored in the input data temporary storage means for the parallel operation means to perform the parallel operation processing. Filter coefficient temporary storage means for reading and temporarily storing an n-th filter coefficient sequence having a data amount n times as large as the force data sequence from the filter coefficient storage means, and an input of one column read into the input data temporary storage means In order to filter the input data, the data sequence and the n-th filter coefficient sequence read into the filter coefficient temporary storage means are divided into
A computer-readable recording medium in which a program for functioning as a parallel operation means for executing a product-sum operation in a predetermined order in parallel in a parallel operation process using an LU ALU is recorded. 12. A computer-readable recording medium for recording a program for causing a computer to function as an arithmetic processing device, the computer comprising: input data storage means for sequentially storing input data in a storage area; A filter coefficient storage unit in which a storage area is filled with filter coefficients arranged in correspondence with each input data stored in the means and an operation required to calculate output data from each input data; An input data temporary storage unit that reads a predetermined amount of input data from the input data storage unit and temporarily stores the input data so that the parallel operation unit performs the parallel operation process; In order to perform the processing, a filter coefficient of a predetermined data amount is read from the filter coefficient storage means and temporarily stored. A filter coefficient temporary storage means for storing the input data read in the input data temporary storage means and a filter coefficient read in the filter coefficient temporary storage means for filtering input data;
A computer-readable recording medium in which a program for functioning as a parallel operation means for executing a product-sum operation in parallel in a parallel operation process using U is recorded.