JP3326232B2 - Video signal synchronizing apparatus and synchronizing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronizing apparatus for synchronizing a video signal without using a delay circuit and a method therefor.

[0002]

2. Description of the Related Art In a still video device such as a still video camera, a luminance signal Y and color signals R, G and B obtained by a color image sensor are converted into, for example, a luminance signal Y and a color difference line sequential signal LSC (Line- Sequential R-
Y, BY differential Color signal) for recording and playback. Luminance signal Y and color difference line sequential signal L
The SC is FM-modulated by carrier waves of different frequencies, and is multiplex-recorded together with a predetermined synchronization signal, ID signal and the like. At the time of reproduction, a luminance signal and a color difference line-sequential signal are separated by a low-pass filter and a high-pass filter, subjected to predetermined processing such as demodulation, and output.

Here, the color difference line-sequential signal LSC is such that the color difference signal RY and the color difference signal BY correspond to the horizontal scanning period (1H).
Are reproduced alternately for each color, so that the chrominance signal RY synchronized with the luminance signal can be displayed on a monitor or the like.
And BY need to be obtained. Therefore, the conventional reproducing circuit includes, as shown in FIG. 7, a memory means (RAM) for temporarily storing the color difference line sequential signal LSC. One of the color difference signals is delayed by a delay circuit, and the color difference signal R- Y
And BY were simultaneously written in the respective RAMs. That is, the determination circuit 92 determines whether the color-difference line-sequential signal demodulated by the color-signal FM demodulation circuit 91 is the color-difference signal RY or BY.
Delayed by 1H (horizontal scanning period) by the delay circuit 93,
A / D conversion is performed by A / D converters 95 and 96 via the switch circuit 94 simultaneously with the color difference signal RY output after 1H, and the respective signals are simultaneously converted to the corresponding RY signal memories 97 and BY. The signals are stored in the signal memory 98 sequentially.

When signals for one screen (one field or one frame) are stored in memory in this manner, each memory 97,
The data of the same address is read out simultaneously from the data 98 and the color difference line-sequential signals RY and BY are synchronized.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned prior art, and has as its object to realize synchronization of video signals with a simpler configuration without using a delay circuit.

[0006]

SUMMARY OF THE INVENTION To achieve this object, the present invention provides
One screen of video is output for each horizontal line
Luminance signal and two types output alternately for each horizontal line
A color difference signal into a video signal which is temporally simultaneous, comprising a luminance signal and two types of color difference signals.
Area for each screen is stored for each horizontal line.
Memory means corresponding to each of the signals, and the brightness
Signal and the two types of color difference signals to the respective memory means.
Writing is performed at different periods, and the
Single memory control to perform simultaneous reads
The memory control means comprises: a vertical scan;
The luminance signal output during the period is stored in the corresponding memory means.
Write sequentially for each flat line, and use one water for another vertical scanning period
The above two types of color difference signals output alternately for each flat line
Each corresponding memory means has one horizontal line equivalent area
Write sequentially every other area, and in another vertical scanning period
The above two types of color difference output alternately for each horizontal line
The signal is transferred to the one horizontal line of the unwritten data of each corresponding memory means.
In the area corresponding to the in, and after the above writing is completed,
The luminance signal and the two types of
The color difference signals are simultaneously read out sequentially and synchronized .

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below based on illustrated embodiments. FIG. 1 is a block diagram showing a circuit configuration of a still video device to which the present invention is applied. First, an outline of a still video device to which the present invention is applied will be described with reference to FIG.

Recording tracks are formed on the magnetic disk 11 in a predetermined format, and a luminance signal Y and a chrominance signal C (color difference line sequential signal LSC) are FM-modulated on these tracks together with a predetermined synchronization signal to perform multiplex recording. Have been. The multiplexed FM modulation signal recorded on the magnetic disk 11 is read by a magnetic head 21, amplified by a head amplifier 23, a luminance signal Y is extracted by a high-pass filter 25, and a color difference line sequential signal LSC is extracted by a low-pass filter 27. .

The luminance signal Y is supplied to a luminance signal FM demodulation circuit 29.
Is demodulated. The demodulated luminance signal is output from the A / D converter 3
The signal is converted into a digital signal by 1 and stored in the luminance signal memory 33. On the other hand, the synchronization signal separation / pulse generation circuit 5
7 detects the horizontal and vertical synchronizing signals included in the demodulated luminance signal, sends them to the memory controller 61, and generates a pulse signal. Sampling clock generator 59
Generates a sampling clock fs via a PLL circuit or the like based on the pulse signal. The A / D converter 31
The luminance signal is A / S synchronized with this sampling clock fs.
D Convert. Also, this sampling clock fs is
Memory controller 61 and system controller 6
7 is output. And the sampling clock fs is
It is used for the operation of the address counter in the memory controller 61.

The FM modulated chrominance signal extracted by the low-pass filter 27 is demodulated by a chrominance signal FM demodulator 41.
The digital signal is converted by the D converter 43 into a color difference line-sequential signal LSC. The color difference signal RY is stored in the RY signal memory 45, and the color difference signal BY is stored in the BY signal memory 47. Note that the color difference line sequential signal LSC is a color difference signal RY, B which is alternately read from the magnetic disk 11.
−Y, which is a signal output from the A / D converter 43. The color difference line-sequential signal LSC is input to a synchronization signal separation / pulse generation circuit 57. The synchronization signal separation / pulse generation circuit 57 outputs to the memory controller 61 a line index signal for determining whether the color difference signal is RY or BY based on the level of the color difference line sequential signal LSC.

The conversion processing of the A / D converters 31 and 43 and the writing processing to the memories 33, 45 and 47 are controlled by the memory controller 61 in synchronization with the sampling clock fs output from the sampling clock generator 59. Is done.

When the memory of the video signal for one field is completed, the memory controller 61 causes the memories 33, 45,
47, the luminance signal Y and the color difference signals RY and BY are sequentially read. The luminance signal read from the luminance signal memory 33 is converted into an analog signal by a D / A converter 35, and a high-pass component is removed by a low-pass filter 37.
The synchronization signal is mixed and output to the interface 69. On the other hand, the color difference signals RY and BY stored in the RY signal memory 45 and the BY signal memory 47 are also read out at the same time as the luminance signal Y, and are converted into analog signals by the D / A converters 49 and 53. The signal is converted and the high-frequency components are removed by the low-pass filters 51 and 55, and then output to the encoder circuit 69. The encoder circuit 69 generates a video signal of a standard suitable for a monitor device, a connected personal computer, and the like from the three input signals and outputs the video signal.

The magnetic disk 11 is driven to rotate at a predetermined rotational speed, in this embodiment, 3600 rpm, by a spindle motor 15 controlled by a system controller 67. The system controller 67 controls the magnetic disk 11
The PG coil 17 detects the passage of the upper PG yoke 13 and detects one rotation of the magnetic disk 11 and controls the rotation phase. The rotation speed of the magnetic disk 11 is controlled by the FG pulse output in conjunction with the rotation of the spindle motor 15. Control.

The above is an outline of the present still video apparatus. The features of the present invention will be described in more detail with reference to FIGS. In the present embodiment, three memories 33, 45,
47 addresses are managed. During reproduction, the luminance signal is stored in the memory 33 at the first rotation of the magnetic disk 11, and the RY and BY signals are alternately stored in the memories 45 and 47 in the order of output at the second and third rotations. There is a feature. FIG. 2 shows an output timing chart of the color-difference color signals RY and BY, and FIGS. 3 and 4 schematically show modes of the memories 45 and 47. The memories 45 and 47 have a horizontal address and a vertical address, and are configured to store 1H signals in a row having the same vertical address. The luminance memory 33 has the same configuration. These horizontal and vertical addresses are managed by an address counter of the memory controller 61, but are assumed to be managed by a horizontal address counter and a vertical address counter for easy understanding.

In the color difference line sequential signal LSC, the reference levels of the color difference signals RY and BY are different as shown in FIG. Therefore, by detecting this reference level,
Which of the color difference signals RY and BY is output can be detected. The synchronization signal separation and pulse generation circuit 57
As a result, a line index for determining either the signal RY or BY is generated, and the memory controller 6
1 and the memory controller 61 uses the line index signal to output the RY and BY signal memory 4.
5 and 47 are selected. When recording is started, the memory controller 61 of this embodiment writes only the luminance signal Y after first detecting the vertical synchronization signal V. That is, when the horizontal synchronizing signal H is detected thereafter, the writing of the luminance signal Y starts from the first initial address (horizontal address = 0, vertical address = 0), and every time the luminance signal Y is output, the horizontal address counter is incremented. After counting up, the luminance signal Y for one horizontal line is written. Then, the horizontal synchronization signal H
Is output, the vertical address counter is counted up, the horizontal address counter is cleared, and the same writing is started.

The above processing is repeated until the vertical synchronizing signal V is output, that is, until writing for one track and one screen is completed. In the case of field recording, a luminance signal for one track (one field) is recorded, and in the case of frame recording, a luminance signal for two tracks (two fields) is recorded. In this embodiment, field recording is performed.

When the recording in the first cycle is completed, the color difference line sequential signal is written in the reproduction in the second and third cycles. In the second round, the writing of the color difference line sequential signal is started from the first initial address (horizontal address 0, vertical address 0).
If the first color-difference line-sequential signal is RY based on the line index, the color-difference line-sequential signal is counted up by a horizontal address counter while the RY signal memory 4
When the writing to 5 is completed and the writing for one horizontal line is completed, the vertical address counter is incremented by one, the horizontal address counter is returned to the initial value (0), the BY signal memory 47 is selected, and the next output is output. The color difference line sequential signal, that is, BY, is written into the BY signal memory 47.

When the writing of the color difference line sequential signal for one horizontal line, that is, BY, is completed, the horizontal address counter is returned to the initial value, the vertical address counter is counted up by one, and the RY signal memory 45 of the row is read. Is written with a color difference line sequential signal, that is, RY. Similar processing for one screen
(For one vertical scanning period) , the RY signal memory 4
5, one row ( one horizontal line phase) is stored in the BY signal memory 47;
The color difference signal signals RY and BY are written every (for this area) .

When the memory of the second cycle is completed, the memory controller 61 starts from the second initial address (vertical address counter = 1, horizontal address counter = 0) incremented by one in the vertical address counter, as in the second cycle. The third round write processing is performed. By the writing process in the third cycle, the empty row (the area corresponding to one horizontal line)
Color already recorded in the unwritten area left every minute)
The color difference signal corresponding to the difference signal is sequentially written, and
Each of rows 5, 47 is filled with signals.

When the writing is completed, the luminance signal memory 33, the RY signal memory 45, the BY signal memory 4
7, signals of the same address are sequentially read. By this reading, the video signals are synchronized as shown in FIG.

The above memory process will be described in more detail with reference to the flowchart shown in FIG. The control of the entire apparatus, such as the control of the spindle motor 15, is performed by the system controller 67. When reproduction starts, the memory controller 61 sets the first initial address in the horizontal and vertical address counters (S101),
Put the luminance signal memory 33 in a writable state (S10
3). Then, the memory of the luminance signal output from the A / D converter 31 is started (S105). This memory process
This is performed for one screen. That is, in the case of field recording, a luminance signal for one track (one field) is recorded, and in the case of frame recording, a luminance signal for two tracks (two fields) is recorded. In this embodiment, field recording is performed.

When the recording of the luminance signal for one field is completed, writing to the luminance signal memory 33 is prohibited, and the flag N
Is cleared, and the first initial value is set in the horizontal and vertical address counters (S107, S109, S110). Then, based on the line index signal, the A / D converter 4
3 is checked to see if the color signal is a color difference signal RY.
Writing to the signal memory 45 (S115). After writing the signal for one horizontal line, the vertical address counter is counted up by one and the process returns to S113 (S113, S115,
S119, S121).

Similarly, if the color difference signal is BY, the color difference signal BY for one line is written into the BY signal memory 47, and then the vertical address counter is counted up by one.
13 (S113, S117, S119, S12
1). In this embodiment, one horizontal line is a color difference signal RY or a color difference signal BY, and the color difference signals RY and BY are alternately reproduced for each horizontal line. By the above processing, the color difference signals RY and BY are written into the memories 45 and 47 in the manner shown in FIG.

When the writing for one field is completed, it is checked whether the flag N is "1". At the first time, the flag N is cleared in S109. Therefore, in order to write the second color difference signal, S
Go to 125. In S125, a second initial value is set in the horizontal and vertical address counters. Then, the color difference signals RY, B-
Y are sequentially written into the corresponding color signal memories 45 and 47 (S113 to S121). By the above writing process,
As shown in FIG. 4, the color difference signals RY and BY are sequentially written one by one.

The end of writing for one field is detected by the output of the vertical synchronizing signal V (S119). If this is the end of the second writing, since the flag N has been set in S127, the process proceeds from S123 to S129. Then, reading of the luminance signal memory 33 and the color signal memories 45 and 47 is enabled, and the sampling pulse fs' generator 6
3 sequentially reads out the luminance signal Y, the color difference signals RY, and BY in synchronization with the sampling pulse fs' output by
129). By this reading, the luminance signal Y, the color difference signals RY, and BY are synchronized as shown in FIG.

The luminance signals read from the luminance signal memory 33 and the color signal memories 45 and 47 are supplied to a D / A converter 35.
Is converted to an analog signal, a high-frequency component is removed by a low-pass filter 37, a synchronizing signal is added by a synchronizing signal mixing circuit 39, and is output to an encoder circuit 69 as a luminance signal Y + S. On the other hand, the color difference signals RY and BY are
The signals are converted into analog signals by the D / A converters 49 and 53, and high-frequency components are removed by the low-pass filters 51 and 55, and are output to the encoder circuit 69 as color difference signals RY and BY. The encoder circuit 69 outputs the luminance signal Y + S,
The color difference signals RY and BY are encoded and output to a monitor or the like as a composite video signal.

As described above, in this embodiment, the magnetic disk 1
The luminance signal Y is stored in the luminance signal memory 33 in the reproduction of the first rotation of 1.
And two color difference signals RY, B in the second rotation reproduction.
-Y is sequentially written to the corresponding color signal memories 45 and 47 every other row, and the two color difference signals R
-Y and BY are sequentially written in the skipped line.
When the writing is completed, these memories 33,
The signals of the same address are simultaneously read from 45 and 47,
Synchronization is being attempted.

Although the present invention has been described based on the embodiment applied to the still video apparatus, the present invention is not limited to this embodiment. In short, a plurality of types of signals alternately output with a time lag are sequentially written in a predetermined area of the memory means corresponding to the output order. Then, in each memory, a predetermined area where a signal is written and a predetermined area where a signal is not written are alternately generated. The same data as the signal written in the adjacent predetermined area is sequentially written into the predetermined area where no writing has been performed. By this processing, the same signal is temporally written to the same address.
Then, by simultaneously reading signals from the same address of these memory means, synchronization of signals shifted in time is achieved.

[0029]

As described above, according to the present invention, an image for one screen can be obtained.
For the luminance signal output for each horizontal line,
Two types of color difference signals output alternately for each horizontal line
The luminance signal output during one vertical scanning period.
The memory means is sequentially written for each horizontal line, and the other vertical
The above two types that are output alternately for each horizontal line during the scanning period
Each color difference signal to the corresponding memory means.
Write sequentially every flat line equivalent area, and another vertical
It is output alternately every horizontal line during the scanning period.
The two types of color difference signals are stored in the corresponding memory means.
Write sequentially to an area equivalent to one horizontal line, and
After completion, the luminance signal and the
And the above two types of color difference signals are read out simultaneously and synchronized.
Therefore, just by reading from each memory of the eyes, each horizontal line
The luminance signal and the two types of color signals can be synchronized for each color.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a still video device to which the present invention has been applied.

FIG. 2 is a timing chart showing an input state of a luminance signal and a color difference line sequential signal.

FIG. 3 is a diagram illustrating a manner in which a first-time color difference line sequential signal is written into a color difference signal memory;

FIG. 4 is a diagram illustrating a manner in which a second color difference line sequential signal is read out and written into a color difference signal memory;

FIG. 5 is a timing chart of a luminance signal and a color difference signal synchronized by the synchronization apparatus of the present embodiment.

FIG. 6 is a flowchart relating to memory processing during reproduction according to the embodiment.

FIG. 7 is a block diagram showing a conventional synchronization circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Magnetic disk 15 Spindle motor 27 Low-pass filter 33 Luminance signal Y memory 45 Color difference signal RY memory 47 Color difference signal BY memory 61 Memory controller

Claims (3)

(57) [Claims] 1. One horizontal line for one screen of video
The luminance signal output for each horizontal line and the luminance signal output alternately for each horizontal line
A synchronizing device for converting two types of color difference signals to be simultaneously converted into a video signal which is temporally simultaneous, wherein the luminance signal and the two types of color difference signals are each horizontally converted.
Each of the above signals, which has an area for storing one screen
Memory means corresponding to the signals, the luminance signal, and the respective memories of the two types of color difference signals.
Writing to the means is performed at different times, and
A single memory controller that simultaneously reads from a stage
A memory for storing a luminance signal output during one vertical scanning period ;
Means is sequentially written for each horizontal line, and output alternately for each horizontal line during another vertical scanning period.
Each of the above two types of color difference signals
Means is sequentially written every other horizontal line equivalent area, and further changed every horizontal line in another vertical scanning period.
The two types of color difference signals output from each other are
Write sequentially to the area corresponding to one unwritten horizontal line of the memory means
Inclusive, after which the writing has been completed, the bright from each of the memory means
Simultaneously read out the color signal and the above two types of color difference signals simultaneously
Video signal synchronizing device
Place. 2. A video signal synchronizing apparatus according to claim 1, wherein
The two types of color difference signals are color difference signals RY and B-
Y, the luminance signal and the color difference signal RY in the one vertical scanning period,
BY is one field for one track of the magnetic disk.
And each time the magnetic disk makes one revolution,
With the corresponding luminance signal for each horizontal line from the rack
The color difference signals RY and BY are alternately reproduced.
And the memory control means controls the color difference signal R-
When writing Y and BY sequentially to the corresponding memory means
Corresponds to a certain round of playback of the magnetic disk.
Writing the first initials address of the memory means
Starts playback, and responds to playback in the next lap.
Is the area equivalent to the first free horizontal line in the memory means
Video signal synchronizing device that starts writing. 3. A video signal synchronizing apparatus according to claim 2, wherein
In the above, each of the memory means is provided with the memory control.
Horizontal and vertical addresses controlled by means
Luminance signal and color difference signal for one horizontal line.
RY and BY are one vertical address of each of the memory means.
And the color difference signals RY and BY are
In writing during the one vertical scanning period, the vertical
Synchronization device for video signals written every other dress.