JP3329628B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a MOS type semiconductor device having an elevated source / drain structure.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been miniaturized as the degree of integration has increased, and on the other hand, there have been problems associated with the miniaturization of elements. For example, in a MOS transistor, when the gate length is reduced, a short channel effect such as a decrease in threshold voltage is a serious problem.

[0003] The short channel effect is mitigated by making the impurity diffusion layer sufficiently shallow. However, when the impurity diffusion layer is made thin, the resistance of the diffusion layer is increased and the parasitic resistance between the source and the drain is increased. For this reason, MOS
In a type transistor, reduction of this kind of parasitic resistance is desired.

Here, as a technique for obtaining a low electric resistance from the viewpoint of reducing the parasitic resistance, a method of forming silicide on source / drain regions has been used.

In general, in order to form silicide on source / drain regions, a method is used in which a metal is sputtered on a silicon substrate, heated, and the metal reacts with a semiconductor. According to this method, (1) the diffusion layer is consumed as much as reacts with the metal, (2) there is unevenness at the interface between the formed silicide and silicon, and (3) the reaction accompanying the reaction at the time of silicide formation. For reasons (1) to (3), such as the fact that defects are diffused into the inside of the substrate to deteriorate the bonding characteristics, a certain thickness of the diffusion layer is required.

However, when the thickness of the diffusion layer is increased, the conventional diffusion layer is formed only by ion implantation, so that the depth of the diffusion layer is increased, which is contradictory to miniaturization of the device. .

To solve this problem, a structure called elevated source / drain has been proposed.
In the elevated source / drain, after forming a source / drain using ion implantation, a single crystal silicon layer is selectively epitaxially grown on the source / drain to increase the height of the source / drain region. For this reason, silicide for lowering the resistance can be formed without increasing the depth of the diffusion layer.

FIGS. 7 and 8 are sectional views showing the steps of a method for manufacturing a MOS transistor to which the elevated source / drain structure is applied. As shown in FIG. 7A, an element isolation insulating film 2 is formed on the surface of an n-type silicon substrate 1 by a selective oxidation method. Next, the n-type silicon substrate 1
A gate oxide film 3 is formed thereon by thermal oxidation. On the gate oxide film 3, an impurity-doped polycrystalline silicon film 4 and a tungsten silicide film 5 are sequentially formed as a gate electrode. Thereafter, a silicon oxide film 6 is formed on the entire surface by the LP-CVD method, and these laminated films are etched by a reactive ion etching method to form a gate portion.

Next, as shown in FIG. 7B, a sidewall gate insulating film 7 made of a silicon nitride film is formed on the sidewall of the gate portion by using the CVD method and anisotropic dry etching.

Next, as shown in FIG. 7C, BF ₂ ⁺ ions are implanted using the gate portion as a mask, and thereafter boron is activated by heat treatment to form a diffusion layer 8 serving as a source / drain region. I do.

Next, as shown in FIG. 8D, a single crystal silicon layer 9 is formed on the surface of the silicon substrate 1 by selective epitaxial growth. BF ₂ ⁺ ions are implanted into the single-crystal silicon layer 9 in the same manner as the diffusion layer 8 and heat-treated.
Thereafter, a titanium thin film and a titanium nitride thin film are sequentially deposited on the entire surface by a sputtering method.

Next, as shown in FIG. 8E, the titanium thin film is reacted with the silicon substrate by heat treatment in a nitrogen atmosphere, and a titanium silicide film 10 is formed only on the source / drain regions. Thereafter, an unreacted titanium thin film on the titanium nitride film and the insulating film is selectively removed by, for example, an aqueous solution of hydrofluoric acid or a mixed solution of sulfuric acid and hydrogen peroxide.

Next, as shown in FIG.
A silicon oxide film 11 is deposited by the VD method, and a contact hole is opened in the silicon oxide film 11 by anisotropic dry etching. Thereafter, an aluminum film containing trace amounts of silicon and copper is formed, and the aluminum film is patterned to form the source / drain electrodes 12. Next, heat treatment is performed in a nitrogen atmosphere containing hydrogen to complete the process.

[0014]

However, in the above MOS type transistor having the elevated source / drain structure, when the silicon film is lifted, the single crystal silicon layer 9 is formed by selective epitaxial growth. As shown in d), a facet is formed at the end of the single crystal silicon layer 9. In this case, the thickness of the facet portion is effectively reduced, so that the junction characteristics are deteriorated.

When the silicon film formed by epitaxial growth is non-doped, the same type of impurity as that of the diffusion layer 8 is ion-implanted in order to reduce the resistance of the silicon film. However, since the thickness of the facet portion is small, the impurity is diffused deeply in the diffusion layer 8 below the facet portion, as shown in FIG. There is a problem of lowering.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and prevents a decrease in film thickness due to facets, effectively increases the thickness of a diffusion layer, and thereby improves the reliability of transistor characteristics. An object of the present invention is to provide a method for manufacturing a device.

[0017]

According to the present invention, there is provided a method for manufacturing a semiconductor device having a MOS structure on one main surface of a semiconductor substrate, wherein a gate portion, a source region, and a drain region are formed. Step and after the formation,
The activity generated by micro-discharge of the
Supplying a sex species onto one main surface of the semiconductor substrate;
After the serial supply, before Kiso over source region and the drain region
Only selectively depositing amorphous silicon, and monocrystallizing the deposited amorphous silicon.
And a method of manufacturing a semiconductor device.

Further, as the amorphous silicon,
It preferably contains a Group III or V element.

The halogen-based material gas is C
_{F 4, F 2, Cl 2} , SF 6, HF , or ClF ₃ Noise
Any of these halogen-based materials may be used.

[0020] Therefore, by took measures as invention or corresponding to claim 1, the gate portion, to form a source region, a drain region, after the formation, halogenated
Activated species generated by micro-discharge of material gas
Supplied onto the one main surface of the conductor substrate, after this supply, source over the amorphous silicon only source region and the drain region is selectively deposited, amorphous silicon is the deposit
The as they may turn into single crystals, and selectively depositing amorphous silicon only to the diffusion layer region, effectively increasing the thickness of preventing a reduction in thickness diffusion layer faceted, with,
The reliability of transistor characteristics can be improved.

According to a second aspect of the present invention, the amorphous silicon contains a group III or group V element. It can also be used with molds, and can exhibit excellent versatility.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a cross-sectional view showing the structure of a MOS transistor to which an elevated source / drain structure according to an embodiment of the present invention is applied. The same parts as those in FIG. The detailed description is omitted, and only different parts are described here.

That is, the MOS transistor according to the present embodiment is intended to prevent a decrease in the film thickness due to the facet, and more specifically, as shown in FIG. Instead, an amorphous silicon film is deposited flat, and a single crystal silicon film 21b is formed by heat treatment. Note that facets are not formed in the amorphous silicon film because it is amorphous.

Next, a method for manufacturing such a MOS transistor will be described with reference to FIGS.

Now, for example, as shown in FIG.
An element isolation insulating film 2 having a thickness of 0.6 μm is formed on a surface of an n-type silicon substrate 1 having a plane orientation (100) and a specific resistance of 4 to 6 Ωcm by a selective oxidation method. Next, a 10-nm-thick gate oxide film 3 is formed on the n-type silicon substrate 1 by thermal oxidation. On the gate oxide film 3, 100 n is formed as a gate electrode.
An m-thick impurity-doped polycrystalline silicon film 4 and a tungsten silicide film 5 are sequentially formed. After a while, LP on the whole surface
Forming a silicon oxide film 6 by a CVD method, and etching these stacked films by a reactive ion etching method to form a gate portion;

Next, as shown in FIG. 2B, a sidewall gate insulating film 7 made of a silicon nitride film having a thickness of about 100 nm is formed on the sidewall of the gate portion. The side wall gate insulating film 7 is obtained by, for example, depositing a silicon nitride film having a thickness of 50 nm on the entire surface by a CVD method and then etching the entire surface by anisotropic dry etching.

Next, as shown in FIG. 2C, BF ₂ ⁺ ions are implanted using the gate portion as a mask. B injected
F ₂ ⁺ ions are distributed around the peak depth depending on the acceleration energy inside the silicon substrate. Thereafter, for example, boron is activated by a heat treatment at 900 ° C. for 30 seconds to form a diffusion layer 8 serving as a source / drain region.

Next, the natural oxide film on the silicon surface is removed by such a diluted hydrofluoric acid solution, the substrate was placed in a vacuum reactor, for example, carbon tetrafluoride (CF ₄₎ by the micro-discharge gas, generated active The seed is provided on the substrate surface. Thus, a large amount of fluorine remains on the surface of the insulating film. After this,
The substrate is transferred to a silicon film forming step in a vacuum or a non-oxidizing atmosphere.

In the silicon film forming step, for example, 5
Disilane (Si ₂ H ₆ ) is flowed at 100 sccm at 00 ° C. This disilane is thermally decomposed only on the silicon surface, and FIG.
As shown in (d), the amorphous silicon film 21a is selectively deposited.

Here, BF ₂ ⁺ ions are implanted into the amorphous silicon film 21a in the same manner as in the diffusion layer 8, and heat treatment is performed at 600 ° C. for 2 hours. As a result, the amorphous silicon film 21b grows in a solid phase and becomes a single crystal silicon film 21b. Thereafter, a titanium thin film having a thickness of 25 nm and a titanium nitride thin film having a thickness of 50 nm are sequentially deposited on the entire surface by sputtering.

Next, as shown in FIG. 3E, the titanium thin film is reacted with the silicon substrate by a heat treatment at 700 ° C. for 1 minute in a nitrogen atmosphere to form a titanium silicide film 22 only on the source / drain regions. I do. Thereafter, an unreacted titanium thin film on the titanium nitride film and the insulating film is selectively removed by, for example, an aqueous solution of hydrofluoric acid or a mixed solution of sulfuric acid and hydrogen peroxide.

Next, as shown in FIG.
A silicon oxide film 11 is deposited by the VD method, and a contact hole is opened in the silicon oxide film 11 by anisotropic dry etching. Thereafter, an 800 nm-thick aluminum film containing, for example, 0.5% each of silicon and copper is formed, and the aluminum film is patterned to form a source film.
The drain electrode 12 is formed. Next, heat treatment is performed at 450 ° C. for 15 minutes in a nitrogen atmosphere containing 10% of hydrogen.
Thereby, the manufacturing process of the MOS transistor is completed.

Next, the characteristics of the MOS transistor manufactured as described above will be described. FIG. 4 is a diagram showing the relationship between the gate voltage and the drain current of a MOS transistor in comparison between the present embodiment and the prior art. As shown in the figure, in the related art, a high drain current flows even when no gate voltage is applied. On the other hand, in this embodiment, when the gate voltage is about 0.2 V or less, the drain current is below the measurement limit, and it can be seen that there is no leakage current.

This is because, in the case of the prior art, the end of the single crystal silicon layer 9 is effectively thinned by facets, and when titanium and silicon are reacted to form silicide, as shown in FIG. It is presumed that titanium diffuses from the substrate into the substrate to form a carrier generation / recombination center, which becomes a local leak path.

On the other hand, in the case of the present embodiment, a single-crystal silicon film 21b is obtained by solid-phase growing an amorphous silicon film to be deposited flat without facets.
As shown in FIG. 5, the titanium 22 does not enter the substrate 1, the interface between the source / drain layer 8 and the silicide can be separated from the junction interface, and the diffusion layer is formed with a shallow impurity distribution.

FIG. 6 is a graph showing the dependence of the threshold voltage on the gate length of a MOS transistor in this embodiment and the prior art. As shown in the figure, in the related art, as the gate length becomes shorter, the threshold voltage decreases, and the short channel effect occurs. On the other hand, in the present embodiment, even if the gate length is reduced, the threshold voltage is constant, and it can be seen that the short channel effect can be prevented.

As described above, according to this embodiment, the gate portion and the diffusion layer 8 composed of the source region and the drain region are formed, and the amorphous silicon film 21a is formed on the formed source region and the drain region, respectively. Since selective deposition is performed, amorphous silicon is selectively deposited only in the diffusion layer 8 region, and the single-crystal silicon film 21b is formed by solid phase growth of the amorphous silicon. As a result, the thickness of the diffusion layer can be effectively increased, so that the reliability of the transistor characteristics can be improved.

Further, since the amorphous silicon film 21a according to the present embodiment contains a group III element, it can be adapted to a p-channel MOS transistor.
Note that, although different from the present embodiment, the n-channel M
The present invention has excellent versatility because it can be applied to OS-type transistors.

In the above embodiment, the case where titanium was used as the metal for forming silicide was described. However, the present invention is not limited to this. For example, nickel, cobalt, platinum, vanadium, palladium, etc. other than titanium. Even if silicide is formed by using a metal, the present invention can be implemented in the same manner and the same effect can be obtained. At this time, since the amount of the silicon layer consumed by the silicide reaction varies depending on the type and thickness of the metal, the thickness of the silicon thin film to be lifted needs to be equal to or greater than the consumed layer thickness.

Further, in the above-described embodiment, the case where the resistance is reduced by ion implantation of BF ₂ ⁺ after depositing the amorphous silicon film by flowing disilane has been described. However, the present invention is not limited to this. In some cases, the present invention can be carried out in the same manner to obtain the same effect as a manufacturing process in which, for example, diborane (B ₂ H ₆ ) is simultaneously flown at ₂ sccm as a doping gas to deposit a boron-added amorphous silicon film. B to amorphous silicon film
The ion implantation of F ₂ ⁺ can be omitted. Note that this boron-added amorphous silicon film can be deposited at a lower temperature such as 300 ° C.
-It becomes a boron-added silicon layer having a low resistance of cm.

In the above embodiment, the case where the normal silicon substrate 1 is used has been described. However, the present invention is not limited to this, and the present invention may be applied to a configuration using an SOI substrate or a SIMOX substrate instead of the silicon substrate 1. In the same manner to obtain the same effect.

Further, in this embodiment, CF _{4 is used} as a pretreatment for depositing the amorphous silicon film 21.
Has been described a case that generated fluorine radicals by the micro discharge gas is not limited to this, for example, F ₂ Cl _2,
Even if other halogen-based materials such as SF ₆ , HF, and ClF ₃ are used, the present invention can be implemented in the same manner and the same effect can be obtained.

In the above embodiment, the case where disilane gas is used to deposit the amorphous silicon film 21 has been described. However, the present invention is not limited to this, and a decomposition reaction occurs at 700 ° C. or less to form a silicon layer. The type of gas is not limited as long as it is a suitable gas. For example, silane (SiH ₄ ), dichlorosilane (SiH ₂ Cl ₂ ), SiCl ₄ ,
SiF ₄ , SiH ₄ Cl ₄ , SiH ₂ F ₂ , SiH ₂ C
l ₄ , Si ₂ Cl ₆ , SiH ₄ F ₂ , SiH ₂ F ₄ , S
Even if an amorphous silicon film is deposited using any one of i ₂ F ₆ , the present invention can be implemented in the same manner and the same effect can be obtained. When an impurity-doped silicon layer is deposited from the viewpoint of omitting ion implantation, these gases may be mixed with boron trichloride (BCl ₃ ) or boron trifluoride (BF ₃ ) as a doping gas in addition to diborane. I just need. For an n-channel MOS transistor, phosphine (PH ₃ ) or arsine (AsH) is used.
₃ ) Alternatively, a halide containing phosphorus or arsenic may be mixed as a doping gas.

In addition, the present invention can be variously modified and implemented without departing from the gist thereof.

[0046]

As described above, according to the first aspect of the present invention, a gate portion, a source region, and a drain region are formed.
After this formation, a micro discharge of the halogen-based material gas is performed.
To supply the generated active species on one main surface of the semiconductor substrate
And, after this supply, the Seo over source region and a drain region
Selectively depositing only amorphous silicon, the deposition
The amorphous silicon was as they may turn into single crystals, and selectively depositing amorphous silicon only to the diffusion layer region,
It is possible to provide a method for manufacturing a semiconductor device capable of effectively reducing the thickness of a diffusion layer by preventing a decrease in film thickness due to facets, thereby improving the reliability of transistor characteristics.

According to the second aspect of the present invention, since the amorphous silicon contains a group III or group V element, in addition to the effect of the first aspect, it is possible to cope with both the p-channel type and the n-channel type. It is possible to provide a method of manufacturing a semiconductor device which can exhibit general versatility.

Further, according to the third aspect of the present invention, the halogenation
CF ₄ , F ₂ , Cl ₂ , S
Any halogen-based material of F ₆ , HF or ClF ₃
Since use can be provided a method of manufacturing a semiconductor device which can achieve the same effect as claim 1.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a MOS transistor to which an elevated source / drain structure according to an embodiment of the present invention is applied;

FIG. 2 is a sectional view showing a step of the method for manufacturing the MOS transistor in the embodiment.

FIG. 3 is a sectional view showing a step of the method for manufacturing the MOS transistor in the embodiment.

FIG. 4 is a comparative diagram showing a relationship between a gate voltage and a drain current in the embodiment.

FIG. 5 is a sectional view showing an impurity distribution in the embodiment.

FIG. 6 is a comparative diagram showing a gate length dependency of a threshold voltage in the embodiment;

FIG. 7 is a process cross-sectional view showing a method for manufacturing a MOS transistor to which a conventional elevated source / drain structure is applied;

FIG. 8 is a process sectional view showing a method for manufacturing a MOS transistor to which a conventional elevated source / drain structure is applied;

FIG. 9 is a cross-sectional view showing an impurity distribution in a conventional mode.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... n-type silicon substrate, 2 ... element isolation insulating film, 3 ... gate oxide film, 4 ... impurity doped polycrystalline silicon film, 5 ... tungsten silicide film, 6 ... silicon oxide film, 7 ... side wall gate insulating film, 8 ... Diffusion layer, 11 ... silicon oxide film,
12: source / drain electrodes, 21a: amorphous silicon film, 21b: single crystal silicon film, 22: titanium silicide film.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 29/78 H01L 21/336 H01L 21/20 H01L 21/28

Claims (3)

(57) [Claims] 1. A method of manufacturing a semiconductor device having a MOS structure on one main surface of a semiconductor substrate, comprising the steps of: forming a gate portion, a source region, and a drain region; By
Supplying the generated active species onto one main surface of the semiconductor substrate.
A step of feeding, after the supply, the step of selectively depositing amorphous silicon only before Kiso over source region and said drain region, engineering of single crystallization of amorphous silicon obtained by the deposition
The method of manufacturing a semiconductor device characterized by and a degree. 2. The method according to claim 1, wherein the amorphous silicon contains a group III or group V element. 3. The method according to claim 2, wherein the halogen-based material gas is CF ₄ , F
_{2, Cl 2, SF 6,} HF , or any of Ha ClF ₃
2. The method for manufacturing a semiconductor device according to claim 1, wherein a logene-based material is used .