JPH077793B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device using a silicon selective epitaxial method.

<Problems of Prior Art> In recent years, as a method of separating active elements in a semiconductor device, a fine element isolation technique has been required in place of the selective oxidation method. As a method of forming a fine and deep device isolation region, for example, in a paper published under the title of “Device Isolation by Selective Epitaxial Growth” on pages 39 to 45 of Technical Report of the Institute of Electronics and Communication Engineers, SSD83-52, silicon (10
0) As shown in FIGS. 1 (a) and 1 (b), a silicon oxide film pattern 2 to be an element isolation region is formed in advance on both substrates 1 so as to be parallel to the (110) plane orientation, and then its insulation is performed. It is shown that silicon is epitaxially grown only on the exposed silicon substrate region without being deposited on the film to form a substrate as shown in FIGS. 2 (a) and 2 (b). To form the MOS transistor using the substrate shown in FIG. 2 SiO ₂ of the epitaxial growth layer 3
The facet 4 is formed in contact with the pattern 2 and becomes an obstacle when forming the gate electrode. In order to eliminate the facets, a polycrystalline silicon thin film 5 is formed on the side wall of SiO ₂ as shown in FIG. 3 and then epitaxially grown to form a flat substrate as shown in FIG. When a MOS transistor is formed using the substrate shown in FIG. 4, single crystallization in the silicon region at the interface with SiO ₂ is not sufficiently performed, which may cause a leak current at the pn junction and a decrease in withstand voltage. There is a drawback that the production yield is reduced.

<Objects of the Invention> The present invention provides a method for forming a substrate having a flat portion without forming a polycrystalline silicon film on the sidewall of an insulating film by eliminating the above-mentioned conventional defects. .

<Structure of the Invention> According to the present invention, an insulating film is formed on a substrate provided with a silicon single crystal layer having a (100) plane orientation, and then an opening is provided in a desired portion of the insulating film, and then the opening is formed. In a method for manufacturing a semiconductor device, in which a single crystal silicon film is selectively epitaxially grown only in a portion and a semiconductor device is formed in the epitaxial growth layer, the side surface of the insulating film opening is perpendicular to the substrate, and the side surface is (100) The present invention provides a method for manufacturing a semiconductor device, which is characterized in that a gate electrode is formed in a portion parallel to the surface and where the insulating film and the epitaxial growth layer are flat.

(Detailed Description of Configuration) The present invention has solved the problems of the prior art by adopting the above configuration. By making the variation of the insulating film pattern parallel to the (100) plane, there is a portion where the epitaxial growth layer and the insulating film pattern are flat even without the polycrystalline silicon film. A fine gate electrode can be formed by forming the gate electrode on the flat portion. Further, since the polycrystalline silicon film does not exist, the epitaxial growth layer is single crystal silicon. Therefore, the leak current at the pn junction was reduced.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. 5 (a) and 5 (b) are views showing an embodiment of the present invention. Wet oxidation of a thermal oxide film on a p-type single crystal silicon substrate (specific resistance 15 Ω · cm) with plane orientation (100) of 2 μm
Thickness, and then a normal photo-etching technique and reactive ion etching method are used to form a SiO ₂ insulating film pattern with a vertical cross section so as to be parallel to the (100) plane, and then SiH ₂ C
About 1 Vol% HCl was added to a gas system composed of l ₂ and H _2, and silicon was selectively epitaxially grown to a thickness of 2 μm only on the surface of the silicon substrate in the temperature range of 900 ° C. to 1100 ° C. In this case, the facets 14 are formed parallel to the (111) plane, but there is a flat portion at the center of the interface with SiO ₂ parallel to the (100) plane. Then, in O ₂ at 950 ° C, thickness 2
A gate oxide film 15 of 00 Å is formed, and boron is double-implanted by ion implantation at an acceleration energy of 30 KeV at 1 × 10 ¹² cm ⁻² and at an acceleration energy of 100 KeV at 2 × 10 ¹² cm ⁻² . Next, after depositing a polysilicon film with a thickness of 5000 Å by low pressure CVD method, a gate electrode is formed on a flat part by photo-etching method and dry etching method, and then arsenic is self-aligned at an acceleration energy of 100 KeV at 5 × 10 ¹⁵ cm. ^-2 ion implantation,
When the polysilicon gate electrode is doped with phosphorus by the diffusion method, the sectional structure of FIG. 6 (a) is obtained. Next, a contact hole is formed by depositing a SiO ₂ film 18 with a thickness of 5000 Å by the low pressure CVD method. Then, an Al film having a thickness of 1 μm is deposited by an electron beam evaporation method, and an Al wiring 19 is formed by a usual lingraphy method. Next, a passivation film is formed and contacts are opened to obtain an n-channel MOSFET having a sectional structure as shown in FIG. 6 (b).

(Effect of the Invention) FIG. 7 shows the current characteristics in reverse bias of the diode manufactured by the present invention and the conventional method.

According to the present invention, the manufacturing process of the MISFET can be generally simplified, and it is effective in reducing the junction leak current.

[Brief description of drawings]

FIGS. 1A and 1B are a front view and a cross-sectional view showing the shape of the element isolation region, respectively. FIG. 2 is a front view (a) and a sectional view (b) showing a shape after selective epitaxial growth for the structure of FIG. FIG. 3 is a sectional view of a substrate having a polysilicon thin film formed on the side wall of SiO ₂ . FIG. 4 is a sectional view after selective epitaxial growth of silicon on the substrate having the structure of FIG. FIG. 5 is a front view (a) and a sectional view (b) showing the structure of the substrate in the embodiment of the present invention. 6 (a) and 6 (b) are MOSFETs in the embodiment of the present invention.
FIG. 6 is a cross-sectional view showing the method of manufacturing. FIG. 7 is a diagram showing the relationship between the reverse bias voltage and the junction current of the diode obtained by the conventional method and the present invention. In the figure, 1,11… (100) Si single crystal substrate, 2,12… insulating film pattern,
3,13 ... Epitaxial silicon layer, 4,14 ... Facet,
5 ... Polycrystalline silicon thin film, 15 ... Gate oxide film, 16 ... Gate electrode, 17 ... High-concentration ion-implanted n + layer, 18, 20 ... C
VDSiO ₂ film, 19 ... Wiring aluminum film, a ... Voltage-current characteristics according to the present invention, b ... Voltage-current characteristics by conventional method.

Claims (1)

[Claims] 1. An insulating film is formed on a substrate provided with a silicon single crystal layer having a (100) plane orientation, an opening is provided at a desired portion of the insulating film, and then only the opening is selectively formed. In a method of manufacturing a semiconductor device in which a single crystal silicon film is epitaxially grown and a semiconductor device is formed in the epitaxial growth layer, a side surface of an insulating film opening is perpendicular to a substrate and the side surface is parallel to a (100) plane, A method of manufacturing a semiconductor device, comprising forming a gate electrode on a portion where an insulating film and an epitaxial growth layer are flat.