JP3332220B2 - Digital signal reproducing apparatus and reproducing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal reproducing apparatus and a reproducing method for reproducing a signal which has been compressed and coded by using a variable length coding method. Is obtained.

[0002]

2. Description of the Related Art As a standard for consumer digital video devices, a standard called DV has been proposed and put into practical use. In the digital signal recording / reproducing apparatus according to the DV standard, as described in "Illustrated Digital Video Readers" P41 to P60 (edited by Yukio Kubota, Ohmsha, 1995), a digital information signal is utilized by utilizing the correlation of pixel data in a frame. , And a digital information signal is recorded at a recording rate of 25 Mbps.

[0003] In a digital signal recording / reproducing apparatus based on the DV standard, one frame of image information is first divided into blocks each consisting of 8 pixels in the horizontal direction and 8 pixels in the vertical direction, and DCT (discrete cosine transform) is performed. The image information is subjected to quantization and variable-length coding, and is recorded on a magnetic tape. When reproducing a signal recorded on a magnetic tape, image information is restored by performing DCT, quantization, variable-length decoding corresponding to variable-length encoding, inverse quantization, and inverse DCT at the time of recording. are doing.

In the above apparatus, a recording signal is recorded on a magnetic tape after a predetermined error correction code is added at the time of recording, and at the time of reproduction, an error correction process is performed using the error correction code to restore a reproduction signal. are doing.

[0005]

However, in the digital signal recording / reproducing apparatus for performing the above-mentioned compression encoding,
If there is abnormal data during reproduction, the reproduced data may be broken. In particular, if the data subjected to DCT is subjected to variable-length coding and there is abnormal data when decoding the data, the reproduced signal subjected to inverse DCT often becomes an unnatural image with a checkerboard pattern. That is, if an error occurs due to such abnormal data, the error data becomes more noticeable on the screen.

[0006] Such an error during data reproduction is normally output after error data has been corrected by error correction processing, so that no error occurs.
The quality of the playback signal is particularly high when a head-related trouble occurs, when the tape is repeatedly played, when the playback signal is lost due to damage to the tape, or when the device that recorded the data is different from the device that plays the data. Is deteriorated, data that cannot be completely corrected by the error correction processing is reproduced, so that such a problem may occur.

[0007] When decoding a compressed signal input from the outside via a digital interface, or
When decoding a signal that has been repeatedly dubbed or transmitted, correct reproduction data cannot be obtained due to the line quality of the digital interface, signal deterioration due to dubbing or transmission, and the same problem may occur. Further, when dubbing and transmission are repeated, data reproduced unnaturally like a checkered pattern may be recorded as normal data on the recording side.

[0008] An object of the present invention is to avoid such a failure of reproduced data. When abnormal data is detected during signal reproduction, only normal data is output to output the reproduced data. Is to try to avoid.

[0009]

In order to solve the above-mentioned problems, a digital signal reproducing apparatus according to the present invention performs orthogonal transformation processing and variable conversion into rectangular blocks obtained by dividing one screen in a horizontal direction and a vertical direction. A storage area of a predetermined amount provided for each rectangular block, which is subjected to a long encoding process, and is further provided with data obtained by compressing and encoding a plurality of rectangular blocks into one compressed block so that the code amount in the compressed block becomes a predetermined value or less. And digital data in which data which is not completely stored and which is stored as second data in a storage area for storing another rectangular block of the compressed block is decoded, and a digital signal reproducing apparatus for restoring data, the de
If there is an error while decoding the digital data,
An abnormality is found in any of the first and second data.
Identification means for identifying the presence of
And a use restriction means for restricting the use of the barrel data, before
In accordance with the identification result of the identification means,
It is characterized in that the condition of the use restriction is changed .

A digital signal reproducing method according to the present invention performs an orthogonal transformation process and a variable length encoding process on a rectangular block obtained by dividing one screen in a horizontal direction and a vertical direction. The data obtained by compression-encoding the blocks as one compression block so that the code amount in the compression block is equal to or less than a predetermined value is sequentially stored as first data in a predetermined amount of storage area provided for each rectangular block, and is stored. the overflow data without decodes the digital data stored as the second data storage area for storing the other of the rectangular block of the compressed block, a digital signal reproduction method for restoring the image data, the digital An error occurred during data decryption
The first data and the second data.
Identify any abnormal data and terminate decoding.
Limits the use of digital data obtained
The use of digital data after the decoding
It is characterized in that the limit conditions are changed .

[0011] The digital data is decoded.
If there is abnormal when, are those wherein the replaced without the use of all or a portion of the second data in the compression block the had abnormality in 0 code, also, before
When there is an error in decoding digital data
Further, the data of the compressed block having the abnormality is replaced with the data of the compressed block at the same screen position which has already been decoded.

A digital signal reproducing apparatus according to the present invention
The position and playback method is to divide one screen horizontally and vertically.
Orthogonal transformation processing and variable-length code for rectangular blocks obtained by dividing
And a plurality of rectangular blocks are compressed
The amount of code in the compressed block is
Compression-encoded data that is less than the
The first data is stored in a predetermined amount of storage area provided for each
And store them sequentially, and overflow data that cannot be stored.
To store another rectangular block of the compressed block
Digital data stored as the second data in the storage area of
Digital signal to decode data and restore image data
Signal reproducing apparatus and reproducing method, wherein the digital data
Is the one obtained by performing the orthogonal transformation
DC coefficients and a predetermined number of AC coefficients are assigned to each rectangular block.
Has to, abnormality detection during decoding of the digital data
If issued, the existence of abnormal data where the abnormality was detected
The use of the second data in the compressed block to be performed is restricted, and when a larger number of AC coefficients than the predetermined number of AC coefficients are obtained, the variable that constitutes the AC coefficient obtained beyond the predetermined number of AC coefficients is restricted. It is characterized in that all data related to long codes is regarded as abnormal data.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram for explaining a main configuration of a digital signal reproducing apparatus.
FIG. 1A is a block diagram showing a main configuration of a digital signal recording device conforming to the DV standard, and FIG. 1B is a block diagram showing a main configuration of a digital signal reproducing device for reproducing a signal from a magnetic tape recorded in this way. is there.

Here, the processing of the signal recording system in the DV standard digital signal recording apparatus will be described first. In FIG. 1A, when one frame of image data is stored in the frame memory 1 (FM), a DCT block consisting of 8 pixels in the horizontal direction × 8 pixels in the vertical direction is sequentially output from the frame memory 1 (FM). (DCT).

The DCT circuit 2 performs DCT (Discrete Cosine Transform) on the image data output from the frame memory 1 in units of DCT blocks, and as shown in FIG.
And three AC coefficients. The 63 AC coefficients are rearranged in order from the lowest frequency component to the highest frequency component (zigzag scan) as indicated by the arrow in FIG. Is quantized.

The quantized image data is then input to a run-length encoding circuit 4 (RLC), and the 63 AC coefficients whose values have been reduced by quantization are, as shown in FIG. Are sequentially encoded into a run-length code consisting of a set of a zero run value (r), which is the number of zeros, and a value (n), which is a value other than zero. In other words, the number of consecutive 0s is counted in the quantized AC coefficient, and the count value of the 0 and the value of the AC coefficient other than 0 following the 0 are encoded as a set. As shown in the figure, when the 63rd AC coefficient is 0 in the high-frequency portion of the quantized AC coefficient, all of the last consecutive 0 values are collectively EOB.
(End of Block). In this way, the quantized image data is sequentially encoded, and when there is no longer a value other than 0, the encoding is terminated with the EOB code.

[0017] Then, the image data comprising run length code, in the variable-length coding circuit 5 (VLC), based on a predetermined variable length coding table, variable length as V ₁ to V ₆ shown in FIG. 3 Converted to sign.

In the above-described compression coding, one frame has 525 horizontal scanning lines and a field frequency of 60.
As shown in FIG. 4, in the case of a television signal of the NTSC system or the like, four DCT blocks (DCT0 to DCT3) of four luminance signals adjacent to each other in the horizontal direction on the screen, and these DCT blocks have the same position on the screen. The macroblocks formed by one DCT block (DCT4) of one color difference signal CR and one DCT block (DCT5) of one color difference signal CB are formed from five different positions on the screen called shuffling according to a predetermined rule. The collected five macroblocks are regarded as one video segment, and the quantized code amount of this video segment after variable-length encoding is set as close as possible to the code amount allocated to the video segment so as not to exceed the allocated code amount. The conversion table is set.

The image data converted into the variable length code is further input to the packing circuit 6, where the data of each variable length coded DCT block is divided into a plurality of groups having different frequency components and stored. I do. As described above, the code amount of one video segment composed of five macroblocks is compression-encoded so as to be substantially constant, and the data of the five macroblocks is output as five sync blocks. Become.

The unit corresponding to the data area of each sync block is divided into six regions, which are the number of DCT blocks constituting one macro block. In each of the six regions, the data of each DCT block has its frequency component. Are stored in priority from the lowest one.

If the code amount of the variable-length-encoded DCT block exceeds the data storage amount of the divided area in the sync block, the data of all DCT blocks is stored in one area. Data that cannot be stored but overflows without being stored is preferentially stored in another area in the same sync block from the one with the lowest frequency component. Also, data that cannot be stored in another area in the same sync block and is overflown is stored in an area in another sync block forming the same video segment.

[0022] Then, the relatively low-frequency data directly stored in the divided area in the sync block is treated as the first data belonging to the first group and stored in the divided area in the sync block. Data that cannot be stored and is higher in frequency than the first data stored in another area in the same sync block is treated as second data belonging to the second group, and is stored in another area in the same sync block. The highest-frequency data that cannot be stored and is stored in an area in another sync block that forms the same video segment is treated as third data belonging to a third group.

FIG. 5 shows an example in which data of one video segment is stored in five sync blocks (SBs). The six DCT blocks (DCT0 to DTC) shown in FIG.
The data of CT5) includes six divided areas (1- 1) obtained by dividing a unit corresponding to the data area of the sync block.
1 to 1-6) are preferentially stored in ascending order of frequency components.

Here, the DCT block of the luminance signal Y0 (DCT block)
If the code amount of T0) is less than the data storage amount of the divided area, all of the divided areas 1-1 as the first data
Is stored in Assuming that the code amount of the DCT block (DCT1) of the luminance signal Y1 exceeds the data storage amount of the divided area, the data having the lower frequency component is preferentially set as the first data in the divided area 1-2. The data which is not completely stored and overflows is stored as the second data in the divided area 1-1, for example. Data to be stored in other sync blocks (SB2 to SB5, etc.), but data that cannot be completely stored and is stored in the divided area 1-6 is treated as third data.

In the packing process, information of DC coefficients of the DCT block, information of a quantization table when quantization is performed, and other related information are also stored in a predetermined area in each sync block. Are output as these data.

The packing data having been subjected to such packing processing is subjected to an error correction code or other necessary data in the recording processing unit 7 after the data array is rearranged by the deshuffling processing corresponding to the above shuffling to restore the original data arrangement. Information is added, and further modulated and recorded on a recording medium. Further, at this time, the data may be output via a digital interface or the like after adding an error correction code or other necessary information without recording on the recording medium.

Next, a signal reproducing system process in the digital signal reproducing apparatus will be described with reference to FIG. In the figure, reference numeral 8 denotes a reproduction processing section for demodulating reproduction data reproduced from a recording medium and performing error correction processing to obtain packing data at the time of recording. Note that data input through the digital interface can also be subjected to error correction processing to obtain packing data at the time of recording. Then, the packing data from the reproduction processing unit 8 is input to the unpacking circuit 9 in video segment units at the time of recording.

Then, inside the unpacking circuit 9, the first to third data at the time of recording are each divided and restored to the original data stream of the variable length code for each DCT block. The data string of the variable length code is supplied to the variable length decoding circuit 10 (VL
In D), the run-length decoding circuit 11 (RLD) restores a run-length code consisting of a set of consecutive 0's and non-zero values with reference to the variable-length coding table.
Then, the data is restored to the original data string by inserting 0s at necessary places.

The data sequence restored by the run-length decoding circuit 11 is inversely quantized by the inverse quantization circuit 12 based on the quantization table information extracted separately from the packing data.
The AC coefficient of each DCT block at the time of recording is restored. The restored AC coefficient is returned to two-dimensional data by inverse zigzag scan, and the inverse DCT circuit 13 restores image data for one DCT block consisting of 8 pixels in the horizontal direction × 8 pixels in the vertical direction at the time of recording.

Image data from the inverse DCT circuit 13 is sequentially stored in the frame memory 14 (FM) for each DCT block, and is output as image signal data when the restoration of image data for one screen is completed.

Next, a digital signal reproducing apparatus and a reproducing method according to the present invention will be described with reference to FIG. In addition,
Here, a first embodiment of the digital signal reproducing apparatus according to the present invention will be described with reference to FIG.

As shown in FIG. 1, the unpacking circuit 9 shown in FIG. 1B includes a code data cutout unit 9a, a code length table 9b, a grouping memory unit 9c, and a write control unit 9.
d, a first memory 9e, a second memory 9f, a read control unit 9g, a reproduction data restriction unit 9h, a DCT / VLC counter 9i, and a switching unit 9j, and packing data in video segment units from the reproduction processing unit 8. Is first input to the code data cutout unit 9a.

The code data cutout unit 9a has a memory for one video segment therein, stores the data for one video segment, and then refers to the code length table 9b to record the first to third data at the time of recording. To cut out.
For example, when packing data for one video segment as shown in FIG. 5 is input from the reproduction processing unit 8, the code data cutout unit 9a temporarily stores these data therein, and first, the respective sync blocks (SB1 to SB5). ) Is cut out and output to the grouping memory unit 9c.

That is, the code data cutout unit 9a firstly refers to the code length table 9b to obtain first data in the divided area 1-1, first data in the divided area 1-2,
The first data in the divided area 5-6 are cut out in the order of the first data in the divided area 1-3.

Then, all the second data is cut out in the order of the second data in the divided area 1-1, the second data in the divided area 1-3, and the second data in the divided area 1-5. Finally, all the third data stored in the divided area 1-6 and the other divided areas are cut out.

Here, the first data consisting of the variable length code cut out by the code data cutout unit 9a is the first memory area in the grouping memory unit 9c, the second data is the second memory area, and the third data is The code data cutout unit 9a outputs grouping information so that the data is written in the third memory area, and the write control unit 9d performs write control based on the grouping information.

As described above, the packing data for one video segment from the reproduction processing unit 8 is the first to third data, respectively.
And the extracted first to third data are written in the first to third memory areas in the grouping memory unit 9c, respectively, and are divided into one video segment output from the code data extraction unit 9a. Is also output to the first memory 9e and written therein.

If the variable length code from the reproduction processing unit 8 is an undefined code or the code is truncated in the middle, the code data cutout unit 9a generates an error as described above. Variable-length code number (VLC No.) indicating the order of the variable-length code from the beginning in the DCT block, and D in which an error has occurred.
The DCT block number (DCT No.) indicating the number of the DCT block from the beginning of the video block in the video segment is output to the second memory 9f. The variable length code number (VLC No.) has 1 as an initial value as shown in FIG.
CT No. ) Has 0 as an initial value as shown in FIG.

When the packing data for one video segment is written in the grouping memory 9c, the data is read out next.
The variable length codes constituting each DCT block are read based on the grouping information for one video segment stored in the memory 9e.

Here, FIG. 7 shows an example of grouping information for one video segment stored in the first memory 9e. For DCT block number 0, only the first data exists. The variable length code number (VLC No.) of the first data is shown to be 1 to 8. Also, DCT block number 1 has first data and second data, the first data has a variable length code number (VLC No.) of 1 to 10, and the second data has a variable length code number (VLC No.). VLC No.) are shown to be 11 and 12. The DCT block number 29 includes first data to third data, and the variable length code number (VLC No.) of the first data.
Indicates that the variable length code number (VLC No.) of the second data is 12, and that the variable length code number (VLC No.) of the third data is 13 and 14.

The reading control unit 9g includes a DCT / VLC counter 9
i, an appropriate read address is set in the order of the DCT block number (DCT No.) and the variable-length code number (VLC No.) while referring to the grouping information written in the first memory 9e. Each variable length code is sequentially read.

Here, the DCT block number (DCT No.) and the variable length code number (VLC No.) output from the DCT / VLC counter 9i are output to the read control unit 9g and simultaneously to the reproduction data restriction unit 9h. The reproduced data restriction unit 9h checks whether the variable length code number and the DCT block number are written in the second memory 9f, and when the variable length code number and the DCT block number are not written, The reproduction data limiting unit 9h is provided with a switch 9
j is switched to the terminal A side, and the data of one video segment read out from the grouping
All are output from the switch 9j for each block.

However, when the variable length code number and the DCT block number are written in the second memory 9f,
The reproduction data restriction unit 9h switches the switch 9j to the terminal B side as necessary, and a part of the data for one video segment read from the grouping memory unit 9c is E.
Is replaced by the variable-length codes are output as V ₆ shown in FIG. 3 showing the OB code.

When the variable-length code number and the DCT block number are written in the second memory 9f, the reproduction data restricting unit 9h refers to the grouping information in the first memory 9e to make an error. It is determined which one of the first data to the third data is the variable length code in which is generated.

[0045] Then, the reproduction data restricting unit 9h performs a variable length code indicating an EOB code according to which of the first data to the third data the variable length code in which an error has occurred. To change the data to be replaced. FIG.
Indicates that the variable length code in which the error has occurred is the first data,
In each of the second data and the third data, the data is replaced with a variable length code indicating an EOB code.

First, a case will be described in which it is determined that the variable-length code in which an error has occurred is the first data. At this time, the reproduction data limiting unit 9h outputs, from the switch 9j, the variable length code in which the error has occurred and the subsequent variable length code with respect to the DCT block having the variable length code in which the error has occurred. So as not to be
The switch 9j is switched to replace these variable length codes with variable length codes indicating EOB codes.

Then, all other DCT blocks in the macroblock in which the error-occurring variable length code exists,
That is, for example, the DCT of DCT block number 8 shown in FIG.
When an error has occurred in the variable length code in the block, the variable length codes forming the second data and the third data are changed with respect to the five DCT blocks of DCT block numbers 6 and 7, and 9 to 11. The switch 9j is switched to replace these variable-length codes with variable-length codes indicating the EOB code so that the output is not output from the switch 9j.

[0048] Also, all the Ds in the macroblock other than the macroblock in which the variable length code in which the error has occurred are present.
If an error has occurred in the variable length code in the CT block, for example, the DCT block of DCT block number 8, 24 of DCT block numbers 0 to 5, 12 to 29
For the DCT blocks, the switch 9j is switched to replace these variable-length codes with variable-length codes indicating EOB codes so that the variable-length codes constituting the third data are not output from the switch 9j.

Next, the variable length code in which the error has occurred is
To explain the case of the data, the reproduced data restricting unit 9h outputs all the DCT blocks in the macroblock in which the variable length code in which the error has occurred, that is, the variable data in the DCT block of DCT block number 8, for example. If an error has occurred in the long code, the second DCT block of DCT block numbers 6 to 11 is
And the variable-length code forming the third data
The variable length code is replaced by a variable length code indicating an EOB code by switching the switch 9j so as not to be output from j.

[0050] Also, all the Ds in the macroblock other than the macroblock in which the variable length code in which the error has occurred are present.
If an error has occurred in the variable length code in the CT block, for example, the DCT block of DCT block number 8, 24 of DCT block numbers 0 to 5, 12 to 29
For the DCT blocks, the switch 9j is switched to replace these variable-length codes with variable-length codes indicating EOB codes so that the variable-length codes constituting the third data are not output from the switch 9j.

The case where the variable-length code in which an error has occurred is the third data will be described. , That is, 30 DCT blocks of DCT block numbers 0 to 29, the switching unit 9j is switched by switching the switching unit 9j so that the variable length code constituting the third data is not output from the switching unit 9j. The variable length code is replaced with a variable length code indicating an EOB code.

Note that these switching operations of the switch 9j are performed by EO
The DCT block number (DCT No.) and variable length code number (VLCN) to be replaced with the variable length code indicating the B code
o. ) Is indicated by the DCT / VLC counter 9i, the reproduction data limiting unit 9h outputs a switching signal to the switch 9j, thereby replacing the data.

The variable length code output from the switch 9j in this manner is converted into a variable length decoding circuit 10
(VLD) and subjected to variable length decoding processing.
Run-length decoding processing is performed in the run-length decoding circuit 11 (RLD).

In the above embodiment, it is determined which of the first to third data the variable length code in which the error has occurred is, and EOB is determined according to the determination result.
The data to be replaced with the variable length code indicating the code is changed. For example, regardless of which of the first to third data the variable length code in which the error occurs is the variable length in which the error occurs. Regarding all DCT blocks in the video segment where the code exists, the second data and the third data may be controlled to be replaced with the variable length code indicating the EOB code.

For the DCT block having a variable length code in which an error has occurred, the variable length code in which the error has occurred and the subsequent variable length codes are replaced with a variable length code indicating an EOB code. For DCT blocks other than the DCT block in which the variable length code in which the error has occurred, control may be performed so that the second data and the third data are replaced with the variable length code indicating the EOB code. In addition, for all DCT blocks in the video segment in which the error occurred variable-length code exists, control may be performed so that only a predetermined number of AC coefficients or variable-length codes are output.

The variable length code in which the error has occurred is the first
In the case where data to be replaced with a variable-length code indicating an EOB code is determined regardless of which of the data to the third data, the control in the reproduction data restriction unit 9h can be simplified. .

Also, the DCT block in the macro block in which the error occurred variable-length code exists, the DCT block in the macro block reproduced before this macro block, and the DCT block in the macro block reproduced after this Different control may be performed on each DCT block.

As described above, in the digital signal reproducing apparatus and the reproducing method according to the present invention, when an error has occurred in the variable length code, the error occurrence location in the DCT block where the error has occurred and Error data is reproduced by replacing not only the variable-length code of the above but also the data of other DCT blocks in the same video segment that may be affected by these errors with a code indicating the EOB code. This prevents the possibility that reproduced data will fail.

However, in the above-described embodiment, there may be a case where an error is detected in the variable-length code, and even if an error occurs, the error is accidentally associated with some code and decoded, and the error cannot be detected. In this case, since the correct boundary of the variable-length code is not known, meaningless random data is decoded, decoding in this DCT block is continued in an abnormal state, and the number of data of AC coefficients after decoding is originally smaller. It is possible to exceed 63 which should be.

The digital signal reproducing apparatus according to the second embodiment is designed to deal with such a problem, and its configuration is shown in FIG. As shown in the figure, in the second embodiment, the variable length decoding circuit 10 includes a decoding unit 10a and a decoding table 10b, and the variable length code string from the unpacking circuit 9 is input to the decoding unit 10a. You. Then, the decoding unit 10a performs the variable length decoding process with reference to the decoding table 10b corresponding to the variable length encoding table at the time of recording. Then, the decoding unit 10a separately outputs the zero run value (r) and the value (n) of the run length code as shown in FIG.

The run length decoding circuit 11 comprises a down counter 11a, a holding circuit 11b, an OR circuit 11c, and a switch 11d. The zero run value (r) from the variable length decoding circuit 10 is output from the down counter 11a, (N) is input to the holding circuit 11b.

Then, the logical sum of the output of the down counter 11a and the error detection signal from the error control unit 14, which will be described later, is output from the logical sum circuit 11c, and the switch 11d is switched based on the output signal and held. Either the value (n) of the variable length code or the 0 code held in the circuit 11b is selectively output.

FIG. 10 shows the count value of the down counter 11a in the run-length decoding circuit 11 when the variable length code from the unpacking circuit 9 has no error and the error control unit 14 does not output an error detection signal. It shows the output of each configuration. For example, for a variable length code V ₁ as shown in FIG. 3, a zero run value 0 is output to the down counter 11 a and a value n ₁ is stored in the holding circuit 11.
b. Further, with respect to the variable length code V _2, zero run value 3 is outputted to the down counter 11a, value n ₂ is outputted to the holding circuit 11b.

The down counter 11a counts down the inputted zero run value (r) at every predetermined clock, and outputs a signal of H when the value is other than 0 and a signal of L when the value is 0. Also,
The holding circuit 11b holds the input value (n) until the next value is rewritten.

At this time, since the error control unit 15 does not output the error detection signal, it always outputs an L signal, and the output of the OR circuit 11c becomes the same as the output signal of the down counter 11a. Then, the switch 11d is the OR circuit 1
While the output signal of 1c is H, the 0 code is selected and output,
During the period of L, run-length decoding is performed by selectively outputting the value (n) held in the holding circuit 11b.

Similarly, run-length decoding is performed on the variable-length codes V _{3 to} V ₅ as shown in the figure, and when a variable-length code V ₆ indicating EOB is input, the switch 11e performs run-length decoding. The output of the 0 code is continued until the last part of the DCT block being performed, and the run-length decoding process for one DCT block is completed.

Next, the error control unit 15 will be described. The error control unit 15 includes an accumulation counter ER1 and an error signal generation unit ER2.
The zero run value (r) from the decoding unit 10a and information indicating 1 as the counter value are input, and the accumulation counter ER1 accumulatively adds a value obtained by adding 1 to the zero run value (r) input from the decoding unit 10a.

Here, the value obtained by adding 1 to the zero run value (r) is
It indicates the number of codes to be run-length decoded by the run-length decoding circuit 11, that is, the number of AC coefficients. By cumulatively adding this number, the number of AC coefficients decoded in the DCT block is known. Can be.

When the value output from the accumulation counter ER1 exceeds 63, the error signal generation unit ER2 regards that an error has occurred and outputs an H signal, that is, an error detection signal to the OR circuit 11c. Output. Therefore, even when an abnormal variable length code is accidentally associated with some code and decoded, and more than 63 AC coefficients are obtained, all codes obtained beyond 63 are replaced with 0 codes. The switch 11d is switched.

That is, when more than 63 AC coefficients are obtained for one DCT block, the AC coefficients obtained for more than 63 AC coefficients are replaced with 0 codes, and these data are dequantized by an inverse quantization circuit. 12 is input. Then, after the inverse quantization processing is performed by the inverse quantization circuit 12, the data after the inverse quantization is written to the video segment memory 16 (VS memory).

As described above, the run-length decoding circuit 11 (R
LD), a DCT with more than 63 AC coefficients
For blocks only, AC coefficients obtained over 63 are 0
The output is replaced with a sign.
DCT blocks in the same macroblock as the DCT block from which the C coefficient was obtained or in the same video segment may also be affected by this error.

[0072] Therefore, it is desirable to replace a part of the data in the DCT block, which may be affected by the error, with the 0 code. By switching the unit 18, the data is replaced.

Here, the unpacking circuit 9 outputs the grouping information described in the first embodiment, and the DCT / VLC / AC counter 20 includes the run-length decoding circuit 11 (RLD). DCT currently being processed
Block number (DCT No.), variable length code number (VL
C No. A) when AC coefficients are obtained from variable-length codes
The C coefficient number (AC No.) is output.

[0074] The grouping information conversion section 19 outputs the grouping information output from the unpacking circuit 9, the DCT block number (DCT No.) output from the DCT / VLC / AC counter 20, and the variable length code number ( VLC No.), AC coefficient number (AC No.)
Is input, and the variable length code number in the grouping information as shown in FIG. 3 is converted into an AC coefficient number when the variable length code is decoded, and is output as conversion grouping information.

On the other hand, the third memory 21 receives the conversion grouping information from the grouping information conversion unit 19 and the error detection signal from the error control unit 15, and as described above, one DCT The error signal generator ER is used only when more than 63 AC coefficients are obtained in the block.
2 outputs an H signal, that is, an error detection signal. Only at that time, the conversion grouping information for one video segment from the grouping information converter 19 is written to the third memory 21.

The reproduction data limiting unit 17 outputs the DCT block number (DCT No.) and the AC coefficient number (AC No.) currently read by the video segment memory 16 (VS memory). Although the counter value is input from the AC counter 22, when the conversion grouping information is written in the third memory 21, the reproduction data restricting unit 17
On the basis of the counter value from the AC counter 22, the second data and the third data are 0-signed for all the DCT blocks in the video segment where the DCT block in which more than 63 AC coefficients are obtained is present. The switch 18 is switched to be replaced.

[0077] Then, the data for one video segment in which the second data and the third data are all replaced by 0 codes is output to the inverse DCT circuit 13 and subjected to inverse DCT processing. As described above, in the second embodiment, an abnormal variable length code is accidentally associated with some code and decoded, and
Even when more than three AC coefficients can be obtained, it is possible to reduce the possibility that the reproduced data will fail. Also,
By using the second embodiment in combination with the first embodiment, it is possible to further reduce the possibility that the reproduced data will fail.

In the second embodiment, an example has been described in which data having an error is replaced with 0 code at the time of run-length decoding. However, other codes may be used instead of run-length coding. Similarly, in the case where the compression encoding is performed according to the encoding method, the data in which the error has occurred is obviously replaced with the 0 code.

Next, a digital signal reproducing apparatus according to a third embodiment will be described. In the embodiments described above, when an error has occurred in the variable-length code, only data considered to be normal is output so as to prevent breakdown of the reproduced signal as much as possible. Alternatively, it has been replaced with a variable length code equivalent to the 0 code.

On the other hand, in the digital signal reproducing apparatus according to the third embodiment, when an error occurs in the variable length code, the digital signal reproducing apparatus in the video segment in which the error occurred variable length code exists. It is characterized in that data is replaced by data at the same position on the screen one frame before, and FIG. 11 shows an example of the configuration.

As shown, the frame memory 14 (FM)
It includes a first frame memory 14a, a second frame memory 14b, and first to third changeover switches (SW1 to SW3) therein, and a frame memory control unit 23 is newly added. I have.

[0082] The frame memory control unit 23
3a, a switching signal generator 23b, and a VS counter 23c. When there is an error in the variable-length code, the video segment number (VS No.) of the video segment in which the variable-length code in which the error has occurred exists. The data is written to the fourth memory 23a. At this time, the VS counter 23
c outputs the number of the video segment currently being written to the frame memory 14.

[0083] Then, when the video segment number (VS No.) indicating the error location written in the fourth memory 23a matches the number output from the VS counter 23c, the switching signal generator 23b outputs A control signal is output so as to switch the first and second changeover switches (SW1 and SW2) to the terminal B side.

The first and second changeover switches (SW1 and SW2) are normally switched to the terminal A side, and the image data from the inverse DCT circuit 13 is changed to 14a or 14a.
b, and the third switch (SW3) selectively outputs data read from the other frame memory to which no writing has been performed, but the third switch (SW3) controls the switching from the switching signal generator 23b. Based on the signal, the first and second changeover switches (SW1 and SW2) are switched to the terminal B side.
Instead of the image data from the third switch (SW
The image data from the frame memory which is selectively output via 3), that is, the image data of the same screen position one frame before is written.

That is, when an error has occurred in the video segment data written in the frame memory 14, the first and second changeover switches (SW1 and SW2) based on the control signal from the frame memory control unit 23. Is switched to the terminal B side, the image data of the video segment in which this error has occurred is replaced with the image data of the same screen position one frame before. When writing image data to one frame memory, it goes without saying that address control is performed so that image data at the same position on the screen one frame before is read from the other frame memory.

[0086] When control is performed based on a control signal from the frame memory control unit 23 to inhibit the write processing of the first and second frame memories 14a and 14b, the first and second changeover switches ( SW1 and SW2) need not be provided. At this time, the image data of the video segment in which the error has occurred is not written in the frame memory 14, and only the image data of the video segment in which the error has not occurred is written in the frame memory 14 to update the data. Therefore, the data of the video segment in which the error has occurred is replaced with the image data of the same screen position two frames before.

In the above embodiment, an example is shown in which the DCT block is composed of 8 pixels in the horizontal direction × 8 pixels in the vertical direction. However, the present invention is not limited to this, and 8 pixels in the horizontal direction × 4 pixels in the vertical direction, or It goes without saying that the DCT block may be constituted by another number of pixels such as 16 pixels in the horizontal direction × 16 pixels in the vertical direction.

[0088]

According to the digital signal reproducing apparatus and the reproducing method according to the present invention, when decoding digital data,
If there is an abnormality, what is the first and second data
It is identified whether there is an abnormality in these data, and the identification result
Restrictions on the use of decrypted digital data according to
Is changed, it is possible to reduce the probability that the reproduction data is broken, and an unnatural image such as a checkered pattern does not appear on the screen.

Further, when it is detected that there is an abnormality, if the data in the compressed block in which the abnormality is detected is replaced with the data of the compressed block at the same screen position which has already been decoded, the reproduction without any uncomfortable feeling is performed. Images can be obtained.

Further, a predetermined number of A
When a larger number of AC coefficients than the C coefficient are obtained, all data relating to the variable length code constituting the AC coefficient obtained by exceeding the predetermined number of AC coefficients is regarded as abnormal data, so that the reproduced data is broken. The probability can be further reduced, and the effect of stabilizing the quality of the reproduced image is achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main configuration of a digital signal recording / reproducing apparatus.

FIG. 2 is a diagram illustrating a DCT block and a zigzag scan.

FIG. 3 is a diagram illustrating run-length encoding and variable-length encoding.

FIG. 4 is a diagram showing a macroblock.

FIG. 5 shows an example in which data for one video segment is stored in five sync blocks.

FIG. 6 is a diagram for explaining the first embodiment of the present invention.

FIG. 7 is a diagram illustrating an example of grouping information.

FIG. 8 is a diagram illustrating data that is replaced with a variable length code indicating an EOB code.

FIG. 9 is a diagram for explaining a second embodiment of the present invention.

FIG. 10 is a diagram illustrating the operation of the variable length decoding circuit when there is no error in the variable length code.

FIG. 11 is a diagram for explaining a third embodiment of the present invention.

[Explanation of symbols]

 1, 14, 14a, 14b Frame memory 2 DCT circuit 3 Quantization circuit 4 Run length encoding circuit 5 Variable length encoding circuit 6 Packing circuit 7 Recording processing unit 8 Reproduction processing unit 9 Ann Packing circuit 9a Code data cutout unit 9b Code length table 9c Grouping memory unit 9d Write control unit 9e First memory 9f Second memory 9g Read control unit 9h, 17 Reproduction data limit unit 9i ... DCT / VLC counter 10 ... variable length decoding circuit 10a ... decoding section 10b ... decoding table 11 ... run length decoding circuit 11a ... down counter 11b ... holding circuit 11c ... OR circuit 11d ... switching device 12 ... inverse quantization circuit DESCRIPTION OF SYMBOLS 13 ... Inverse DCT circuit 15 ... Error control part 16 ... VS memory 18 ... Switching device 19 ... Grouping information conversion part 2 ... DCT · VLC · AC counters 21 ... third memory 22 ... DCT · AC counters 23 ... frame memory controller 23a ... fourth memory 23b ... switching signal generating unit 23c ... VS counter

Claims (8)

(57) [Claims] 1. A rectangular block obtained by dividing one screen in a horizontal direction and a vertical direction is subjected to an orthogonal transformation process and a variable length encoding process, and a plurality of rectangular blocks are treated as one compression block. Are sequentially stored as first data in a predetermined amount of storage area provided for each rectangular block so that the code amount of the compressed block is equal to or less than a predetermined value. A digital signal reproducing apparatus for decoding digital data stored as second data in a storage area for storing another rectangular block and restoring image data, wherein there is an abnormality in decoding the digital data. If
In any one of the first and second data,
Identification means for identifying abnormalities and use to limit the use of decoded digital data
Limiting means, and in accordance with the identification result of the identifying means,
A digital signal reproducing apparatus characterized by changing a condition of use restriction in the digital signal reproducing apparatus. 2. An abnormal condition occurs when the digital data is decoded.
If there is, the abnormality digital signal reproducing apparatus according to claim 1, wherein the replacing at 0 code without the use of all or part of the second data of a compressed block is. 3. An error in decoding the digital data.
2. The digital signal reproducing apparatus according to claim 1 , wherein when there is an error, the data of the compressed block having the abnormality is replaced with the data of the compressed block at the same screen position which has already been decoded. 4. A rectangular block obtained by dividing one screen in a horizontal direction and a vertical direction is subjected to an orthogonal transformation process and a variable length encoding process, and a plurality of rectangular blocks are treated as one compression block. Are sequentially stored as first data in a predetermined amount of storage area provided for each rectangular block so that the code amount of the compressed block is equal to or less than a predetermined value. A digital signal reproduction device for decoding digital data stored as second data in a storage area for storing another rectangular block to restore image data, wherein the digital data is subjected to the orthogonal transformation processing.
And a predetermined number of AC coefficients obtained by
Is provided for each of the rectangular blocks to detect an abnormality in the digital data.
At least detection means, and an abnormality is detected when decoding the digital data.
If anomalies have been detected, anomalies exist in the compression
Restricting use of the second data in the block, and
If more AC coefficients are obtained than the number of AC coefficients,
Forming AC coefficients obtained by exceeding a predetermined number of AC coefficients.
Treat all data related to variable-length codes as abnormal data
A digital signal reproducing apparatus characterized by the above-mentioned. 5. A rectangular block obtained by dividing one screen in a horizontal direction and a vertical direction is subjected to an orthogonal transformation process and a variable length coding process, and further, a plurality of rectangular blocks are treated as one compression block. Are sequentially stored as first data in a predetermined amount of storage area provided for each rectangular block so that the code amount of the compressed block is equal to or less than a predetermined value. decodes the digital data stored as the second data storage area for storing the other rectangular block, a digital signal reproduction method for restoring the image data, there is an abnormality in the decoding of the digital data If
In any one of the first and second data,
Identify whether there was an error and decode the decoded data.
Digital data, and according to the identification result,
Conditions for restricting use of digital data after decoding
A digital signal reproducing method characterized by changing the following. 6. An error in decoding the digital data.
If there was, a digital signal reproducing method according to claim 5, wherein the replacing without the use of all or a portion of the second data in the compression block the had abnormality in 0 code. 7. An error in decoding the digital data.
6. The digital signal reproducing method according to claim 5 , wherein when there is a defect, the data of the compressed block having the abnormality is replaced with the data of the compressed block at the same screen position which has already been decoded. 8. A rectangular block obtained by dividing one screen in a horizontal direction and a vertical direction is subjected to an orthogonal transformation process and a variable length encoding process, and further, a plurality of rectangular blocks are treated as one compression block. Are sequentially stored as first data in a predetermined amount of storage area provided for each rectangular block so that the code amount of the compressed block is equal to or less than a predetermined value. A digital signal reproduction method for decoding image data by decoding digital data stored as second data in a storage area for storing another rectangular block, wherein the digital data is subjected to the orthogonal transformation processing.
And a predetermined number of AC coefficients obtained by
For each of the rectangular blocks, and an abnormality was detected during the decoding of the digital data.
If anomalies have been detected, anomalies exist in the compression
Restricting use of the second data in the block, and
If more AC coefficients are obtained than the number of AC coefficients,
Forming AC coefficients obtained by exceeding a predetermined number of AC coefficients.
Treat all data related to variable-length codes as abnormal data
A digital signal reproducing method characterized in that: