JP3341807B2 - Logic gate - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic gate constituting a high-speed and multifunctional semiconductor logic circuit.

[0002]

2. Description of the Related Art As shown in FIG. 4, there is known a logic gate in which two resonance elements (negative resistance elements) D1 and D2 having an n-type differential negative resistance characteristic are connected in series. KJ
Chen, T. Akeyoshi and K. Maezawa: Abs. 1994 Sold State
Devices and Materials, Yokohama, 1994, p. 979;). In this logic gate, with the given power supply voltage V _bias from one end of the negative resistance element D2, the input voltage V _in to the negative resistance element D1, the power supply voltage V _bias of the intermediate voltage to the output voltage V
_I take it _out .

The operation of this logic gate will be described below. First, the current-voltage characteristic of one negative resistance element is
As shown in FIG. 5, this negative resistance element exhibits a voltage control type negative resistance characteristic before the normal forward rise. This is due to, for example, a tunnel current. Negative resistance element D having such a negative resistance characteristic
When D1 and D2 are connected in series as shown in FIG.
As shown in FIG. 6, the stable point of the system changes according to the power supply voltage _Vbias .

That is, as shown in FIG. 6A, when _Vbias is smaller than twice the peak voltage Vp of the negative resistance element D1, the point S becomes a stable point of the system. And
The output voltage V _{out at} this time is V _bias / 2. on the other hand,
As shown in FIG. 6B, when V _bias is larger than 2 Vp, the system has two stable points, S1 and S2. here,
This logic gate operates in a bistable operation, and the output voltage V is changed due to the difference in the negative resistance characteristics of the two negative resistance elements D1 and D2.
_out VB or VC.

[0005] Whether the system settles in S1 or S2,
Due to the difference between the peak currents of the two negative resistance elements D1 and D2
Is determined. For example, as shown in FIG.
If the peak current of the resistive element D1 is larger,
The state becomes point S1 and the output voltage V_out Becomes VB. to this
On the other hand, as shown in FIG.
If the peak current is greater, the state of the system will be point S2
Output voltage V_out Becomes VC. And this negative resistance element
In order to form a logic circuit using the children D1 and D2, V_{bi as}
Using a drive voltage that periodically changes up and down 2Vp
You. This works as a clock and when the voltage rises
Switching will occur.

Now, in order to operate this as a logic gate, it is necessary to modulate the peak current according to the input voltage. One method for this is to connect a field effect transistor T in parallel with the negative resistance element D, as shown in FIG. At this time, the current flowing through the composite element including the negative resistance element D and the field effect transistor T is the sum of the two. Therefore, as shown in FIG. 7B, the gate voltage V of the field-effect transistor T
With g, the peak current can be effectively modulated.

FIG. 8 shows an inverter circuit using the above-described composite element. In this inverter circuit, it is necessary to design the peak current characteristics of the negative resistance elements D1 and D2 as shown below. First, the input voltage V _in is "Low" (to 0
In the case of V), the sum of the current of the field effect transistor T and the peak current of the negative resistance element D1 is smaller than the peak current of the negative resistance element D2. In contrast, when the input voltage V _in is "High", the sum of the peak current of the current and the negative resistance element D1 of the field effect transistor T is larger than that the peak current of the negative resistance element D2. These negative resistance elements can be set, for example, by designing the area of the diode if a resonant tunneling diode is used as the negative resistance element.

[0008]

By the way, in the above-mentioned conventional logic gate, the peak current of the negative resistance element D2 must be larger than the peak current of the negative resistance element D1. Whether to do so is an important factor in design. Here, the field effect transistor T
Is a general enhancement type, the input voltage V
The current when _in is "Low" can be regarded as substantially 0, which is convenient. That is, the peak current of the negative resistance element D2 may be designed to be larger than the peak current of the negative resistance element D1 without regard to the characteristics of the field effect transistor T.

However, the situation is different in the case of a general depression type transistor. In the case of a depletion type transistor, a current generally flows even at an input “Low” where the gate voltage and the source voltage are at the same potential. Therefore, it is necessary to take this into consideration in designing the peak current of the negative resistance element D2. That is, it is necessary to consider the amount of current flowing even at this input “Low” as an offset when designing the peak current of the negative resistance element D1. However, the value of the current flowing even at the input “Low” strongly depends on the transistor characteristics such as the threshold value and the transconductance. Therefore, there is a problem that these designs are difficult.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and a logic gate using two negative resistance elements exhibiting a differential negative resistance between two terminals can be more easily provided. It is intended to be able to be manufactured.

[0011]

SUMMARY OF THE INVENTION A logic gate according to the present invention comprises a first gate connected to ground with a differential negative resistance between two electrodes.
Shows negative differential resistance between 1 negative resistance element and 2 electrodes
A second negative resistance element is connected in series;
A logic gate in which a periodically changing drive voltage is applied to both ends of the
In over DOO, first field effect in the first negative resistance element
Are connected in parallel, and the connected field-effect second transistor is connected in parallel to the second negative resistance element. The current that flows through the first transistor when the gate voltage is 0 volt flows through the second transistor as well.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. Embodiment 1 FIG. 1 is a circuit diagram showing a configuration of an inverter circuit using a logic gate according to a first embodiment of the present invention. In the first embodiment, the negative resistance element D2 (second negative resistance element) and the negative resistance element D1 (first negative resistance element) are connected in series similarly to the above-described conventional configuration.
Field effect transistor T1 (first transistor)
Are connected in parallel to the negative resistance element D1. The power supply voltage V _bias is applied to the negative resistance element D2, the input voltage V _in is input to the gate of the transistor T1, the output voltage V _out is taken out from the middle of the negative resistance element D2 and a negative resistance element D1 ing.

In the first embodiment, in addition to the above-described configuration, a field effect transistor T2 (second transistor) is connected in parallel to the negative resistance element D2,
The gate of the transistor T2 is short-circuited to the source. The transistor T2 has the same element configuration as the transistor T2, such as a gate length and a gate width. As a result of these configurations, in the first embodiment, when the gate voltage and the source-to-source voltage of the transistor T1 are equal to 0 volt, the current flowing between the source and the drain of the transistor T1 and the current of the transistor T2 The current flowing between the source and the drain becomes the same.

In the transistor T2, the source and the gate are connected, and the source voltage and the gate voltage are always the same. That is, the transistor T2 is in the same state as when the gate voltage and the source-to-source voltage of the transistor T1 are the same as 0 volt. For this reason,
When the transistors T1 and T2 are of a general depletion type, the current flowing through the transistor T2 is
This is the same as the current flowing as an offset in the transistor T1 on the negative resistance element D1 side. Therefore, the current corresponding to the offset can be compensated for by the transistor T2.

As is clear from the above, according to the first embodiment, a depression-type transistor can be used as the transistor T1 as in the case of using an enhancement-type transistor. That is, since the current flowing through the transistor T1 even when the input is “Low” is compensated by the depletion-type transistor T2, the peak current of the negative resistance element D2 may be set to be larger than the peak current of the negative resistance element D1. .

Further, as a result of manufacturing, even if the threshold value and the transconductance of the transistor T1 fluctuate from the design values, this characteristic fluctuation is also reflected on the transistor T2, and the transistor T1 and the transistor T2 always obtain almost the same characteristics. Can be Therefore, the transistor T2 always compensates for the current flowing through the transistor T1 at a gate voltage of 0 volt, and a wider manufacturing margin can be obtained. In the above description, a general depletion type transistor is used to facilitate the description. However, in the transistors T1 and T2, a current flows between the source and the drain when the gate voltage and the source-to-source voltage are the same. It is a transistor. Depending on the setting of the threshold value, even in the enhancement-type transistor, a current may flow between the source and the drain when the gate voltage and the source-to-source voltage are the same potential. 1 is applicable.

Embodiment 2 Hereinafter, a case where the present invention is applied to a circuit that performs weighted addition threshold logic by increasing the number of input terminals will be described. In the second embodiment, the case where there are three inputs is shown. However, the present invention is not limited to this, and the number of inputs is arbitrary. In the second embodiment, as shown in FIG. 2, three transistors T21 are connected to negative resistance element D1.
a, T21b, and T21c are connected in parallel so that weighted addition threshold logic can be performed. This transistor T
21a, T21b, and T21c have gate widths W1, W2, and W3, respectively.

In the second embodiment, the negative resistance element 1 includes three transistors T22a, T22b, and T22.
22c are connected in parallel. In addition, the transistors T22a, T22b, and T22c have gate widths W1, W2, and W3, respectively. Thus, similarly to the first embodiment, the transistor T2
As 1a to T21c, it becomes possible to use a depression-type transistor as in the case of using an enhancement-type transistor.

That is, the current flowing through the depletion type transistors T21a to T21c even when the input is "Low" is reduced by the depletion type transistors T22a to T22.
Since the peak current of the negative resistance element D2 is set to be larger than the peak current of the negative resistance element D1, since the compensation is made by c. As described above, according to the second embodiment, the circuit for performing the weighted addition threshold logic in which the number of input terminals is increased by using a plurality of depletion-type field effect transistors is provided by two negative resistances. It can be composed of elements.

Third Embodiment In the second embodiment, in order to provide three inputs, three transistors T22a and T22a are connected to the negative resistance element D2.
Although 22b and 22c are connected in parallel, the invention is not limited to this. As shown in FIG. 3, the gate width is set to W1.
The transistor T23 of + W2 + W3 may be connected in parallel to the negative resistance element 1. By doing so, the number of elements can be reduced.

Fourth Embodiment In the first to third embodiments, the input terminal is provided on one of the negative resistance elements. However, the present invention is not limited to this. May be provided. In the first to third embodiments, the negative weighting is performed. However, by providing the input terminals to both negative resistance elements, it is possible to cope with both the positive weighting and the negative weighting. . In this case, a field effect transistor is connected in parallel to each of the two negative resistance elements, and its gate is used as an input terminal. In the fourth embodiment, in addition to the signal input transistor, a compensation transistor having a gate and a source connected in parallel is connected to the negative resistance element to which the power supply voltage V _bias is applied. With this configuration, the fourth embodiment has the same effects as those of the first to third embodiments.

[0022]

As described above, according to the present invention, 2
A first negative electrode grounded with differential negative resistance between the two electrodes
Resistive element and a second element that exhibits differential negative resistance between the two electrodes.
Are connected in series with the negative resistance element of
The logic gate to which the drive voltage that changes periodically is applied to
Oite, the first transistor of the field-effect to the first negative resistance element connected in parallel, the second transistor of the field effect gate and source are connected to the second negative resistance element in parallel It was to appear to be connected. Therefore, when the gate voltage and the source voltage are the same, the current flowing through the first transistor also flows through the second transistor to compensate. As a result, in the present invention, by setting the peak current values of the first and second negative resistance elements, respectively,
That Ki out to design the operating characteristics of logic gates. That is, according to the present invention, since there is no need to consider the current flowing in the first transistor when there is no input, there is an effect that a logic gate using two negative resistance elements can be manufactured more easily. .

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of an inverter circuit using a logic gate according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of an inverter circuit using a logic gate according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a configuration of an inverter circuit using a logic gate according to a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a configuration of a conventional logic gate in which two resonance elements (negative resistance elements) having an n-type differential negative resistance characteristic are connected in series.

FIG. 5 is a characteristic diagram showing current-voltage characteristics of a negative resistance element.

6 is a characteristic diagram showing current-voltage characteristics of the logic gate shown in FIG.

FIG. 7 is a circuit diagram showing a configuration in which a field-effect transistor is connected in parallel to a negative resistance element, and a characteristic diagram showing current-voltage characteristics thereof.

FIG. 8 is a circuit diagram showing an inverter circuit using a composite element including two negative resistance elements and a field effect transistor connected in parallel to one of the negative resistance elements.

[Explanation of symbols]

D1, D2: negative resistance element, T1, T2: transistor.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H03K 19/12 H03K 19/01

Claims (4)

(57) [Claims] 1. A two and the first negative resistance element which is grounded shows a negative differential resistance between the electrodes, the second negative resistance element and a series showing the negative differential resistance between the two electrodes Connected to
In addition, a drive voltage that changes periodically is applied to both ends.
A first gate of a depletion type in which two output terminals are connected in parallel to the first negative resistance element; and two output terminals of the second negative resistance element. A depletion-type field-effect second transistor connected in parallel and having a gate connected to one output terminal. 2. The logic gate according to claim 1, wherein the second transistor has characteristics similar to those of the first transistor. 3. The logic gate according to claim 1, wherein a plurality of said first and second transistors are connected in parallel to said first and second negative resistance elements. Gate. 4. The logic gate according to claim 1, wherein a plurality of said first transistors are connected to said first negative resistance element, and a gate width of said second transistor is equal to said plurality of first transistors.
A logic gate, characterized in that it is the sum of the gate widths of the transistors.