JPH0249519B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a sense amplifier used in semiconductor integrated circuits and the like.

[Prior art]

With the recent advances in electronic computers, semiconductor integrated circuits are becoming more and more highly integrated, faster, and faster.
High stability is desired. Under such circumstances, differential amplifiers and the like are used as sense amplifiers that operate at high speed and are used in these semiconductor integrated circuits to detect minute changes in potential at the output point.
However, due to its configuration, the characteristics of a differential amplifier are
It is sensitive to fluctuations in manufacturing conditions, power supply voltage, etc., has a small operating margin, and because it relies on a mechanism that detects potential, there is a certain limit to its operating speed.
There is a problem in that the above-mentioned demands for high speed and high stability cannot be fully satisfied.

[Purpose of the invention]

The purpose of the present invention is to provide a sense amplifier that solves the above-mentioned problems and that allows high-quality products to be obtained even when manufacturing conditions vary, and that operates extremely stably even when power supply voltage etc. fluctuate. It's about doing.

[Structure of the invention]

The sense amplifier of the present invention includes a load circuit connected to an input terminal as an input current source, a first current mirror circuit connected between a first and a second voltage supply terminal, and an output of the first current mirror circuit. at least one sense circuit comprising a first load transistor connected between the terminal and the second voltage supply terminal and outputting an output signal from the output terminal of the first current mirror circuit; and at least one sense circuit that is electrically connected to the load circuit. The input current source is a dummy current source that generates a current equal to the load current flowing in the state, and its reference voltage output terminal is connected to the control electrode of the first load transistor of the sense circuit to supply the first and second voltages. a second current mirror circuit connected between the terminals; and a control electrode connected between the output terminal of the second current mirror circuit and the second voltage supply terminal, and a control electrode connected to the output terminal of the second current mirror circuit. a reference voltage generation circuit comprising a second load transistor connected thereto, the saturation current value of the first load transistor of the sense circuit is greater than the saturation current value flowing to the output terminal of the first current mirror circuit. Each current value is set so that the current value is also small.

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the present invention.

In this embodiment, the first current mirror circuit 15 is a p-type field effect transistor (hereinafter referred to as FET) whose drain and gate are connected to the first node _N1 and whose source is connected to the first voltage supply terminal 5. ) and an n-type inverter whose drain is connected to the node N ₁ and whose gate is connected to the output of the first inverter IN ₁ whose input is connected to the input terminal 7 and whose source is connected to the input terminal 7 whose input current source is the load circuit 2. FETQ ₂ , and a p-type FETQ ₃ whose drain is connected to the output terminal 8, whose gate is connected to the node _N1 , and whose source is connected to the first voltage supply terminal 5, whose drain is connected to the output terminal 8 and whose gate is the reference voltage output terminal. 9
n whose source is connected to the second voltage supply terminal 6
one sense circuit 1 consisting of a p-type FETQ ₄ , a second current mirror circuit 16, a p-type FETQ ₅ whose drain and gate are connected to the node N ₂ and whose source is connected to the first voltage supply terminal 5; An n-type FETQ ₆ whose drain is connected to node N ₂ and whose gate is connected to the output of the second inverter IN 2 _whose input is connected to node N ₃ and whose source is connected to node N ₃ and a load connected to node N ₃ . A dummy current source 4 generates a current equal to the load current flowing when the circuit 2 is in a conductive state, and a p-type current source 4 whose drain is connected to the reference voltage output terminal 9, whose gate is connected to the node _N2 , and whose source is connected to the first power supply terminal 5. and a reference voltage generating circuit ₃ consisting of an n-type eighth FETQ ₈ whose drain and gate are connected to the reference voltage terminal 9 and whose source is connected to the second voltage supply terminal ₆ . In order to make the saturation current value of FETQ ₃ smaller than that of FETQ 3, FETQ ₃ , Q ₄ ,
Conductance g _n of Q ₇ and FETQ ₈ and respectively
When g _n3 , g _n4 , g _n7 and g _n8 , g _n3 > g _n7 or
The settings are made to satisfy the following relationships: g _n4 < g _n8 or g _n3 < g _n7 , g _n4 < g _n8 , and g _n7 < g _n8 , and the sense circuit 1 and the reference voltage generation circuit 3 are connected to each other using other FETs. The logic threshold voltages of the FET g _n and the first and second inverters IN ₁ and IN ₂ are respectively set to be equal.

In this embodiment, as the load circuit 2, a ROM in which a Y selector and a read-only memory (ROM) cell are connected in series is used. Further, the dummy current source 4 has the same shape as the load circuit 2, and has the same potential relationship as the load circuit 2 in a conductive state.

FIG. 2 is a drain current-voltage characteristic diagram of FETQ ₃ and Q ₄ , and the operation of this embodiment will be explained below with reference to FIG.

First, in the reference voltage generation circuit 3, the dummy current source 4 corresponding to the load circuit 2 in a conductive state is connected, and since the inverter IN ₂ and FETQ ₆ are connected as shown in Fig. 1, the node N ₃ The potential becomes approximately equal to the logical threshold voltage of the inverter _IN2 , and a current i flows through the dummy current source 4. The logic threshold voltages of inverter IN ₁ and inverter IN ₂ and the g _n of FETQ ₂ and FETQ ₆ are set to be equal, and the load circuit 2 and dummy current source 4 are also set to be equal when they are in a conductive state. Therefore, if the load circuit 2 is conductive, the same current i as that of the dummy current source 4 flows through the load circuit 2 as well.

Here, since the current i is flowing to the dummy current source 4, the current i also flows to FETQ ₅ , and the g _n (g _n5 ) of FETQ ₅ is applied to FETQ ₇ , which has a current mirror relationship with FETQ ₅ .
_{The current} i′ ₍ i′=
g _n7 /g _n5 ×i) flows, and a similar current i' flows through the load FETQ ₈ connected in series with the FETQ ₇ . Furthermore, as shown in FIG. 1, the gate electrode of FETQ 4 for the load of the first current mirror circuit 15 is connected to the reference voltage output terminal 9, and the gate electrode of FETQ ₄ for the load of the first current mirror circuit ₁₅ is connected to the reference voltage output terminal ₉ .
is also in a current mirror relationship, and FETQ ₄ has i _Q4 (i _Q4 = g _n4 / g _n8 × i') in the saturation region as shown in Figure 2.
A current flows.

On the other hand, when current flows to the load circuit 2 in the sense circuit 1 (corresponding to the case where there is a ROM cell in the ROM of this embodiment), the g _n of FETQ ₁ and FETQ ₅ and the g _n of FETQ ₃ and FETQ ₇ are set equal. _{Since it is set to}
= i', and the drain current/voltage characteristics of FETQ ₃ are as shown in Figure 2. In this case FETQ ₃ and
Since FETQ ₄ is connected in series, a high level voltage "V _H ", which is the intersection of the drain current/voltage characteristic curves of FETQ ₃ and FETQ ₄ , is output to the output terminal 8.

By the way, since the sense circuit 1 and the reference voltage generation circuit 3 are formed on the same semiconductor substrate, each FET
The matching is very good, and the high level “V _H ”
The current flowing through FETQ ₃ and FETQ ₄ that specifies _Q3 =
The ratio of i′ to i _Q4 =g _n4 /g _n8 ×i′ (=g _n8 /g _n4 ) hardly changes even if the manufacturing conditions, power supply _voltage , etc. can output stably. Also, in this embodiment, compared to the conventional sense amplifier that detects changes in potential,
Because it detects the presence or absence of a fast-tracking current, it operates even faster.

Next, when no current flows to load circuit 2 (corresponding to the case where there is no ROM cell in the ROM of this embodiment), no current flows to FETQ ₁ , and therefore no current flows to FETQ ₃ (FETQ ₃ is in the off state). ), the ground potential (low level) is output to the output terminal 8.

In addition, in the above explanation, g _n4 of FETQ ₄ is replaced with g n4 of FETQ _8.
We have explained the case where g _n of the other paired FETs and the logic threshold voltages of inverters IN ₁ and IN ₂ are all set to be smaller than FET Q _{3 .}
Set g _n3 larger than g _n7 of FETQ ₇ , or
Or each of g _n3 of FETQ ₃ and g _n4 of FETQ ₄
smaller than each of g _n7 of FETQ ₇ and g _n8 of FETQ ₈ ,
In addition, it may be set so that g _n7 < g _n8 . That is, as shown in Fig. 2, the saturation current i _Q3 of FETQ ₃
If the saturation current i _Q4 of FETQ ₄ is in the relationship i _Q3 ≫ i _Q4 , when the load current flows through the load circuit 2, “V _H ”
When no load current flows, a low level voltage of the ground potential is output, resulting in extremely stable and high-speed operation.

FIG. 3 is a circuit diagram showing essential parts of a second embodiment of the present invention.

In this embodiment, in the first current mirror circuit 15 of the first embodiment shown in FIG. 1, the drain is connected to the node _N1 , the gate is connected to the clock signal terminal 10, and the source is connected to the first voltage supply terminal 5. p-type
Consists of adding FETQ ₉ .

This embodiment is intended to speed up the precharging of the parasitic capacitance of the load circuit 2. That is, the load circuit 2 connected to the input terminal 7 of the sense circuit 1
The parasitic capacitance associated with
The charge for charging up to a potential approximately equal to the logic threshold voltage of IN ₁ is supplied through FETQ ₁ , but as shown in
By connecting FETQ ₉ between the first power supply terminal 5 and node _N1 , it is possible to increase the speed of charge up. This pre-charge FET is a p-type FET,
Either type of FET may be used as an n-type FET.

FIG. 4 is a circuit diagram of a third embodiment of the present invention.

In this embodiment, in the circuit of the first embodiment shown in FIG. 1, the first and second current mirror circuits are FETQ ₂ and FETQ, respectively, instead of the first and second inverters IN ₁ and IN ₂ , respectively. The first signal STOP is connected between the gate and source of ₆ and is input to one of the signal input terminals 11 and 13 at a high level during a period when the sense circuit 1'' and the reference voltage generation circuit 3' do not need to operate. and a second 2-input NOR gate NOR ₁
and NOR ₂ , and a p-type signal whose drain is connected to the node N ₁ and whose gate is connected to the first signal STOP and the second signal ( ) input terminal 12 whose source is connected to the first power supply terminal 5 FETQ ₁₀ , the drain is at node _{N2 and} the gate is the second signal input terminal 14
p whose source is connected to the first power supply terminal 5
It consists of a FETQ of type ₁₁ and containing.

This embodiment is designed to prevent through current in the sense circuit and reference voltage generation circuit in the circuit of the first embodiment shown in FIG.

That is, NOR instead of inverters IN ₁ and IN ₂
Connect gates NOR ₁ and NOR ₂ as shown in Figure 4,
One input of each NOR gate is set to "1" during the period when the sense circuit 1'' and reference voltage generation circuit 3' do not need to operate.
Apply a signal (STOP) that makes the level
Sense circuit 1″ during which the signal STOP is at “1” level
FETQ ₁₀ and FETQ 11 are turned on by preventing a through current from flowing through the reference voltage generation circuit 3 _{' and by applying a signal having a reverse phase relationship with the signal STOP to the gates of FETQ 10 and} FETQ ₁₁ . By doing so, there is a period node where the sense circuit 1'' and the reference voltage generation circuit 3' do not need to operate.
By fixing the potentials of N ₁ and node N ₂ to the first supply voltage V _CC , leakage current and through current are completely prevented from flowing through FETQ ₃ and FETQ ₇ .

If only the NOR gates NOR ₁ and NOR ₂ are inserted, the potential of nodes N ₁ and N ₂ will be V _CC −V _TP
(V _CC is the first supply voltage, V _TP is the threshold voltage of the p-type FET), so FETQ ₃ and FETQ ₇ are also in the off state, but a small leakage current flows and the node N ₁ , If there is noise etc. on _N2 , _FETQ3 or
Although there is a possibility that the FETQ ₇ will turn on and a through current will flow, this embodiment can completely prevent this as described above.

In the above embodiment, only one sense circuit is used, but it goes without saying that the present invention is similarly applicable to a case where a plurality of sense circuits are connected to one reference voltage generation circuit.

〔Effect of the invention〕

As explained above in detail, the sense amplifier of the present invention has the above-described configuration, and by detecting the presence or absence of current flowing through the load, high-quality products can be obtained at high speed and without being affected by fluctuations in manufacturing conditions. is,
It has the effect of operating extremely stably against fluctuations in power supply voltage, etc.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of the first embodiment of the present invention;
The figure is a drain current-voltage characteristic diagram of a field effect transistor to explain its operation, FIG. 3 is a circuit diagram showing the main part of the second embodiment of the present invention, and FIG. It is a circuit diagram of an example. 1, 1', 1''... sense circuit, 2... load circuit, 3, 3'... reference voltage generation circuit, 4... dummy current source, 5... first voltage supply terminal, 6... th... Voltage supply terminal 2, 7...input terminal, 8...output terminal, 9...reference voltage output terminal, 10-14...
Signal input terminal, 15...first current mirror circuit,
16...Second current mirror circuit, Q ₁ , Q ₃ , Q ₅ ,
Q ₇ , Q ₉ , Q ₁₀ , Q ₁₁ ... p-channel field effect transistor, Q ₂ , Q ₄ , Q ₆ , Q ₈ ... n-channel field effect transistor, IN ₁ , IN ₂ ... inverter, NOR ₁ , NOR ₂ ...NOR gate, _VCC ...first supply voltage, i, i', i _Q3 , i _Q4 ...current.

Claims (1)

[Claims] 1. A first current mirror circuit connected between the first and second voltage supply terminals using a load circuit connected to the input terminal as an input current source, and an output of the first current mirror circuit. at least one sense circuit comprising a first load transistor connected between the terminal and the second voltage supply terminal and outputting an output signal from the output terminal of the first current mirror circuit; and at least one sense circuit that is electrically connected to the load circuit. The input current source is a dummy current source that generates a current equal to the load current flowing in the state, and its reference voltage output terminal is connected to the control electrode of the first load transistor of the sense circuit to supply the first and second voltages. a second current mirror circuit connected between the terminals, and a control electrode connected between the output terminal of the second current mirror circuit and the second voltage supply terminal;
and a second load transistor connected to the output terminal of the current mirror circuit of the sense circuit, the saturation current value of the first load transistor of the sense circuit is such that the saturation current value of the first load transistor of the sense circuit is A sense amplifier characterized in that each current value is set to be smaller than a saturation current value flowing through an output terminal. 2. A first current mirror circuit includes a first field effect transistor of one conductivity type, the drain and the gate of which are connected to the first node, the source of which is connected to the first voltage supply terminal, and the drain of which is connected to the first node. a second field effect transistor of opposite conductivity type, whose gate is connected to the output of the first inverter whose input is connected to the input terminal; whose source is connected to the input terminal of which the load circuit is an input current source; and whose drain is connected to the output terminal. The gate is the first
a third field effect transistor of one conductivity type, the source of which is connected to the first voltage supply terminal at the node, the drain of which is connected to the output terminal, the gate of which is connected to the reference voltage terminal, and the source of which is connected to the second voltage supply terminal. at least one sense circuit comprising a fourth field effect transistor of opposite conductivity type connected, and a second current mirror circuit having a drain and a gate connected to the second node and a source connected to the first voltage supply terminal. a fifth field effect transistor of one conductivity type connected, a drain connected to the second node, a gate connected to the output of the second inverter, an input connected to the third node, and a source connected to the third node; a sixth field effect transistor connected to the third node; a dummy current source that generates a current equal to the load current flowing when the load circuit is conductive; and a dummy current source whose drain is connected to the reference voltage output terminal; the fourth of the sense circuit through
a seventh field effect transistor of one conductivity type, the gate of which is connected to the second node, the source of which is connected to the first power supply terminal, and the drain and gate of which are connected to the reference voltage output terminal; a reference voltage generation circuit comprising an eighth field effect transistor of opposite conductivity type whose source is connected to the second voltage supply terminal; When the conductance g _n of the transistor is g _n3 , g _n4 , g _n7 and g _n8 respectively, g _n3 > g _n7 or g _n4 < g _n8 or g _n3
< g _n7 , g _n4 < g _n8 , g _n7 < g _n8 , and other field effect transistors are used to form pairs of field effect transistors in the sense circuit and the reference voltage generation circuit, respectively. 2. The sense amplifier according to claim 1, wherein the conductance g _n and the logical threshold voltages of the first and second inverters are set equal. 3. The first current mirror circuit includes a ninth field effect transistor of one conductivity type, whose drain is connected to the first node, whose gate is connected to the clock signal terminal, and whose source is connected to the first power supply terminal. A sense amplifier according to claim 2. 4. A first current mirror circuit and a second current mirror circuit are respectively connected between the gate and source of the second field effect transistor in place of the first and second inverters, and have one input connected to the sense circuit and the second field effect transistor. first and second two-input NOR gates to which a first signal at a high level is input during a period when the reference voltage circuit does not need to operate; a drain is connected to the first node and a gate is connected to the first signal; a tenth field effect transistor of one conductivity type, whose source is connected to the first voltage supply terminal and whose drain is connected to the second node and whose gate is connected to the second signal input terminal in an antiphase relationship; a first conductivity type whose source is connected to the signal input terminal of the first power supply terminal;
The sense amplifier according to claim 2, comprising eleven field effect transistors.