JP3343933B2 - Television signal processing circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a high-definition television signal.
The present invention relates to a television signal processing circuit for processing a down-converted signal of a signal and an NTSC or PAL signal.

[0002]

2. Description of the Related Art A conventional television signal processing circuit of this type processes a MUSE down-convert signal of a high-definition television signal as an NTSC signal to perform wide display. Wide display refers to displaying a landscape screen for a high-definition television signal on a normal television receiver, and can display all images on the landscape screen. For example,
When the MUSE down-convert signal is displayed, 387 lines can be displayed as shown in the following equation. 1032 ÷ 2 × 3/4 (number of MUSE video signal scanning lines) (down-conversion) (compression ratio for wide display) However, in the NTSC signal, as shown in the following equation,
Only 363 lines can be displayed, and the number of scanning lines is reduced by 24 compared to the case where the MUSE signal is displayed. (525-40) x 3/4 (number of NTSC scanning lines) (number of blanking scanning lines) (compression ratio for wide display)

[0003]

As described above, the conventional television signal processing circuit processes a MUSE down-convert signal as an NTSC signal to perform wide display, so that the number of scanning lines is smaller than the original number. There has been a problem that the number of images is reduced and the image is missing.

The present invention has been made in view of such a situation, and an object of the present invention is to provide a television signal processing circuit which does not cause picture loss even when a down-converted signal is displayed in a wide view.

[0005]

A television signal according to the present invention is provided.
Signal processing circuit switches between the first signal and the second signal
Signal switching means for outputting the
A signal obtained by compressing the vertical direction of the output first signal.
Signal at the top and bottom of the signal, or
The vertical direction of the second signal output from the switching means is compressed.
The predetermined range of the upper and lower ends of the signal obtained by
Mask means for replacing the mask signal with the mask signal and outputting the mask signal;
Which of the signal and the second signal is signal switching
Depending on the output from the means, by the mask means
A first signal or a second signal replaced with a mask signal
Mask control means for controlling the range of
The means is provided when the first signal is output from the signal switching means.
The second signal is output from the signal switching means.
Is replaced by a mask signal rather than the first case.
So that the signal range becomes smaller.
It is characterized in that the range to be replaced is controlled.

[0006]

[0007]

In the television signal processing circuit of the present invention,
Is switched between the first signal and the second signal and output
Is obtained by compressing the vertical direction of the output first signal.
A predetermined range of the upper end and lower end of the signal to be
A signal obtained by compressing the vertical direction of the output second signal.
A predetermined range of the upper and lower ends of the signal is placed in the mask signal.
And output. Also, the first signal and the second signal
Depending on which signal is being output.
Range of the first signal or the second signal to be
Enclosure is controlled. At this time, the first signal is being output.
Is higher than when the second signal is output.
Also, the range of the first signal replaced with the mask signal is small.
Thus, the range to be replaced is controlled.

[0008]

[0009]

FIG. 1 shows an embodiment of a television signal processing circuit according to the present invention. The MUSE signal is supplied to the A / D converter 2, where it is converted into a digital signal. The MUSE signal converted into a digital signal is supplied to the decoding unit 4, where it is decoded into Y (luminance) and (RY) and (BY) (color difference) baseband signals. Since the decoded signal conforms to the HDTV standard, the horizontal frequency is 33.75 kHz and the vertical frequency is 60.
Hz and the number of scanning lines is 1125. NTSC converter 6
Extracts 525 scanning lines including 516 video signal portions from 1125 scanning lines of this signal, converts the horizontal frequency to 15.75 kHz of the NTSC standard, and converts the vertical frequency to 60 Hz of the NTSC standard. Convert. The signal processing performed by the NTSC converter 6 is called down-conversion. The NTSC conversion unit 6 supplies the output MUSE down-convert signal to the input terminal 8A of the switch 8.

As shown in FIG. 3 , an external NTSC signal that has been horizontally compressed and corresponds to a landscape screen is input to an NTSC decoding unit 1.
0, where it is decoded into Y (luminance) and (RY) and (BY) (color difference) signals. The decoded signal is supplied to an NTSC / A / D conversion unit 12, where it is converted into a digital signal, and an input terminal 8B
Supplied to

The switch 8 is connected to an input terminal 8A.
Either the USE down-convert signal or the external NTSC signal supplied to the input terminal 8B is output from the output terminal 8C in response to a selection signal supplied from the user via, for example, a remote controller.

The vertical filter section 14 performs vertical filter processing in consideration of thinning out scanning lines in the memory 16 provided in the next stage. The memory 16 has a capacity capable of storing an image for one field,
The writing timing is controlled by the writing control unit 18 so that only three of the four scanning line signals output from are written (that is, one out of four scanning lines are discarded). You. The scanning line signals written in the memory 16 are sequentially read under read timing control by the read control unit 20. As a result, the signal is compressed by 3/4 in the vertical direction, and becomes a signal that can be displayed on a general television receiver .

The signal output from the memory 16 has no video signal in the portions corresponding to the upper end and the lower end of the screen of the television receiver.
Is replaced with another signal such as a gray signal. The timing of this replacement is as follows. For the MUSE down-convert signal, the MUSE mask timing unit 24 sends the input terminal B and the output terminal Y of the mask timing switch 26.
The external NTSC signal is controlled by the MUSE mask timing signal supplied to the mask unit 22 via the input terminal A and the output terminal Y of the mask timing switch 26 from the NTSC mask timing unit 28. Is controlled by an NTSC mask timing signal supplied to the. The MUSE mask timing unit 24 masks a portion corresponding to 138 scanning lines,
The NTSC mask timing section 28 masks a portion corresponding to 162 scanning lines. Note that the mask section 22
It is provided for each of the Y, (RY) and (BY) signals.

The output signal of the mask section 22 is converted into an analog signal by the D / A conversion section 30. The converted Y, (RY) and (BY) signals output from the D / A converter 30 are converted into a matrix circuit (not shown).
Are converted into R, G, and B signals, and supplied to a CRT.

FIG. 4 shows an example of the configuration of a counter constituting a part of the MUSE mask timing section 24 and the NTSC mask timing section 28. FIG. 5 shows the mask section 22 and the MU.
4 shows a configuration example of the remaining parts of the SE mask timing unit 24 and the NTSC mask timing unit 28.

[0016] In FIG. 4, the upper counter 50, medium counter 51 and the lower counter 52 is inverted VT signal H4 of 4 times the frequency 4f _H of the horizontal synchronizing frequency is supplied to the clock terminal, is supplied to the load terminal L 26 depending on the signal
Cleared every 2.5H. And
Ripple carry output RC of the lower-order counter 52 is supplied to the terminal E _T medium counter 51, a ripple carry output RC moderate counter 51 supplied to the upper counter 50K terminal E _T
Is done.

The tenth output from the upper counter 50
, Ninth and eighth bit signals VQ10, VQ9 and VQ8 are inverted by inverters 53, 54 and 55, respectively, and inverted tenth, ninth and eighth bit signals XVQ10, XVQ9 and X
VQ8.

The seventh output from the middle counter 51,
Sixth, fifth and fourth bit signals VQ7, VQ
6, VQ5 and VQ4 are connected to the inverter 5
6, 57, 58 and 59,
, Sixth, fifth and fourth bit signals XVQ7, XVQ6, XVQ5 and XVQ4.

The third place output from the lower counter 52,
Second, first and zeroth bit signals VQ3, VQ
2, VQ1 and VQ0 are connected to inverter 6
0, 61, 62 and 63, inverted third
Bit signal XVQ3, XVQ2, XVQ1 and XVQ0 .
You.

The MUSE mask timing unit 2 shown in FIG. 5
4 will be described. The tenth inverted bit XVQ
10, inverted 9th bit XVQ9 and 8th bit VQ8
Is input to the AND gate 70. 7th inverted bit XVQ
7, inverted 6th bit XVQ6 and 5th bit VQ5
Is input to the AND gate 71. Inversion 4th bit XVQ
4. Inversion third bit XVQ3 and second bit VQ2
Is input to the AND gate 72. AND gate 70, 71
And 72 are input to NAND gate 76. NA
The output of the ND gate 76 is supplied to one input terminal of a NAND gate 78.

The tenth bit VQ10, the inverted ninth bit XVQ9 and the inverted eighth bit XVQ8 are AND
Input to the gate 73. Inverted 7th bit XVQ7,
The inverted sixth place bit XVQ6 and the inverted fifth place bit XV
Q5 is input to the AND gate 74. The inverted fourth bit XVQ4, the third bit VQ3, and the inverted second bit XVQ2 are input to the AND gate 75. AN
The outputs of D gates 73, 74 and 75 are input to NAND gate 77. The output of NAND gate 77 is N
It is supplied to one input terminal of an AND gate 79.

The output of the NAND gate 78 is supplied to the other input terminal of the NAND gate 79. The output of the NAND gate 79 is a synchronous flip-flop (D-FF)
Supplied to 80 D inputs. The synchronous clock terminal of the flip-flop (D-FF) 80, signal H4 of 4 times the frequency 4f _H of the horizontal synchronizing frequency is supplied. The output of the synchronous flip-flop (D-FF) 80 is supplied to the input terminal B of the mask timing switch 26 and to the other input terminal of the NAND gate 78.

[0023]

Next, the configuration of the NTSC mask timing section 28 shown in FIG. 5 will be described. The tenth inverted bit XVQ10, the ninth inverted bit XVQ9, and the eighth inverted bit
VQ8 is input to the AND gate 90. Inverted 7th bit XVQ7, 6th bit VQ6 and inverted 5th bit XVQ
5 is input to the AND gate 91. 4th bit VQ
4. Inversion third bit XVQ3 and second bit VQ2
Is input to the AND gate 91. AND gate 90, 91
And 92 are input to NAND gate 96. NA
The output of the ND gate 96 is supplied to one input terminal of a NAND gate 98.

The tenth bit VQ10, the inverted ninth bit XVQ9, and the inverted eighth bit XVQ8 are AND
The signal is input to the gate 93. Inverted 7th bit XVQ7,
The inverted sixth place bit XVQ6 and the inverted fifth place bit XV
Q5 is input to the AND gate 94. The inverted fourth bit XVQ4, the third bit VQ3, and the inverted second bit XVQ2 are input to the AND gate 95. AN
The outputs of D gates 93, 94 and 95 are input to NAND gate 97. The output of NAND gate 97 is N
The signal is supplied to one input terminal of the AND gate 99.

The output of the NAND gate 98 is supplied to the other input terminal of the NAND gate 99. The output of the NAND gate 99 is a synchronous flip-flop (D-FF)
100 D inputs. The synchronous clock terminal of the flip-flop (D-FF) 100, the signal H4 of 4 times the frequency 4f _H of the horizontal synchronizing frequency is supplied. The output of the synchronous flip-flop (D-FF) 100 is supplied to the input terminal A of the mask timing switch 26 and to the other input terminal of the NAND gate 98.

[0027]

When the user selects a MUSE down-convert signal with a remote controller or the like, the mask timing switch 26 outputs an M signal (“1”) to the selection input terminal S.
Is supplied, the output of the synchronous flip-flop (D-FF) 80 supplied to the input terminal B, ie, MUSE
The mask timing signal 24M is supplied from the output terminal Y to one input terminal of the AND gate 26A. The mask timing switch 26 supplies the N signal (“0”) to the selection input terminal S when the user selects an external NTSC signal using a remote controller or the like. Formula flip-flop (D-FF) 100
From the output terminal Y to one input terminal of the AND gate 26A.
Supply.

The other input terminal of the AND gate 26A receives "0" (=) during the horizontal (H) blanking period.
A signal HBK that is “L”) is supplied. Therefore, AN
The MUSE mask timing signal 24M is output from the output terminal of the D gate 26A except for the horizontal blanking period.
(“1” = “H”) or the NTSC mask timing signal 28M (“1” = “H”) is supplied to the selection input terminals S of the switches 111 and 112 of the mask unit 22.

Input terminals 1A, 2A, 3A of switch 111
And 4A are supplied with the upper 4 bits of the digital data from the memory 16. Input terminal 1 of switch 111
B, 2B, 3B and 4B have a mask data generator 1
Supply upper 4 bits of mask data generated from 13
Is done. The mask data is output from the mask data generator 113.
Set by switch.

Input terminals 1A, 2A, 3A of switch 112
And 4A are supplied with the lower 4 bits of the digital data from the memory 16. Input terminal 1 of switch 112
B, 2B, 3B and 4B have a mask data generator 1
Supply the lower 4 bits of the mask data generated from 13.
Is done.

The switches 111 and 112 output the MUSE mask timing signal 24M (“1” = “H”) or N
TSC mask timing signal 28M (“1” = “H”)
Is supplied to the selection input terminal S, the mask data generated from the mask data generator 113 is output from the output terminals 1Y, 2Y, 3Y and 4Y, and the MUS
E mask timing signal 24M (“1” = “H”) and NTSC mask timing signal 28M (“1” =
When “H”) is not supplied to the selection input terminal S, the digital data from the memory 16 is output to the output terminal 1.
Y, 2Y, 3Y and 4Y.

[0033] Next, with reference to FIG. 6, memory 16, MUSE
The operation of the mask timing section 24 and the NTSC mask timing section 28 will be described. Upper counter 50 of FIG. 4, middle counter 51 and the lower counter 52, the respective clock terminals, signal H4 of 4 times the frequency 4f _H of the horizontal synchronizing frequency is supplied, inverted VT signal supplied to the load terminal L Is cleared every 262.5H. At this time,
Figure 6 is an address in the vertical direction memory 16 (a), when the transverse time, the memory 16, writing is performed as indicated by the broken line, reading as indicated by the solid line is performed. This is because only three of the four scanning lines are written to the memory 16, so that the reading is performed in ／ of the writing time.

When the input signal is a MUSE signal, 1
With 258 scanning lines per field, the blanking period is 4H (horizontal synchronization period). Therefore, the signal period to be read is 258 × 3/4, that is, 193H. Assuming that the read end point is 262H, the read start point is 69H. Since the signal that has passed through the vertical filter unit 14 is input to the mask unit 22, the upper and lower ends of the input signal of the mask unit 22 are not normal signals, so it is necessary to apply a mask of about 4H. . Therefore,
At the upper end, the mask is applied to 69H + 4H = 73H, and at the lower end, the mask is applied from 262H-4H = 258H.

The MUSE mask timing unit 2 shown in FIG. 5
4, the output bit signals VQ10, VQ9, VQ8, VQ7, VQ6, VQ5, VQ4, VQ3 of the counters 50, 51 and 52
And when VQ2 is 0, 0, 1, 0, 0, 1, 0, 0 and 1 (73 in decimal), that is, the bit signal XVQ
10, XVQ9, VQ8, XVQ7, XVQ6, VQ5, XVQ4, XVQ
When AND3 and VQ2 are all "1", AND gate 7
Since the outputs of 0, 71 and 72 become "1", the output of the NAND gate 76 becomes "0" and the output bit signals VQ10, VQ9, VQ8, VQ7,
VQ6, VQ5, VQ4, VQ3 and VQ2 are 1, 0, 0,
0, 0, 0, 0, 1, and 0 (25 decimal
8), that is, bit signals VQ10, XVQ9, XVQ8, XVQ
7. When XVQ6, XVQ5, XVQ4, VQ3 and XVQ2 are all "1", the outputs of the AND gates 73, 74 and 75 become "1", so that the output of the NAND gate 77 becomes "0".
Becomes Therefore, the synchronous flip-flop (D-FF) 80
Of the output Q is up to 73H and from 258H to “1” (=
"H"). Thus, 73H at the upper end
Up to 258H at the lower end.

When the input signal is an NTSC signal, 1
With 242 scan lines per field, the blanking period is 20H. Therefore, the read signal period is 242 × 3/4, that is, 181H. Assuming that the read end point is 262H, the read start point is 81H.
It is. Since the signal that has passed through the vertical filter unit 14 is input to the mask unit 22, the upper and lower ends of the input signal of the mask unit 22 are not normal signals, so it is necessary to apply a mask of about 4H. . Therefore, at the upper end portion, masking is performed up to 81H + 4H = 85H, and at the lower end portion, masking is applied at 262H-4H = 258H.

[0037] shown in FIG. 5 NTSC mask timing section 2
8, the output bit signals VQ10, VQ9, VQ8, VQ7, VQ6, VQ5, VQ4, VQ3 of the counters 50, 51 and 52
And when VQ2 is 0, 0, 1, 0, 1, 0, 1, 0 and 1 (85 in decimal), that is, the bit signal XVQ
10, XVQ9, VQ8, XVQ7, XVQ6, XVQ5, VQ4, XVQ
When 3 and VQ2 are all "1", AND gate 9
Since the outputs of 0, 91 and 92 become “1”, the output of the NAND gate 96 becomes “0” and the output bit signals VQ10, VQ9, VQ8, VQ7,
VQ6, VQ5, VQ4, VQ3 and VQ2 are 1, 0, 0,
0, 0, 0, 0, 1, and 0 (25 decimal
8), that is, bit signals VQ10, XVQ9, XVQ8, XVQ
7, when XVQ6, XVQ5, XVQ4, VQ3 and XVQ2 are all "1", the outputs of the AND gates 93, 94 and 95 become "1", so that the output of the NAND gate 97 becomes "0".
Becomes Therefore, the synchronous flip-flop (D-FF) 10
The output Q of 0 is up to 85H and from 258H to “1” (=
"H"). Thus, 85H at the upper end
Up to 258H at the lower end.

As described above, in the above embodiment,
It is possible to eliminate image loss during wide display of the MUSE down-convert signal, and to optimize the display area.

In the above embodiment, the NTSC signal is supplied as an external signal, but a PAL signal may be supplied. In this case, the MUSE signal is set to NT
It is better to downconvert to a PAL signal instead of an SC signal. Then, the replacement of the MUSE down-convert signal with, for example, a gray signal or the like by the mask is performed by using the P by the mask.
It may be smaller than the replacement of the AL signal with, for example, a gray signal.

[0040]

According to the present invention, the down conversion signal
Signal display area is smaller than the NTSC or PAL signal display area.
Can be widened when displaying down-converted signals.
In the image can be eliminated.

According to the television signal processing circuit of the second aspect, the switching of the mask amount can be externally down-converted.
Since the signal is selected depending on which of the NTSC signal and the NTSC signal or the PAL signal is selected, it is possible to display an image according to the user's selection of the type of television signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a television signal processing circuit of the present invention.

FIG. 2 is an explanatory diagram of a screen showing vertical compression processing for wide display.

FIG. 3 is an explanatory diagram of a screen showing a horizontal compression signal.

FIG. 4 is a block diagram showing a configuration example of a counter forming a part of a MUSE mask timing unit 24 and an NTSC mask timing unit 28;

FIG. 5 is a block diagram illustrating a configuration example of a mask unit 22, and the remaining portions of a MUSE mask timing unit 24 and an NTSC mask timing unit 28;

FIG. 6 is a timing chart showing operations of a memory 16, a MUSE mask timing unit 24 and an NTSC mask timing unit 28 in the embodiment of FIG.

[Explanation of symbols]

 2 A / D conversion unit 4 Decoding unit 6 NTSC conversion unit 8 Switch 10 NTSC decoding unit 12 NTSC / A / D conversion unit 14 Vertical filter unit 16 Memory 18 Write control unit 20 Read control unit 22 Mask unit 24 MUSE mask timing unit 26 Mask timing switch 28 NTSC mask timing section

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04N 7/01 H04N 5/46

Claims (1)

(57) [Claims] 1. The vertical frequency of a high-definition television signal.
And horizontal frequency as the frequency of NTSC standard or PAL standard.
The first down conversion signal obtained by
NTSC or PAL compatible with signals and landscape screens
A television that processes a second signal as a standard signal
A signal processing circuit for switching between the first signal and the second signal and outputting the signal.
Signal switching means, and the first signal output from the signal switching means.
Top and bottom of signal obtained by compressing in the vertical direction
Output from the signal switching means.
Signal obtained by compressing the vertical direction of the second signal
The specified range at the top and bottom of the signal is placed in the mask signal.
Mask means for converting and outputting the signal; and any one of the first signal and the second signal.
Signal is output from the signal switching means.
Is replaced by the mask signal by the mask means.
Controlling the range of the first signal or the second signal.
Mask control means , the mask control means comprising:
The second signal is output when the signal is output from the switching means.
Signal is output from the signal switching means.
The range of the first signal to be replaced with the mask signal
Is replaced by the mask means so that
Television signal processing characterized by controlling the range
circuit.