JP3346845B2 - Semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a method for gradually amplifying a plurality of read data of small amplitude read from a memory cell to a large amplitude signal of CMOS level through a medium amplitude differential signal. The present invention relates to a semiconductor memory device having a data bus for outputting to an output unit and having a test mode for testing the data bus.

[0002]

2. Description of the Related Art FIG. 8 shows a conventional semiconductor memory device having a test mode.
FIG. 7 is a diagram showing a path until read data is output to an external pin. In FIG. 8, input / output data lines IO1, ZI
OOn, ZIO2... IOn, ZIOn are supplied to differential amplifiers P1, P2. These differential amplifiers P1, P2,... Pn are several hundred meters input to the input / output data lines.
A small-amplitude differential signal of V is amplified to a medium-amplitude differential signal of 600 mV to less than 1 V, and the differential amplifiers P1, P2,.
The output of Pn is the read data bus lines R1,
Are supplied to differential amplifiers PP1, PP2,..., PPn via ZR1, R2, ZR2,. Differential amplifier P
.., PPn amplify the middle-amplitude differential signal into a CMOS-level large-amplitude differential signal with “H” level = Vcc and “L” level = 0 V. Differential amplifiers PP1, PP2 ...
The output of PPn is the data line RR1, ZRR1, RR2, Z
RR2... RRn and ZRRn are provided to the selector 53. The selector 53 is connected to the data lines RR1, ZRR1, R
One of R2, ZRR2,... RRn, ZRRn is selected and output to the inputs OD, ZOD of the output control circuit 60.

An output control circuit 60 includes MOS transistors 54 and 55 connected in series between a power supply voltage + Vcc and ground.
And The NAND gate 56 detects whether or not the read bus operates normally in the test mode, and receives the outputs of the differential amplifiers PP1, PP2,. Further, the NAND gate 56 is supplied with a ZTE signal which goes to “L” level in the test mode by the inverter 6.
It is inverted at 3 and given. The ZT signal output from the NAND gate 56 is supplied to the selector 53, is inverted by the inverter 64, and is supplied to the selector 53 as a T signal.

Next, the operation of the read data bus shown in FIG. 8 will be described. First, during normal read, Z
The TE signal is set to “H” level. For this reason,
NAND gate 56 is closed. When read data is input to the input / output data line IO1 of the n sets of input / output data lines, data read from a memory cell (not shown) is supplied to the input / output data line IO1 as a small-amplitude differential signal. This small-amplitude differential signal is amplified by a first-stage differential amplifier P1 into a medium-amplitude differential signal, and read data buses R1, Z
Output to R1. The differential amplifier PP1 amplifies the medium-amplitude differential signal of the read data buses R1 and ZR1 into a large-amplitude differential signal and outputs the amplified signal to the next data bus RR1 and ZRR1. The selector 53 supplies the data buses RR1 and Z
RR1 is selected, and the input OD, ZO of the output control circuit 60 is selected.
Output to D. N channel M receiving this OD and ZOD
An output control circuit 60 composed of the OS transistors 54 and 55 outputs read data to the outside. That is, at the time of normal reading, the read data, which is a small-amplitude differential signal, is amplified to a medium-amplitude differential signal by the differential amplifier P1 at high speed, and the next-stage differential amplifier PP1 converts the medium-amplitude differential signal into a large-amplitude differential signal. By amplifying to a differential signal, the read data is output at high speed as a whole of the MOS RAM circuit. Here, other differential amplifiers P2... Pn and PP unrelated to read data
2 ... PPn does not operate, and only two differential amplifiers P1 and PP1 operate.

Next, the operation in the test mode will be described. In the n-bit compression test mode, n sets of data from the input / output data lines IO1 to IOn are input. Here, “H” level data is written into n bits to “H”.
Consider a test mode for reading level data. When the "H" level data is all correctly read, n differential amplifiers P1 to Pn operate and receive this output, and n differential amplifiers PP1 to PPn operate to output NAND.
The signal is input to the circuit 56. Here, in the test mode, ZT
The E signal is at the “L” level. When "H" level data is correctly read from all m bits, the ZT signal output from NAND gate 56 goes to "L" level, the T signal goes to "H" level, and selector circuit 53 outputs T and ZT. The signals are output to the inputs OD and ZOD of the control circuit 60, and the output Dout of the output control circuit 60 becomes "H" level, and a normal operation flag is set. But,
When even one bit malfunctions and the "L" level data is read, the ZT signal output from the NAND gate 56 goes to the "H" level, the T signal goes to the "L" level, and the output control circuit 60 "L" level data is output to the output Dout, and a malfunction flag is set.

[0006]

As described above, in the conventional semiconductor memory device, only two differential amplifiers P1 and PP1 operate in the normal mode. However, in the n-bit degenerate test mode, P1 to Pn are used. It is necessary to operate all of the n differential amplifiers up to n and the n differential amplifiers PP1 to PPn, and n times as many differential amplifiers as the normal mode operate. Current consumption increases sharply. When the current consumption increases, the noise of the ground and the power supply line generated by the circuit operation increases, the circuit malfunctions, and it is difficult to correlate with the lead in the normal mode.

Therefore, a main object of the present invention is to provide a semiconductor memory device capable of suppressing current consumption in a test mode, reducing malfunction due to noise, and correlating with a read in a normal mode. It is to be.

[0008]

A semiconductor memory according to the present invention is provided.
Memory device tests whether multiple memory circuits are normal.
Semiconductor memory device having a test mode
Each is provided corresponding to a plurality of memory circuits.
In normal mode, data read from the corresponding memory circuit
Data signal having a first amplitude voltage by amplifying the data signal
Output from the corresponding memory circuit in the test mode
The amplified data signal is amplified to be larger than the first amplitude voltage.
A plurality of data signals having different second amplitude voltages are output.
A first amplifier circuit and one end of each of the first
A plurality of data lines for receiving output data signals of one amplifier circuit;
Is activated in the test mode, and the power of multiple data lines is
Determine if multiple memory circuits are normal based on pressure
The judgment circuit is connected to the other end of each of the plurality of data lines.
Each is connected via a corresponding data line in normal mode.
And amplifies the given data signal from the first amplitude voltage.
Also outputs a data signal with a large third amplitude voltage, and tests
A plurality of second amplifier circuits that are deactivated in the mode.
Ru Der thing was painting.

Preferably, the first amplifier circuit has a corresponding
The data signal read from the memory circuit is amplified and the second signal is amplified.
A differential amplifier for outputting a data signal having a width voltage;
In the normal mode, the amplitude voltage of the corresponding signal transmission line is set to the first
Amplitude voltage is limited, and in the test mode,
And a width limiting circuit.

[0010]

[Action] In the semiconductor memory device according to the present invention, a plurality of
Memory circuits and multiple memory circuits
Each of them has a corresponding memory circuit in normal mode.
Amplifies the data signal read from
Output a data signal that has
The data signal read from the memory circuit is amplified and the first signal is amplified.
A data signal having a second amplitude voltage greater than the width voltage
And a plurality of first amplifier circuits that output
Receiving output data signals of a plurality of first amplifier circuits, respectively;
Activated in the test mode and multiple data lines
Multiple memory circuits are normal based on the voltage of data lines
A judgment circuit for judging whether or not a plurality of data lines
Are connected to the other end of the
Amplify the data signal given via the data line of
A data signal having a third amplitude voltage larger than the first amplitude voltage
And outputs a plurality of second signals that are deactivated in the test mode.
Amplifying circuit is provided. Therefore, test mode
At this time, since the plurality of second amplifier circuits are inactivated,
Smaller current and less malfunction due to noise
Can be correlated with the lead in normal mode.
Wear. In the normal mode, the amplitude voltage of the data line is
Since it is kept small, data signals can be transmitted at high speed.
it can. Preferably, the first amplifier circuit includes a corresponding memory
Amplifying the data signal read from the circuit to generate a second amplitude signal;
Differential amplifier for outputting a data signal having a voltage
Mode, the amplitude voltage of the corresponding signal transmission line is set to the first amplitude
Voltage control, which is limited to voltage and deactivated in test mode
Limit circuit. In this case, the first amplifier circuit can be easily provided.
Can be configured.

[0011]

FIG. 1 is a connection diagram of a path from an input / output line to an external pin in a semiconductor memory device according to an embodiment of the present invention. In FIG. 1, the data bus includes differential amplifiers P1,
.. 10n are connected between P2... Pn and PP1, PP2.

Further, the semiconductor memory device shown in FIG. 1 includes a row decoder 1, column decoders 31, 32... 3n, and sense amplifiers 21, 22,. Row decoder 1 activates word lines WL1a, WL1b. Word line WL1
are connected to the gates of the n-channel cell transistors 41, 42,..., and the memory cell capacitors 51, 52,. The drains of the cell transistors 41, 42 are connected to bit lines BL1, BL2,..., And sense amplifiers 21, 22, are connected to the bit line pairs BL1, ZBL1, BL2, ZBL2.
2 are connected. Further, the bit line pairs BL1 and Z
BL1, BL2 and ZBL2 are n-channel transistors 1
Input / output lines IO via 11, 112, 113, 114...
1, ZIO1, IO2, ZIO2,.
These transistors 111, 112, 113, 114
Are supplied with column signals CSL1, CSL2,... From column decoders 31, 32,.

FIG. 2 is a circuit diagram showing an example of the amplitude limiting circuit shown in FIG. In FIG. 2, the amplitude limiting circuit includes n-channel transistors 8, 9 connected in series between read data buses R1 and ZR1, and the drains of n-channel transistors 8, 9 are supplied with power supply voltage Vcc. Are supplied with a ZTE signal. n
The channel transistors 8 and 9 are turned on when the ZTE signal goes to "H" level and operate as a clamp circuit. When the potentials of the read data buses R1 and ZR1 are going to be lower than Vcc-Vth, positive charges are applied from the power supply voltage Vcc. To prevent the voltage from falling below Vcc-Vth. here,
Vth is the threshold voltage of the n-channel transistors 8 and 9.

FIG. 3 is a specific circuit diagram of the selector shown in FIG. The selector 53 includes switching circuits 531 to 536 each having a combination of a p-channel transistor and an n-channel transistor.
n, ZS1... ZSn signals, these switching circuits 531 to 534 turn on, and read data bus RR
1, ZRR1... RRn, read data output to ZRRn are output to OD and ZOD. When the ZTE signal goes to “L” level, the switching circuits 535 and 536 are turned on, and the output signals T and ZT of the NAND circuit 56 become OD and ZO.
D is output. The control signals S1 and ZS1 are output from a column decoder shown in FIG.

FIG. 4 is a diagram for explaining a control signal output from the column decoder shown in FIG. In FIG. 4, a Y address signal is stored in a Y address buffer 200, and Y address signals are stored in column decoders 31, 32,.
, And the decoded outputs CSL1, CSL2,.
n, S1, S2... Sn, ZS1, ZS2.

FIG. 5 is an electric circuit diagram showing an example of the differential amplifier shown in FIG. The differential amplifier shown in FIG.
a current mirror circuit including p-channel transistors 27 and 28 and n-channel transistors 23 and 24;
It is constituted by a current mirror circuit including p-channel transistors 29 and 30 and n-channel transistors 25 and 26. The gates of the n-channel transistors 24 and 25 and the p-channel transistor 2
For example, the read data bus IO
1, ZIO1 are connected, and n-channel transistor 2
The output is taken from 7,29 sources.

FIG. 6 is a time chart for explaining the operation of FIG. 1, and FIG. 7 is a diagram for explaining a potential change of the read data bus.

Next, a specific operation of the embodiment of the present invention will be described with reference to FIGS. First, a read operation in the normal mode will be described. FIG. 6 (a)
When the word line WL1a selected by the row decoder 1 attains the "H" level at the time t1 shown in FIG.
(I = 1, 2,..., N), data of the memory cell is read out to ZBLi as shown in FIG. 6B, and is amplified by the sense amplifier 2i. At this time, the Y address signal is stored in the Y address buffer 200 as shown in FIG.
In response to the address signal shown in (c), a column selection signal CSLi and control signals Si and ZSi shown in FIG. 6D are generated from the column decoder 3i as decode signals.

In FIG. 6, when an internal address Y0 is received, n
Among the decoders, the column decoder 31 operates, and at time t1, the column selection signal CSL1 is at the “H” level, the control signal S1 is at the “H” level, and ZS1 is at the “L” level. When column select signal CSL1 is output from column decoder 31 at time t1, n-channel transistors 111 and 112 are turned on and bit lines BL1 and Z1 are turned on.
As shown in FIG. 6E, the data of BL1 is transmitted to the input / output line pair IO1 and ZIO1 as a small-amplitude differential signal of about several hundred mV. Of the n input / output line pairs, IO1, ZIO1
And the differential amplifier P1 amplifies the low amplitude "L" level or "H" level read data of the input / output line pair IO1 and ZIO1. As shown in FIG. It is output to the data buses R1 and ZR1 as a medium amplitude differential signal.

In the normal mode, since the ZTE signal is at "H" level, the n-channel transistors 8, 9 of the amplitude limiting circuit 101 connected to the complementary read data buses R1, ZR1 are turned on. I do.
These two transistors 8, 9 function as clamps, and the potentials of read data buses R1 and ZR1 are set to Vcc.
-Vth, positive charges are supplied from the n-channel transistors 8 and 9 and the read data bus R
1, the potential of ZR1 does not become lower than Vcc-Vth. The potential change of the read data bus at this time is as shown in FIG.

FIG. 7A shows the case where the read data is at "H" level.
When data of "H" level having a small amplitude of 100 mV of ZIO1 and ZIO1 are applied to amplitude limiting circuit 101, read data buses R1 and ZR1 have threshold voltages of n-channel transistors 8 and 9 (600 to 800 mV). "H" for amplitude
Level data is read. Next, the differential amplifier PP1
Operates, receives a medium-amplitude "H" level signal of read data buses R1 and ZR1, and receives read data buses RR1 and ZR1.
CRR of RR1 = Vcc, ZRR1 = 0V is applied to ZRR1.
"H" level data having a large amplitude of S level is output.
Here, when the control signal S1 becomes "H" level and the ZS1 becomes "L" level, the selector 53 conducts the switching circuits 531 and 532, and only the read data buses RR1 and ZRR1 involved in the read path are shown in FIG. As shown in (h), it is given to the inputs OD and ZOD of the output control circuit 60. Thus, the data of the read data bus selected by the selector 53 is transmitted, and the “H” level data is output to the output control circuit 60 to the outside as shown in FIG.

In FIG. 1, read data buses Ri, Z
Since Ri extends from the periphery of the memory cell array to the output control circuit 60, the wiring capacity increases. here,
If the amplitude of the read data buses Ri and ZRi is increased without suppressing the amplitude, a delay occurs because the read data bus having a large wiring capacity is charged and discharged. Therefore, in one embodiment of the present invention, by providing the amplitude limiting circuit 10, the amplitude of the read data bus is suppressed, thereby reducing the charge / discharge amount of the wiring capacitance of the read data bus, and as a result, the read data can be read at a high speed. Can tell. That is,
When the read path from the memory cell array to the output control circuit 60 is long, the small-amplitude differential signal is amplified to the medium-amplitude differential signal at a high speed. By amplifying the signal into a large-amplitude differential signal, the reading speed of the entire semiconductor memory circuit can be increased.

Next, the test mode will be described. The word line WL1a is selected by the row decoder 1, the column decoders 31... 3n operate, and n sets of input / output lines IO1.
Consider a test mode of n-bit compression in which read data of a memory cell is transmitted to On. The input / output lines IO1, ZIO1... IOn,
The ZIOn small-amplitude differential signal is amplified by the differential amplifiers P1 to Pn. At this time, the ZTE signal is at "L" level. Therefore, the amplitude limiting circuits 101... 10n
The transistors 8 and 9 for clamping the potential level of the read data bus at the time are turned off. As a result, the differential amplitude signals amplified by the differential amplifiers P1.
As shown in (b), the amplitude becomes larger than in the normal mode, and the differential amplitude swings to the level of the power supply voltage + Vcc. The read data bus signal with large amplitude is NA
The signal is input to the ND circuit 56. In the test mode, the differential amplifiers PP1 to PPn do not operate. For example, consider a case where an "H" level signal is written in all memory cells and a test is performed to determine whether "H" level data is read. When there is no reading error and all the read data at "H" level is output, output signal ZT of NAND circuit 56 attains "H" level and T signal attains "L" level. If "H" level data is not written to the memory cell and the read data has at least one "L" level bit, the output of NAND circuit 56 goes to "H" level and an error flag is set. And T, Z
T is the input O of the output control circuit 60 by the selector 53.
D, ZOD, and the test result is output to the output control circuit 60.
Output from

In normal reading, it is sufficient to amplify the differential amplitude of read data buses Ri and ZRi to threshold voltage Vth, and the gain of differential amplifiers P1... Pn is reduced. If this gain is small, it takes time to amplify the differential amplitude of read data buses Ri and ZRi to the level of power supply voltage Vcc in the test mode, but NAND circuit 56 senses "H" level or "L" level. It is enough to amplify to the level that you can,
Actually, the time until the signal is output from the NAND circuit 56 is the time until the NAND circuit 56 is amplified to a level at which the "H" level or the "L" level can be sensed, and the delay time is short.

As described above, in the test mode circuit according to the embodiment of the present invention shown in FIG. 1, since the amplitude limiting circuits 101... 10n are not operated in the test mode, n sets of input / output line pairs Since the small-amplitude differential signal is amplified by n differential amplifiers p1... Pn and the amplitudes of read data buses Ri and ZRi become larger than those in the normal read operation, and swings to near power supply voltage + Vcc level, read data bus R1 .., Rn can be received by the NAND circuit 56, and can be easily configured by the test mode circuit CMOS logic. In the test mode, since the differential amplifiers PP1 to PPn do not operate, the read data of the read data buses Ri and ZRi is input to the NAND circuit 56, and the data match / mismatch is output.
The current consumption can be reduced by the difference between the circuit operations of the differential amplifiers PP1 to PPn as compared with the conventional example shown in FIG.

As described above, in this embodiment, in the normal mode, the small-amplitude differential signals of the input / output lines IOi and ZIOi are amplified by the differential amplifiers P1.
The next-stage differential amplifiers PP1 to PPn further amplify the medium-amplitude differential signal to a large-amplitude differential signal and transfer the data. In the test mode, read data that is a small-amplitude differential signal of the input / output lines IOi and ZIOi. Amplify the read data buses Ri and ZRi into differential signals having an amplitude larger than the medium amplitude during normal read by the first-stage differential amplifiers P1... Pn, so that the NAND circuit 56 can detect data match / mismatch.

In the above-described embodiment, during normal reading, the n-channel transistors 8 and 9 of the amplitude limiting circuits 101... 10n function as clamp transistors to suppress the amplitude of differential signals on the read data buses Ri and ZRi. In the test mode, the amplitudes of the read data buses Ri and ZRi are increased by turning off the transistors 8 and 9, but the differential signal amplitudes of the read data buses Ri and ZRi are reduced during a normal read operation.
Any circuit may be used as long as it has a large amplitude operation in the test mode.

[0028]

As described above, the semiconductor memory according to the present invention is provided.
Memory devices have multiple memory circuits and multiple memory
Are provided corresponding to the memory circuits, each of which is in normal mode
When amplifying data signal read from corresponding memory circuit
And outputs a data signal having the first amplitude voltage.
In read mode, the data signal read from the corresponding memory
To a second amplitude voltage larger than the first amplitude voltage.
Plurality of first amplifier circuits for outputting a data signal having a voltage
And one end of each of the plurality of first amplifier circuits
A plurality of data lines for receiving output data signals and a test mode;
Is activated when the data line is
A determination circuit for determining whether or not a number of memory circuits are normal;
Each of the plurality of data lines is connected to the other end, and each is connected to a node.
In normal mode, data given via the corresponding data line
Amplifying the data signal to obtain a third signal which is larger than the first amplitude voltage.
Outputs an amplitude voltage data signal and is inactive in test mode.
And a plurality of second amplifier circuits to be implemented. did
Therefore, in the test mode, the plurality of second amplifier circuits are inactive.
Current consumption, the current consumption is small and noise
Error in normal mode
Correlation can be taken. In the normal mode,
The data voltage is high because the amplitude voltage of the
Can be transmitted quickly. Preferably, the first amplification cycle
Path increases the data signal read from the corresponding memory circuit.
Difference for outputting a data signal having a second amplitude voltage by width
Of the signal amplifier and the corresponding signal transmission line in normal mode.
The width voltage is limited to the first amplitude voltage,
And an amplitude limiting circuit to be activated. In this case, the first
Can easily be configured.

[Brief description of the drawings]

FIG. 1 is a connection diagram of a path from an input / output line to an output to an external pin in a semiconductor memory according to an embodiment of the present invention;

FIG. 2 is a circuit diagram illustrating an example of an amplitude limiting circuit illustrated in FIG. 1;

FIG. 3 is a specific circuit diagram of the selector shown in FIG. 1;

FIG. 4 is a diagram for describing a control signal output from a column decoder shown in FIG.

FIG. 5 is an electric circuit diagram showing an example of the differential amplifier shown in FIG.

FIG. 6 is a time chart for explaining the operation of FIG. 1;

FIG. 7 is a diagram for explaining a potential change of a read data bus.

FIG. 8 is a diagram showing connections from input / output lines of a semiconductor memory having a conventional test mode through read data buses until read data is output to external pins.

[Explanation of symbols]

1 row decoder 21, 22 sense amplifier 31, 32... 3n column decoder 41, 42 memory cell transistor 51, 52 memory cell capacitor 53 selector 60 output control circuit P1... Pn, PP1... PPn differential amplifier 101. , ZIO1 ... IOn, ZIOn I / O lines R1, ZR1 ... Rn, ZRn, RR1 ... RRn, ZRR
1 ... ZRRn read data bus 200 Y address buffer

Claims (2)

(57) [Claims] Testing whether a plurality of memory circuits are normal or not
A semiconductor memory device having a test mode that is provided for each of the plurality of memory circuits.
Are read from the corresponding memory circuit in normal mode.
The amplified data signal is amplified to obtain the data having the first amplitude voltage.
Output the corresponding memory circuit in the test mode.
Amplifying the data signal read from the path to produce the first amplitude
A data signal having a second amplitude voltage greater than
A plurality of first amplifying circuits for outputting , one ends of which are respectively connected to the plurality of first amplifying circuits;
A plurality of data lines receiving an output data signal, the plurality of data lines being activated during the test mode;
Whether the plurality of memory circuits are normal based on the voltage of
A determination circuit for determining, and each of the plurality of data lines;
Are connected to each other at the time of the normal mode.
Amplify the data signal given via the corresponding data line
And a third amplitude voltage larger than the first amplitude voltage.
Output in the test mode.
That Ru comprising a plurality of second amplifier circuits, the semiconductor memory device. 2. The first amplifier circuit amplifies a data signal read from a corresponding memory circuit.
A differential for outputting a data signal having the second amplitude voltage
Amplifier and corresponding signal transmission line in normal mode
Limiting the amplitude voltage to the first amplitude voltage;
2. An amplitude limiting circuit , which is deactivated at the time of loading.
Semiconductor memory device according to.