JP3347102B2 - Loop control circuit and loopback control device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention mainly relates to SDH (Sync
(Hronous Digital Hierarchy: International standard for high-speed relay speed systems) For loop control circuits for each user, which are used in a loop control loop, the loop is correctly inserted and folded in frame units and user units in a loop-back loop and has no adverse effect on other users. It relates to a control circuit.

[0002]

2. Description of the Related Art The current ITU-T recommends SDH (Synchronous Digital Hierarchy) for a B-ISDN hierarchical structure based on the SONET hierarchy (hierarchical structure). In three types of European networks (hierarchy), it is necessary to unify the speed and maintain synchronization. Therefore, it is necessary to perform communication using a dedicated frame. It is necessary to loop back to check the performance of the station and to isolate the faulty part.

At the time of loopback, an ATM (asynchronous transfer mode) network uses an ATM cell signal and a synchronizing signal as a set signal to prevent the occurrence of abnormal cells, but the SDH network has a point of synchronous transfer. A loopback scheme different from the ATM network is required.

Normally, in the SDH system, the number of time slots (TS) that can be used by each user is predetermined, and addition / deletion of a user is arbitrarily performed. Even when a user adds / deletes a loop, the loop must be continued without affecting other users.

For example, FIG. 5 shows that during execution of this loop,
An example of a time slot (TS) changing operation when a user is added / deleted will be described.

As shown in FIG. 5A, first, TS1 to TS2 for user a, TS3 to 4, TS for user b, and user c
When user b is in a loop (A) when user b is in a loop, and when user a is deleted and no longer uses TS 1-2, user b becomes TS 1-2 and user c This is changed to TS3 (FIG. 5B).

At this time, the user b in the loop must continue the loop and maintain the continuity of data. Also, do not affect other users. Similarly, when the user a is added (FIG. 5)
(C) However, the loop must be continuously performed and the continuity of data must be maintained.

[0008] The change of the TS is performed by asynchronous control. The instruction to change the TS is valid at each timing of downlink and uplink. As shown in FIG.
The timings shown in FIGS. 5A to 5B and 5C are not constant, and are specified as loop-back loop information at an arbitrary time. Therefore, it is necessary to take a timing.

[0009]

However, in the loopback system as shown in FIG. 1, a time slot for downlink data to be output from the device is added to a time period when a time slot for uplink data to be input to the device is vacant. This cannot be done simply. For example, the downstream frame phase shown in FIG. 4B and the upstream frame phase shown in FIG.
If they are only shifted, it is difficult to loop back the downlink data. In particular, when searching for a loopback location in a frame unit having a plurality of TSs, a downlink frame phase (FIG. 4B) and an uplink frame phase (FIG.
Just having a loop buffer that absorbs the phase difference of (F)) ((β) shown in FIG. 4) not only cannot maintain the continuity of the folded data but also affects other users. Would.

When a loop buffer corresponding to the phase difference ((.alpha.) Shown in FIG. 4) of the update timing of the downlink / uplink TS is provided, the loop buffer increases and the amount of delay increases.

The present invention absorbs the phase difference between the downstream frame phase and the upstream frame phase when looping back,
An object of the present invention is to reduce the capacity of a loopback buffer and reduce the amount of delay caused by the loopback buffer.

[0012]

According to the present invention, there is provided a loop control circuit for looping up uplink data and downlink data mutually, comprising a frame composed of a plurality of time slots, and a frame pulse for generating a pulse at a head position of the frame. A buffer control unit for inputting the first time slot of the loopback data and the number of necessary time slots following it and the first time slot of the original data added to the loopback data and the number of necessary time slots following the frame information. A buffer for writing and reading the return data in response to a write address and a read address from the buffer control unit, and selecting one of the original data and the return data by a selection control signal of the buffer control unit And a selector for performing the conversion according to the frame information. Wherein the folding La data in synchronization with said folded data to said frame pulse.

In the above-mentioned loop control circuit, the buffer control unit may receive the frame pulse and latch a time slot of the return data, and determine a return timing of latching the time slot of the original data. A timing counter for outputting the data timing and the load timing, a return F / F for storing a leading time slot of the return data and a required number of subsequent time slots in accordance with the return timing; F from the source which stores the head time slot of the source data and the required number of subsequent time slots in accordance with the data timing
/ F, a selection counter that counts a clock according to the load timing, a read counter that counts the clock according to the return F / F, an output of the selection counter, and an output of the original F / F. And a selector for selecting one of the original data and the return data based on an output of the comparator.

In the above-mentioned loop control circuit, the count of the read counter is reset by an output of the comparator, and the buffer writes the return data by a write address from the timing counter, and reads the read data from the read counter. It is characterized by reading by address.

In the above-mentioned loop control circuit, when the selector selects one of the original data and the loopback data, the selector selects the loopback frame in the frame information from the buffer control unit when the selector selects one of the original data and the loopback data. The return data is selected in synchronization with a frame pulse of the original frame among the original frames in the data.

Further, the present invention provides a loop control for returning a downlink signal to an uplink signal between a downlink signal (data) output from the device side to the line side and an uplink signal (data) output from the line side to the device side. In the circuit (FIG. 1), the execution of the loop is performed for each user. Further, the user uses a time slot (TS) designated in advance, and the TS to be used is changed by asynchronous control by adding / deleting another user. Even if another user is added / deleted while the loopback method is being executed and the TS of the user who is executing the loop is changed, a loop buffer is provided to control writing / reading of the buffer. This makes it possible to perform a loopback test without affecting other users.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments according to the present invention will be described.
This will be described in detail with reference to the drawings.

(1) Description of Configuration FIG. 1 is an explanatory diagram showing a basic concept according to an embodiment of the present invention. The device side and the line side are arranged opposite to each other, and the device side includes, for example, an exchange or a device in a station that executes various communication services.When loopback is performed, specific measurement data is transmitted. It is assumed that the user including the user is specified and the data of the plurality of time slots of the user is looped back. Further, the line side includes a transmission path to the next exchange, a monitoring device for monitoring the transmission path, and the like. In this system, data transmission and reception are performed by transmitting downlink data from the device side to the line side and receiving uplink data from the line side to the device side. This data is transmitted in units of one frame in a plurality of cells combined with cells of other users.

Here, depending on whether a failure has occurred on the line side or whether the data as downlink data is normal in the device side, the loop control circuit loops the downlink data and converts the data into uplink data. Insertion and loopback may occur. In this case, since data of another user is transmitted in the uplink data, it is not permitted to simply return the data, and the selection of the return timing and the timing of the uplink data is performed as shown in FIGS. The configuration is as shown.

FIG. 2 is a block diagram of a loopback control system showing an embodiment of the present invention. In FIG.
A buffer 2 for temporarily storing downlink data on the device side;
A buffer control unit 1 for inputting a frame pulse FP, a clock CLK, a leading TS value and loop information of the number of used TSs from the device side, and either the uplink data or the buffer 2 under the control of the buffer control unit 1 And a selector 3 to be selected. The buffer control unit 1 outputs the write address a and the read address b to the buffer 2 and
Outputs a selection control signal c. The selector 3 selects one of the uplink data and the return signal of the downlink data. Here, it is assumed that the write / read address of the buffer 2 is performed with data of one TS as one unit. Further, the capacity of the buffer 2 may be a data amount of the number of timeslots (TS) of the predicted downlink data to be turned back.

Referring to FIG. 2, the buffer control unit 3 supplies a frame pulse (F) indicating the head of the apparatus-side downlink data.
P), and a CLK synchronized with the downlink data is supplied. The user who performs the loopback is specified by loop information indicating the start position of the TS used by the user and the number of used TSs, and is input asynchronously.

In normal times (when loopback is not performed), the selector 3 selects uplink data from the line side and outputs it to the apparatus side.

The operation at the time of executing the loopback is to control the writing / reading of the loop buffer 2 by the write / read control signal of the buffer control unit 1, and the downlink data written in the buffer 2 is based on the loop information. The number of TSs used by the users in the loop is read out, selected by the selector 3, and looped back to the device-side uplink data.

Next, a detailed configuration of the buffer control unit 1 will be described. FIG. 3 is a block diagram showing details of the buffer control unit 1 in FIG. 2 of the present invention. The clock signal on the device side is supplied to each of the counters 4, 7, 8 as counter timing.

The counter 4 latches a write address of the buffer 2 (FIG. 2) and loop information (head TS value, number of used TS) indicating the number of used TSs with reference to the frame pulse FP indicating the start point of the return. Therefore, a predetermined update timing d of the downlink TS and an uplink T
An update timing f of S and a load timing e of the counter 8 are generated. The first-in / first-out memory (first-in first-out memory) F / F5 holds loop information (leading TS value) based on the downlink TS latch timing d generated by the counter 4. F / F6 is a counter 4
The loop information (the leading TS value and the number of used TSs) is held based on the uplink TS latch timing f generated in (1). The counter 7 uses the F / F 5 to hold the loop information (top T
The operation is started with the S value) as the load value. Also, it counts up when the enable generated by the comparison circuit 9 is valid,
A read address b for the buffer 2 (FIG. 2) is generated.

The counter 8 operates the counter at the load timing e generated by the counter 4 and
Output the counter value. The comparison circuit 9 includes a counter 8
Is compared with the leading TS value of the loop information held by the F / F 6, and from the time when the values match, the selection signal c of the selector 3 (FIG. 2) and the counter 7 up to the number of used TS. Generate enable for

As described above, the buffer control unit 1 shown in FIG. 2 performs the frame pulse FP, the clock CLK, the leading TS value and the used T
The number of S loop information is input, an address serving as a control signal for storing data to be looped back into the small-capacity buffer 2 for loopback is specified, and the selector 3 selects data to be read from the buffer 2. By outputting the signal, a synchronized loopback test or the like can be executed without conflict with uplink data.

(2) Description of Operation Hereinafter, the operation of the loopback control device according to the present embodiment will be described with reference to the detailed block diagram of FIG. 3 and the timing diagram of FIG. Loop information indicating the user who executes the loopback (the first TS value) is set by asynchronous control (FIG. 4A).

In this loop information, downlink data and uplink data on the device side are monitored. When the loop information shown in FIG. 4A is changed from n to m, the downlink loop information (E) becomes Frame pulse FP of next down frame phase
At the time, the loop information n is changed from m to m, and the upstream loop information (K) is changed from the loop information n to m at the end of the data return period. Depending on F
/ F5 and F / F6 are latched.

The counter 4 inputs CLK and FP, and starts counting when the frame pulse FP shown in FIG. 4B is input, and starts counting down from the beginning of the downstream frame shown in FIG. (FIG. 4C) is stored in a buffer (FIG. 2C).
(2) Outputs the address to be written to.

Further, the downlink TS update timing d (FIG. 4D) for latching the downlink loop information (head TS value) at the F / F5, and the uplink loop information (head T) at the F / F6.
S, the uplink TS update timing f (FIG. 4 (J)) for latching the number of used TSs is output.

Further, the counter 4 generates a timing e indicating the head of the upstream data, and uses it as the load timing of the counter 8.

On the other hand, the F / F 5 holds the leading TS indicating the user in the loop according to the downlink TS update timing d (FIG. 4D) generated by the counter 4 and updates the load value of the counter 7. Output. F / F6 is a counter 4
4, the uplink TS update timing f (FIG. 4)
According to (J)), the comparison circuit 9 generates the selection signal and the first TS indicating the user in the loop and the used TS.
Keep the number.

The counter 7 determines the initial value of the counter at the first TS (FIG. 4 (E)) indicating the user in the loop held by the F / F 5, and when the enable generated by the comparison circuit 9 is valid. Operates In other words, in uplink data,
At the TS position output by the user in the loop, the downstream loop data outputs the written address and reads the data from the buffer (FIG. 2 (2)).

The counter 8 operates at a timing indicating the head of the uplink data generated by the counter 4. The comparison circuit 9 compares the counter value generated by the counter 8 with the first TS (FIG. 4 (K)) indicating the user in the loop held by the F / F 6, and when the values match, the used TS is used. Until the selector (Fig. 2
While outputting the selection signal of (3)), an enable signal is output to the counter 7 (FIG. 4 (G)).

That is, when the loop information (FIG. 4A) is changed from loop information n to m, first, the downlink data (FIG. 4D) is transmitted at the downlink TS update timing d (FIG. 4D).
The start TS of the user in the loop of (C)) is updated from the loop information n to m (E). At this time, while the start TS of the user in the up loop remains the loop information n, the updated loop user data of the down data is read out at the position of TS n where the output of the up data loop user starts. Thereafter, at the uplink TS update timing f, the uplink TS
Is updated from the loop information n to m (K), and at the position of TSm where the output of the uplink data from the loop user is started,
By reading the updated downlink data of the loop user of the downlink data, it is possible to return the downlink data to the uplink data even if the start TS of the user in the loop is changed.

In FIG. 4, the hatched frame indicates the position of the user in the loop according to the loop information n, and the cross frame indicates the position of the user in the loop according to the loop information m.

Therefore, after the loop information is changed from n to m (A), the downstream loop information (E) is updated from n to m, and then the upstream loop information (K) is updated from n to m. Until ((α) shown in FIG. 4), the data read from the buffer 2 by the downstream loop information (E) m is inserted into the position of the upstream loop information (K) n so that the downstream data is It is possible to loop back without losing the uplink data.

In the above embodiment, the time from when the downlink loop information (E) is updated from n to m to when the uplink loop information (K) is updated from n to m (see FIG. 4 (α )) No buffer capacity is required. Therefore,
The storage capacity of the buffer 2 can be small, and the loop back can be executed with a simple configuration by the loop control circuit of the present invention.

Further, the selection of the selector 3 wraps only the data of the user who is executing the loop in the frame of the downlink data, so that the continuity of the wrapped data can be maintained. This does not adversely affect users other than the loop execution.

Further, the buffer 2 does not need to have a capacity corresponding to the phase difference between the downlink / uplink TS update timings ((α) shown in FIG. 4), and the delay amount of the return downlink data does not increase. .

Note that the present configuration can be used even if the phase difference of the TS update timing indicating the downlink / uplink loop user is an arbitrary value. Further, in the above-described embodiment, an example of the loopback on the device side has been described. However, it is also possible to use the loopback of the line-side uplink data to the line-side downlink data.

[0043]

As described above, even when the user's time slot TS is changed by the asynchronous control during the loopback test for each user, the small-capacity buffer is provided and the writing / reading of the buffer is controlled. This makes it possible to maintain the continuity of the return data.
Also, the phase difference between the downlink and uplink TS update timing (FIG. 4)
(Α)) By providing a buffer for the number of the return TSs of the user during the minutes, a circuit configuration for maintaining the continuity of the return data can be realized. By implementing the control of the present invention, the buffer amount can be reduced. In addition, the amount of delay can be reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a conceptual signal folding method of a loop control circuit of the present invention.

FIG. 2 is a conceptual block diagram of a loop back of the loop control circuit of the present invention.

FIG. 3 is a block diagram of a buffer control unit of the loop control circuit according to the present invention.

FIG. 4 is a timing chart of the loop control circuit of the present invention.

FIG. 5 is a timing chart of a conventional loop control circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Buffer control part 2 Buffer 3 Selector 4 Counter 5, 6 F / F 7, 8 Counter 9 Comparator

──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Kenichi Hashimoto 1-403 Kosugi-cho, Nakahara-ku, Kawasaki-shi, Kanagawa Pref. Kaihei 11-27341 (JP, A) (58) Field surveyed (Int. Cl. ⁷ , DB name) H04L 12/437

Claims (8)

(57) [Claims] 1. A loop control circuit for looping back downlink data over uplink data, comprising: a frame including a plurality of time slots; a frame pulse for generating a frame pulse at a head position of the frame; A buffer control unit for inputting frame information with a required number of time slots following the start time slot of original data added to the return data and a required number of subsequent time slots, and writing from the buffer control unit A buffer for writing and reading the return data in response to an address and a read address;
A selector for selecting any of the original data and the return data according to a selection control signal of the buffer control unit; and transmitting the return data from the original data to the frame pulse according to the frame information. A loop control circuit characterized by looping back in synchronization with a loop. And a buffer control unit that receives the frame pulse and latches the time slot of the return data, a data timing from the source that latches the time slot of the original data, and a load control unit. A timing counter for outputting a timing, a return F / F for storing a leading time slot of the return data according to the return timing and a required number of subsequent time slots, and a return F / F corresponding to the original data timing. An original F / F that stores the start time slot of the original data and the number of necessary time slots following it, a selection counter that counts a clock according to the load timing, and A read counter for counting the clock; The output of the counter and the F /
2. The comparator according to claim 1, further comprising: a comparator for comparing an output of the first data with the output of the first data, wherein a selector for selecting one of the original data and the folded data is controlled by the output of the comparator. Loop control circuit. 3. The method according to claim 2, wherein the count of the read counter is reset by an output of the comparator, the buffer writes the return data by a write address from the timing counter, and reads by a read address from the read counter. The loop control circuit according to claim 2, wherein 4. When the selector selects one of the original data and the return data, the selector selects the return frame in the frame information from the buffer control unit and the return data in the original data. 4. The loop control circuit according to claim 1, wherein the loop-back data is selected in synchronization with a frame pulse of the original frame among frames. 5. The method according to claim 1, wherein the selector sets a required number of time slots following the first time slot of the loopback data as a loopback time slot of the loopback data,
5. The method according to claim 1, wherein the original data is selected after the return time slot is returned.
The loop control circuit according to claim 1. 6. A loopback control device comprising: a buffer for temporarily recording downlink data; and a buffer control unit for controlling the buffer, wherein the loopback control device loops back the downlink data of a frame data structure including a plurality of slots so as to overlap with the uplink data. The buffer control unit that loops back the downlink data generates a frame pulse at the head position of the frame data, and inputs frame information including a head time slot of the downlink data to be looped back and a required number of subsequent time slots, A buffer control unit that generates a write address for writing the return data and a read address for reading from the frame pulse and controls the buffer for writing and reading the return data; and a selection control signal of the buffer control unit. , The uplink data and the turn-back below A selector for selecting one of the data according to the frame data, loopback control apparatus characterized by folding the said folded data from the uplink data in synchronism with the frame pulse. 7. The loopback control device according to claim 6, wherein the buffer control unit receives downlink and uplink loop information from a higher-level control system, and after the downlink loop information is changed, the buffer controller. A loopback control device, wherein data read from the buffer according to the downstream loop information is inserted into the position of the upstream loop information until the loop information is updated. 8. The loopback control device according to claim 6, wherein the storage capacity of the buffer is a capacity of downlink data inserted into the uplink data.