JP3347650B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor integrated circuit capable of operating at a low voltage, and an M method suitable for the method of use and the method of manufacture.
The present invention relates to an OS transistor (that is, a MOSFET) and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, high integration of semiconductor devices (that is, L
With the development of SI, it is desired to realize a semiconductor device which operates at a low driving voltage and consumes less power.

However, in order for the semiconductor device to operate at a low drive voltage, the channel region of the semiconductor device must be turned on.
Threshold value (ie, thr
A semiconductor device having a low (e.g., threshold voltage) Vth is required, but in a normal semiconductor device, when the threshold value Vth is lowered, a leak current flows between the source and the drain even when no gate voltage is applied. There was a technical challenge.

In order to solve such a technical problem, the depth of the well region below the gate electrode is reduced to reduce the reverse bias capacitance (unit: [C]) between the semiconductor substrate and the well region and the channel. The prior art for electrically coupling the depletion layer capacitance (unit: [C]) of the region and realizing a high-speed response characteristic of the drain current with respect to the application of the gate voltage,
Japanese Patent Application Laid-Open No. 5-21730 (Title of Invention: Semiconductor device and method of using the same, Applicant: Toshiba Corporation, Filing date:
July 15, 1991, hereinafter abbreviated as the first prior art) or US Pat. No. 5,489,795 (Title of Invention: SEMICONDUC)
TOR INTEGRATEDCIRCUIT DEVICE HAVING DOUBLE WELL ST
RUCTURE, Applicant: Kabushiki Kaisha Toshiba, Filing date: Oct. 4, 1994, hereinafter abbreviated as the second prior art).

FIG. 12 is a cross-sectional view for explaining a semiconductor device according to the first prior art.

In the semiconductor device of the first prior art, a diffusion region (that is, a well region 4A) having a depth of 1.5 μm or less from the surface of the semiconductor substrate 5A is formed in a surface region of the semiconductor substrate 5A. The MO is formed in the diffusion region 4A.
An S transistor was provided.

In the MOS transistor having such a configuration, by reducing the depth of well region 4A, the reverse bias capacitance between semiconductor substrate 5A and well region 4A and the depletion layer capacitance of the channel region (in the gate electrode 1A). (A depletion layer capacitance that can be controlled by an applied gate voltage). Based on this, a technique for obtaining a large drain current flowing between the source 3A and the drain 2A has been disclosed.

FIG. 13 is a sectional view for explaining a semiconductor device according to the second prior art.

In the semiconductor device of the second prior art, a well region 4B is formed in a surface region of a semiconductor substrate 5B, and a drain 2B, a source 3B,
A MOS transistor having a gate 1B was provided.

In the MOS transistor having such a configuration, the depth of the well region 4B below the channel region is set to be smaller than the depth of the well region 4B below the source 3B and the drain 2B. A technique has been disclosed that realizes a high-speed response characteristic of a drain current with respect to application of a gate voltage by electrically coupling a reverse bias capacitance between the regions 4B and a depletion layer capacitance of a channel region.

[0011]

However, in any of the semiconductor devices disclosed in the first prior art and the second prior art, the distance between the drain and the semiconductor substrate is short, so that the gate electrode is not connected to the gate electrode. Even when no voltage is applied, there is a technical problem that a current flows through the semiconductor substrate when a voltage is applied to the drain. As a result, there is a technical problem that the standby current is increased.

An object of the present invention is to solve such a conventional problem. In particular, an antipolar region having a conductivity type opposite to the conductivity type of a well region is surrounded by the well region. The second depletion layer region, which is provided below the gate channel region in a state and is a depletion layer region generated by the junction of the opposite polarity region and the well region, is connected to the first depletion layer region controlled by the gate voltage applied to the gate electrode. It is an object to realize a high-speed response characteristic of a drain current to the application of a gate voltage by controlling a gate voltage applied to a gate electrode so as to be formed near a channel region to be coupled.

Further, by adopting a device structure in which the distance between the drain and the semiconductor substrate is kept long, even if the gate voltage is applied and the voltage is applied to the drain, the leakage current is reduced. It is also an object to prevent the current from flowing to the device and to reduce the standby current.

[0014]

According to the first aspect of the present invention , a channel region is formed before a gate oxide film is formed.
A step of previously forming an E le 19, the channel region weblog
On le 19, forming a gate oxide film 18, the
Step of forming gate electrode 13 on gate oxide film 18
And after the formation of the gate electrode 13, the gate electrode 13
The channel region well with respect to the surface provided with
When p is a p-type, a p-type impurity is added to the channel region.
If the well 19 is n-type, an n-type impurity is implanted obliquely.
The well region and the well region
Provided below the gate channel region in a state surrounded by
And a conduction type opposite to the conduction type of the well region.
Forming a semi -polar region that changes
It is a manufacturing method of a body device.

According to a second aspect of the present invention, a step of forming a field oxide film 17 on an n-type silicon semiconductor region having a predetermined concentration and, after a previous step, p-type impurities with a predetermined acceleration energy and a predetermined ion concentration are performed. Perform ion implantation and p
Forming a switch Yaneru region well 19 of the mold, after the previous step, a gate oxide film 18 and forming a predetermined thickness by thermal oxidation treatment, after forming the n-type polysilicon film by a predetermined thickness and forming the gate electrode 13 is etched according to the shape of the gate electrode 13, after the previous steps, a source region 152 and the n-type impurity perform ion implantation at a predetermined acceleration energy and a predetermined ion concentration or forming an n-type low-concentration impurity diffusion region of the drain region 154, after the previous step, by performing oblique Me ion implantation of p-type impurity at a predetermined acceleration energy and a predetermined ion concentration weblog
Region 15 and a state surrounded by the well region 15
And provided below the gate channel region, and
Opposite polarity territory with E conductivity Den type Le region 15 and opposition conductive heat transfer-type
After forming the region 156 and after the previous process,
After forming an oxide film to a predetermined thickness, a step of forming a sidewall by performing an etch-back process, and after a previous process, performing ion implantation of an n-type impurity at a predetermined acceleration energy and a predetermined ion concentration to perform a source a method of manufacturing a semiconductor device which comprises a step of forming an n-type high concentration impurity diffusion regions of a region 152 and a drain region 154.

According to a third aspect of the present invention, the well region 15 is provided.
An opposite region 156 having a conductivity type opposite to that of the
A gate channel region surrounded by the well region 15
A method of manufacturing a semiconductor device provided below a second well region 24 and a channel region well, which are deep regions of the well region 15 before the gate electrode 13 is formed.
19 , the first well region 15 which is a shallow region in the well region 15 after the formation of the gate electrode 13, and the well region 15 are formed. A method of manufacturing a semiconductor device, comprising forming the antipolar region 156 having an opposite conductivity type and surrounded by the well region.

According to a fourth aspect of the present invention, prior to the formation of the gate electrode 13, an n-type impurity is ion-implanted at a predetermined acceleration energy and a predetermined ion concentration to form the second well region 2 below the field region in advance. Forming, after the previous step, forming the gate electrode 13, and after the previous step, ion-implanting the same n-type impurity as the second well region 24 with a predetermined acceleration energy and a predetermined ion concentration. 4. The method according to claim 3 , further comprising the step of forming the first well region to leave the opposite polarity region 156 only below the channel region.

According to a fifth aspect of the present invention, a step of forming a field oxide film on a p-type silicon semiconductor region having a predetermined concentration and, after the previous step, n-type impurities are ionized with a predetermined acceleration energy and a predetermined ion concentration. Performing an implantation to form an n-type channel region well;
Forming a predetermined film thickness of the gate oxide film by thermal oxidation treatment, after forming the p-type polysilicon film by a predetermined thickness, it is etched to form the gate electrode in accordance with the shape of the Gate electrode A step of performing p-type impurity ion implantation at a predetermined acceleration energy and a predetermined ion concentration to form a p-type low concentration impurity diffusion region of a source region or a drain region after the pre-process; the n-type impurity by performing oblique Me ion implantation at a predetermined acceleration energy and a predetermined ion concentration well region, and, enclosed in the well region
Provided below the gate channel region
A counter having a conductivity type opposite to the conductivity type of the well region;
High temperature CVD after the step of forming a polar region and the previous step
After forming an oxide film to a predetermined thickness, a step of forming a sidewall by performing an etch-back process, and after a previous process, performing ion implantation of a p-type impurity at a predetermined acceleration energy and a predetermined ion concentration to perform source implantation. a method of manufacturing a semiconductor device which comprises a step of forming a p-type high concentration impurity diffusion region of the region or the drain region.

[0019] The invention according to claim 6 is the invention according to claims 1-5.
A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of the preceding claims.

The conduction type of the present invention means a p-type or n-type semiconductor.

[0021] According to the invention described in claims 1 to 6, it becomes possible to lower the threshold (threshold voltage) Vth to the ON state or OFF state channel region, a low Semiconductor device 1 with drive voltage
0 can be operated.

As a result, it is suitable for high integration (LSI),
There is an effect that the semiconductor device 10 which operates at a low drive voltage and consumes less power can be realized.

Furthermore, a device structure in which the distance between the drain and the semiconductor substrate 11 is kept long without increasing the number of masks or the number of lithography used in the device manufacturing process can be obtained. Even in a state where a gate voltage is applied and a voltage is applied to the drain, a standby current (a current flowing in the device during standby when no gate voltage is applied) is avoided by preventing a leak current from flowing to the semiconductor substrate 11. Current) can be reduced.

Further, high-speed response characteristics (specifically, switching characteristics such as turn-on and turn-off) of a drain current with respect to application of a gate voltage can be realized without increasing the number of masks and the number of times of lithography used in a device manufacturing process. It has the effect of being able to do so.

According to the first aspect of the present invention, in addition to the above effects,
According to this, since the oblique ion implantation technique conventionally used is used, the distance between the drain and the semiconductor substrate 11 can be kept long without increasing the number of masks and the number of lithography used in the device manufacturing process. This has an effect that a device structure that can be manufactured can be easily manufactured with a high yield.

According to the third and fourth aspects of the present invention , in addition to the above effects.
According to the invention, the second depletion layer region is formed near the channel region sandwiched between the second well region 24 and the first well region by using the step of forming the second well region 24 and the step of forming the first well region. The formation of 14 produces an effect that a high-speed response characteristic of the drain current to the application of the gate voltage can be realized.

Further, in forming such a second depletion layer region 14, there is an effect that the device manufacturing process can be prevented from becoming complicated without increasing the number of masks and the number of times of lithography used in the device manufacturing process. Play.

[0028]

Embodiments of the present invention will be described below with reference to the drawings.

The semiconductor device 10 according to the present embodiment is a semiconductor integrated circuit capable of operating at a low voltage, and a MOS transistor (MOSFET) suitable for the method of use and the method of manufacture.
It is.

FIG. 1 is a cross-sectional view for explaining a basic configuration of a MOSFET 10 according to this embodiment.

As shown in FIG. 1, a well region 15 is formed in a surface region of a semiconductor substrate 11.
5 is characterized in that a MOSFET 10 having a drain region 154, a source region 152, and a gate electrode 13 is formed.

In such a MOSFET 10,
As shown in FIG. 1, an antipolar region 156 having a conductivity type opposite to that of the well region 15 is provided below the gate channel region in a state surrounded by the well region 15.

Here, the conduction type means a p-type or n-type in a semiconductor. The p-type semiconductor is a p-type semiconductor, and the n-type semiconductor is an n-type semiconductor.

Specifically, an n-channel MOSFET 1
0, the gate channel region is p-type,
The conductivity type of the well region 15 is set to p-type, and the conductivity type of the antipolar region 156 is set to n-type. For the same purpose, when fabricating a p-channel MOSFET 10, the gate channel region is set to n-type, the conduction type of well region 15 is set to n-type, and the conduction type of antipolar region 156 is set to p-type. .

The opposite polarity region 156 and the well region 15
A second depletion layer region 14 which is a depletion layer region generated by the junction of the first and second depletion layer regions is located near a channel region coupled to the first depletion layer region 12 governed (ie, controlled) by the gate voltage applied to the gate electrode 13. Is formed.

As described above, by forming the second depletion layer region 14 near the channel region, there is an effect that a high-speed response characteristic of the drain current to the application of the gate voltage can be realized.

Further, when such a second depletion layer region 14 is formed, it is possible to avoid the complexity of the device manufacturing process without increasing the number of masks and the number of lithography used in the device manufacturing process. Play.

Further, the opposite polarity region 156 is the opposite polarity region 1
The depth d of the uppermost surface of the gate electrode 56 is 0.5 μm or less from the lowermost surface of the gate electrode 13.

As described above, by forming the second depletion layer region 14 near the channel region (that is, depth d ≦ 0.5 μm), a high-speed response characteristic of the drain current to the application of the gate voltage can be realized. It has the effect of becoming

Further, when such a second depletion layer region 14 is formed in the vicinity of the channel region (that is, depth d ≦ 0.5 μm), the number of masks and the number of lithography used in the device manufacturing process are increased. Without complicating the device manufacturing process.

Further, in the method of using MOSFET 10 shown in FIG. 1, the gate voltage applied to gate electrode 13 is controlled such that first depletion layer region 12 and second depletion layer region 14 are coupled.

As described above, the MOS of the present embodiment
According to the FET 10, the channel region is turned on or the channel region is turned off.
Threshold for F state (threshold voltage)
Vth can be reduced, and as a result, it is possible to operate the MOSFET 10 at a low drive voltage.

As a result, it is suitable for high integration (LSI).
MOS operating at low drive voltage and low power consumption
There is an effect that the FET 10 can be realized.

Further, the device structure in which the distance between the drain and the semiconductor substrate 11 can be maintained long without increasing the number of masks and the number of lithography used in the device manufacturing process can be achieved. Even when a voltage is applied and a voltage is applied to the drain, a standby current (a current flowing in the device during standby when no gate voltage is applied) is avoided by preventing a leak current from flowing to the semiconductor substrate 11. ) Can be reduced.

Further, high-speed response characteristics (specifically, switching characteristics such as turn-on and turn-off) of the drain current with respect to the application of the gate voltage can be realized without increasing the number of masks and the number of lithography used in the device manufacturing process. It has the effect of being able to do so.

Next, based on the drawings, the MOSFET shown in FIG.
Various embodiments of the ten manufacturing methods will be described.

FIGS. 2A to 2D are process diagrams for explaining a first embodiment of the manufacturing method of the present invention.

The present manufacturing method is characterized in that after the gate electrode 13 is formed, the well region 15 and the opposite polarity region 156 surrounded by the well region 15 are formed by oblique ion implantation using impurities. Have.

Since the conventional oblique ion implantation technique is used, the distance between the drain and the semiconductor substrate 11 can be increased without increasing the number of masks and the number of lithography used in the device manufacturing process. There is an effect that a device structure that can be maintained can be easily manufactured with a high yield.

More specifically, a step of forming a field oxide film 17 on an N-type silicon semiconductor region having a predetermined concentration and, after the previous step, p-type impurities are ion-implanted at a predetermined acceleration energy and a predetermined ion concentration. a step of forming a p-type channel region, a step of forming a gate oxide film 18 to a predetermined thickness by a thermal oxidation process after the previous step,
After forming an N-type polysilicon film to a predetermined thickness, the gate electrode 1 is etched according to the shape of the gate electrode 13.
After the step of forming 3 and the previous step, N-type impurities are ion-implanted with a predetermined acceleration energy and a predetermined ion concentration to form an N-type low-concentration impurity diffusion region n ⁻ of the source region 152 or the drain region 154. A step of performing oblique ion implantation of a p-type impurity at a predetermined acceleration energy and a predetermined ion concentration from an incident angle of 45 ° to form a well region 15 and an antipolar region 156 after the pre-process; After forming a high-temperature CVD oxide film by a predetermined thickness, a step of forming a sidewall by performing an etch-back process and, after the previous step, performing ion implantation of N-type impurities at a predetermined acceleration energy and a predetermined ion concentration. Forming the N-type high-concentration impurity diffusion region n 2 of the source region 152 or the drain region 154.

More specifically, a manufacturing process for forming a field oxide film 17 on an n-type semiconductor substrate 11 having an ion concentration of 1.6 × 10 ¹⁶ cm ^-3 is performed.

Subsequently, as shown in FIG. 2A, in order to form a p-type channel region (channel dope region 19), boron as a p-type impurity is doped with 10 KeV, 4 × 10 ¹²
After ion implantation at cm ⁻² , a manufacturing process is performed in which the gate oxide film 18 is formed to 8 nm by thermal oxidation.

Subsequently, as shown in FIG. 2B, after an N-type polysilicon film 13 is formed to a thickness of 200 nm and etched into a gate shape, the n ⁻ region 192 (of the source region 152 / drain region 154) is formed. In order to form an n-type low concentration impurity diffusion region, phosphorus as an n-type impurity is
V, a manufacturing process of ion implantation at 2 × 10 ¹³ cm ⁻² is performed.

Subsequently, as shown in FIG. 2C, in order to form the antipolar region 156 (P), boron as a p-type impurity is added at 50 KeV, 1 × 10 ¹³ cm ⁻² ,
A manufacturing process is performed in which ions are implanted at an incident angle of 45 °.

Subsequently, as shown in FIG.
After a VD oxide film is formed to a thickness of 200 nm, an etch-back process is performed, and a sidewall 21 of the MOSFET 10 (MOSFET) is formed, and then an n region of the source region 152 / drain region 154 (that is, an n-type high-concentration impurity diffusion region) is formed.
Arsenic, which is an n-type impurity, is formed at 15 KeV, 6 ×
A manufacturing process is performed in which ions are implanted at 10 ¹⁵ cm ^-2 .

FIGS. 3A and 3B are process diagrams for explaining a second embodiment of the manufacturing method of the present invention. The same portions as those already described in the first embodiment of the manufacturing method are denoted by the same reference numerals, and redundant description will be omitted.

In the present manufacturing method, after the gate electrode 13 is formed, an impurity having a conductivity type opposite to that of the well region 15 is implanted through the gate electrode 13 by ion implantation.
It is characterized in that an antipolar region 156 surrounded by the well region 15 is formed.

As described above, by forming the second depletion layer region 14 near the channel region surrounded by the well region 15, it is possible to realize a high-speed response characteristic of the drain current to the application of the gate voltage. It works.

Further, in forming such a second depletion layer region 14, it is possible to avoid an increase in the number of masks and the number of lithography used in the device manufacturing process, and to avoid an increase in the complexity of the device manufacturing process. Play.

More specifically, a step of forming the well region 15 before forming the gate electrode 13 and a step of forming an n-type low-concentration impurity diffusion region n ⁻ of the source region 152 or the drain region 154 after the previous step. And a step of forming an antipolar region 156 by ion implantation of an n-type impurity having a conductivity type opposite to that of the well region 15 at a predetermined acceleration energy and a predetermined ion concentration after the previous step. have.

More specifically, as shown in FIG. 3A, a manufacturing process is performed in which a well region 15 is formed in advance before the gate electrode 13 is formed, and an n ⁻ region 192 of the source region 152 / drain region 154 is formed. are doing.

Subsequently, as shown in FIG. 3B, a manufacturing process for forming the antipolar region 156 (P) by ion implantation is performed.

FIGS. 4A to 4C are process diagrams for explaining a third embodiment of the manufacturing method of the present invention. Note that the same parts as those already described in the first embodiment or the second embodiment of the manufacturing method are denoted by the same reference numerals, and redundant description will be omitted.

In the present manufacturing method, the second well region 24 which is a deep region in the well region 15 is formed before the gate electrode 13 is formed, and the first well region which is a shallow region in the well region 15 is formed after the gate electrode 13 is formed. By forming the well region 15 to form the well region 15, the well region 1 has a conductivity type opposite to the conductivity type of the well region 15.
It is characterized in that an anti-polar region 156 surrounded by 5 is formed.

As described above, using the step of forming the second well region 24 and the step of forming the first well region, the second depletion layer is formed near the channel region sandwiched between the second well region 24 and the first well region. By forming the region 14, there is an effect that a high-speed response characteristic of the drain current to the application of the gate voltage can be realized.

Further, in forming such a second depletion layer region 14, it is possible to avoid an increase in the number of masks and the number of lithography used in the device manufacturing process, and to avoid an increase in the complexity of the device manufacturing process. Play.

More specifically, before the gate electrode 13 is formed, an n-type impurity is ion-implanted at a predetermined acceleration energy and a predetermined ion concentration to form the second well region 24 below the field region in advance, and Forming the first well region by ion-implanting the same n-type impurity as in the second well region 24 with a predetermined acceleration energy and a predetermined ion concentration after the step of forming the gate electrode 13 and the previous step. And a step of leaving the antipolar region 156 only below the channel region.

Specifically, as shown in FIG. 4A, before the gate electrode 13 is formed, the deep well region 15 (second well region 24) and the channel region 19 are ion-implanted below the field region 17 in advance. Is performed.

Subsequently, as shown in FIG. 4B, after the gate electrode 13 is formed, the low concentration source region 1 is formed by ion implantation.
52, a drain region 154 is formed.

Subsequently, as shown in FIG. 4C, a shallow well region 15 (first well region) is formed by ion implantation, and a source region 152 and a drain region 154 are formed by another ion implantation. The manufacturing process is performed to leave the antipolar region 156 (P) only in the lower part of the parentheses.

Finally, the MO fabricated by the above-described method is used.
SFET10 and MOSFET3 manufactured by conventional technology
The result of comparison with 0 and 31 will be described.

As Comparative Example 1, the above-mentioned US Pat.
In accordance with the fabrication method disclosed in No. 795, a MOSFET 30 was fabricated in which the depth of the well region 15 below the channel was made shallower than the depth of the well region 15 below the source / drain.

In order to form the antipolar region 156 (P), boron as a P-type impurity is added as an impurity having a conductivity type opposite to that of the well region 15 at 50 KeV, 1 ×.
Instead of the manufacturing process of this embodiment (see FIG. 2C) in which oblique ion implantation is performed at 10 13 cm −2 and an incident angle of 45 °, P
30 KeV, 1 × 10 ¹³ c
Ion implantation was performed under the conditions of m ⁻² and an incident angle of 0 °. Other manufacturing conditions were the same as in the first embodiment.

As a comparative example 2, a MOSFET 31 was formed according to a conventional manufacturing process. Manufacturing conditions are first
The oblique ion implantation process of the embodiment (see FIG. 2C)
In order to form a P-type channel region (channel dope region 19), boron as a P-type impurity is doped with 10 KeV, 4 ×
This was performed immediately after the manufacturing step of ion implantation under the manufacturing conditions of 10 @ 12 cm @ -2 (see FIG. 2A). At this time, the implantation condition of boron as a P-type impurity is 30 KeV, 1 × 10 ¹³
cm ^-2 and an incident angle of 0 °.

The MOSFET 30 formed by the above method,
High-speed response of gate voltage-drain current in the case where 1.5V is applied to the drain of 31 and the gate voltage and the voltage of the semiconductor substrate 11 are set to 0V, and the current of the semiconductor substrate 11 and the gate voltage are applied. The S factor (unit: [mV / decade]) obtained from the characteristics was measured.

The smaller the current of the semiconductor substrate 11, the better.
The smaller the factor is, the more steep the rising characteristics can be obtained.

In the MOSFET 10 of this embodiment, the current of the semiconductor substrate 11 was less than 1 pA and the S factor was 75. In the MOSFET 30 of Comparative Example 1, the semiconductor substrate 1
The current of 1 was 4 μA and the S factor was 75. In the MOSFET 31 of Comparative Example 2, the current of the semiconductor substrate 11 is 1
Below pA, the S factor was 85.

As can be seen from the comparison result, the M
In the OSFET 10, a small current of the semiconductor substrate 11 and a small S factor are simultaneously satisfied.

In other words, experiments were conducted to prevent the leakage current from flowing into the semiconductor substrate 11 to reduce the standby current and to simultaneously realize the high-speed response characteristics of the drain current to the application of the gate voltage. Proven by

Next, a fourth embodiment of the manufacturing method of the present invention will be described with reference to the drawings. The same parts as those already described in the first to third embodiments of the manufacturing method are denoted by the same reference numerals, and the duplicate description will be omitted.

FIG. 5 is a top view of the semiconductor device 1010 of FIG. In the following description, FIG.
(A) to FIG. 8 (c), and FIG. 10 (a), FIG.
(B), FIG. 11 (a) and FIG. 11 (b) show cross sections AA 'in FIG. It should be noted that the cross section taken along the line BB 'in FIG. 5 finally has the shape shown in FIG. 7B or 9C, and the opposite polarity region 156 is isolated from the adjacent MOS transistor.

FIGS. 6A to 6C are process diagrams for explaining the first half of the fourth embodiment of the manufacturing method of the present invention. FIGS. 7A to 7C are process diagrams for explaining a middle stage process following the first half process of the fourth embodiment shown in FIGS. 6A to 6C. 8 (a) to 8
7C is a process diagram for explaining a latter half process following the middle process of the fourth embodiment shown in FIGS. 7A to 7C. FIG.

First, the first step is performed, and as shown in FIG. 6A, an n-well region 15 and a p-well region are formed on a p-type semiconductor substrate having a concentration of 1.7 × 10 ¹⁴ cm ^−3. 15 are formed.

The n-well region 15 is formed by adding phosphorus at 160 KeV, 2
Perform ion implantation at × 10 ¹³ cm ^-2 ,
Formed by heat treatment for a minute.

Subsequently, as shown in FIG. 6B, boron is ion-implanted at 30 KeV and 2 × 10 ¹³ cm ^-2 ,
The p-well region 15 is formed by being diffused by a heat treatment at 1200 ° C. for 120 minutes.

Subsequently, a second step is performed to form a field oxide film 17 having a thickness of 400 nm by a thermal oxidation method.

Subsequently, a third step is performed. As shown in FIG. 6C, boron is ion-implanted at 30 KeV and 4 × 10 ¹² cm ⁻² to form an antipolar region 156 in the n-well region 15. Implantation is performed, and phosphorus is added at 30 KeV to form a channel portion of the p-channel MOS transistor.
Ion implantation is performed under an implantation condition of 2.8 × 10 ¹² cm ⁻² .

Subsequently, a fifth step is performed. As shown in FIG. 7A, in order to form an antipolar region 156 in the p-well region 15, phosphorus is ion-implanted at 100 KeV and 1 × 10 ¹³ cm ^-2 . Implantation is performed, and furthermore, boron is added at 10 KeV to form a channel portion of the n-channel MOS transistor.
Ion implantation is performed under an implantation condition of 9 × 10 ¹² cm ⁻² .

Subsequently, a fifth step is performed, and as shown in FIG. 7B, a gate oxide film 18 is formed to a thickness of 8 nm by thermal oxidation, and then a non-doped polysilicon film 13 is formed to a thickness of 200 nm.
Form a film.

Subsequently, a sixth step is performed, and as shown in FIG. 7C, arsenic is added to the non-doped polysilicon film 13 in the region to be the gate of the n-channel MOS transistor by 50K.
Ion implantation is performed under an implantation condition of eV and 5 × 10 ¹⁵ cm ⁻² . In addition, ion implantation is performed on the region boron serving as the gate of the p-channel MOS transistor under the conditions of 10 KeV and 5 × 10 ¹⁵ cm ⁻² . Thereafter, etching is performed in a gate shape.

Subsequently, a seventh step is performed, and as shown in FIG. 8A, a p-channel MOS transistor (pMOS)
To form a p ^- region 194 of a source region 152 or a drain region 154 of a region to be 10 KeV, 2 ×
Ion implantation is performed under an implantation condition of 10 ¹³ cm ^-2 . In order to form a shallower n-well region 15, arsenic is
V, ion implantation is performed under an implantation condition of 2 × 10 ¹³ cm ⁻² .

Then, as shown in FIG. 8B, arsenic is applied at 10 KeV and 2 × to form an n ⁻ region 192 of a source region 152 or a drain region 154 in a region to be an n-channel MOS transistor (nMOS). Ion implantation is performed under an implantation condition of 10 ¹³ cm ^-2 . Further shallow p-well region 15
For forming boron, 40 KeV, 1 × 10 ¹³ cm ⁻²
The ion implantation is performed under the implantation conditions described above.

Subsequently, an eighth step is performed, and as shown in FIG. 8C, a high-temperature CVD oxide film is formed to a thickness of 200 nm, and is etched back to form a sidewall film 21 of the MOS transistor. Then, the high impurity concentration source region 1
P-channel M for forming 52 or drain region 154
BF2 is 30 KeV, 5 × 10 ¹⁵ for the OS transistor.
cm ^-2 , 30 arsenic for n-channel MOS transistor
Ion implantation is performed under the implantation conditions of KeV and 5 × 10 ¹⁵ cm ⁻² .

A voltage of 1.5 V is applied to the drain of the MOS transistor prepared by the above-described manufacturing method, and a gate voltage, a semiconductor substrate current when the semiconductor substrate voltage is set to 0 V, and a gate voltage are applied. The S factor obtained from the gate voltage / drain current characteristics was measured.

As a result of the measurement, a value of 72 mV / decade was obtained for the n-channel MOS transistor and a value of 70 mV / decade was obtained for the p-channel MOS transistor.

Since the S factor of the ordinary MOS transistor is about 80 mV / decade, the p-channel MOS transistor and the n-channel MOS transistor simultaneously satisfy a small S factor in the CMOS transistor process.

Next, a fifth embodiment of the manufacturing method of the present invention will be described with reference to the drawings. The same parts as those already described in the first to fourth embodiments of the manufacturing method are denoted by the same reference numerals, and redundant description will be omitted.

FIGS. 9A to 9C are process diagrams for explaining the first half of the fifth embodiment. FIG.
(A) to FIG. 10 (d) show FIGS. 9 (a) to 9 (c).
FIG. 21 is a process diagram for describing a middle stage process following the first half process of the fifth embodiment shown in FIG. FIG. 11 is a process diagram for explaining the latter half process following the middle process of the fifth embodiment shown in FIGS. 10A to 10D. In the fourth embodiment, channel doping is performed immediately after ion implantation for forming the antipolar region 156. However, in the fifth embodiment, the concentration of the well region 15 and the concentration of the antipolar region 156 are appropriately adjusted. It is characterized in that it is adjusted.

Thus, the channel doping step can be omitted for both the n-channel MOS transistor and the p-channel MOS transistor.

FIGS. 9A to 9C show process flows corresponding to FIGS. 6C to 8 C described above.
This is shown in FIGS. 10 (a) and 10 (b) and FIG.

After the above-described second step, a third step is performed. As shown in FIG. 9A, in order to form an antipolar region 156 in the n-well region 15, boron is applied at 50 KeV.
Ion implantation is performed at 5 × 10 ¹² cm ⁻² , and phosphorus is implanted at 10 KeV and 1 × 10 ¹² cm ⁻² to form a channel portion of the p-channel MOS transistor.

Subsequently, a fifth step is performed. As shown in FIG. 9B, phosphorus is ion-implanted at 100 KeV and 1 × 10 ¹³ cm ^-2 to form an antipolar region 156 in the p-well region 15. Implantation is performed, and furthermore, boron is added at 10 KeV to form a channel portion of the n-channel MOS transistor.
Ion implantation is performed under an implantation condition of 9 × 10 ¹² cm ⁻² .

Subsequently, a fifth step is performed to form a gate oxide film 18 having a thickness of 8 nm by thermal oxidation as shown in FIG. 9C, and then a non-doped polysilicon film 13 having a thickness of 200 nm.
Form a film.

Subsequently, a sixth step is performed, and as shown in FIG. 10A, 50% of arsenic is added to the region of the non-doped polysilicon film 13 to be the gate of the n-channel MOS transistor.
Ion implantation is performed under the implantation conditions of KeV and 5 × 10 ¹⁵ cm ⁻² . In addition, ion implantation is performed on the region boron serving as the gate of the p-channel MOS transistor under the conditions of 10 KeV and 5 × 10 ¹⁵ cm ⁻² . Thereafter, etching is performed in a gate shape.

Subsequently, a seventh step is performed, and as shown in FIG. 10B, a p-channel MOS transistor (pMO
The source region 152 or the drain region 1 of the region to be S)
Boron is doped with 10 Ke to form a p ^- region 194 of 54.
V, ion implantation is performed under an implantation condition of 2 × 10 ¹³ cm ⁻² .
In order to form a shallow n-well region 15,
By performing ion implantation at KeV and 1 × 10 ¹³ cm ⁻² , a narrow antipolar region 156 can be formed in a region to be a p-channel MOS transistor.

Subsequently, as shown in FIG. 11, arsenic is applied at 10 KeV and 2 × 10 ¹³ cm to form the n ⁻ region 192 of the source region 152 or the drain region 154 in the region to be an n-channel MOS transistor (nMOS). Ion implantation is performed under ^-2 implantation conditions. Further, by performing ion implantation of boron at 40 KeV and 1 × 10 ¹³ cm ⁻² to form a shallow p-well region 15, a narrow antipolar region 156 can be formed in a region to be an n-channel MOS transistor.

Subsequently, an eighth step is performed, and as shown in FIG. 11, a high-temperature CVD oxide film is formed to a thickness of 200 nm, etch-back is performed, and the sidewall film 2 of the MOS transistor is formed.
Form one. Thereafter, the high impurity concentration source region 152
Alternatively, for forming the drain region 154, a p-channel MO
BF2 is 30 KeV, 5 × 10 ¹⁵ c for S transistor
Arsenic 30K for m ^-2 , n-channel MOS transistors
Ion implantation is performed under an implantation condition of eV and 5 × 10 ¹⁵ cm ⁻² .

When 1.5 V is applied to the drain of the MOS transistor prepared by the above-described manufacturing method, the gate voltage, the semiconductor substrate current when the semiconductor substrate voltage is set to 0 V, and the gate voltage are applied. The S factor obtained from the gate voltage / drain current characteristics was measured.

As a result of the measurement, a value of 72 mV / decade was obtained with the n-channel MOS transistor, and a value of 70 mV / decade was obtained with the p-channel MOS transistor.

Since the S factor of a normal MOS transistor is about 80 mV / decade, the p-channel MOS transistor and n in a CMOS transistor process are manufactured by the manufacturing method of the first to fifth embodiments.
A small S factor was satisfied simultaneously with the channel MOS transistor.

In order to enhance the isolation state of the opposite polarity region 156, the ion implantation into the opposite polarity region 156 is not performed on the entire field region of the MOS transistor but on the region inside the end of the field oxide film 17 as shown in FIG. It is also possible to reduce the influence of adjacent MOS transistors,
This is desirable when it is necessary to reduce the leakage current between the well regions 15.

In this embodiment, the ion implantation for forming the shallow well region 15 is performed when the low concentration source region 152 or the drain region 154 is implanted (formation of the n ⁻ region 192 or the p ⁻ region 194). However, even if the implantation into the shallow well region 15 is performed before and after the implantation of the high concentration source region 152 or the drain region 154 after the formation of the sidewall film 21 on the side surface of the gate electrode, the first to fifth embodiments are also applicable. Can be implemented.

[0113]

According to the first to sixth aspects of the present invention , the threshold value (threshold voltage) Vth for turning on or off the channel region can be reduced, and as a result, This has the effect that the semiconductor device can be operated at a low drive voltage.

As a result, it is suitable for high integration (LSI).
There is an effect that a semiconductor device which operates at a low drive voltage and consumes less power can be realized.

Furthermore, the gate voltage can be increased without increasing the number of masks used in the device manufacturing process or the number of lithography operations, thereby increasing the distance between the drain and the semiconductor substrate. Is applied, and even when a voltage is applied to the drain, a standby current (a current flowing in the device at a standby time when no gate voltage is applied) is prevented by preventing a leak current from flowing to the semiconductor substrate. This has the effect of being able to keep it low.

Further, high-speed response characteristics of drain current to gate voltage application (specifically, switching characteristics such as turn-on and turn-off) can be realized without increasing the number of masks and the number of lithography used in the device manufacturing process. It has the effect of being able to do so.

According to the second aspect of the present invention, in addition to the above-mentioned effects, since the oblique ion implantation technique conventionally used is used, the number of masks and the number of lithography used in the device manufacturing process can be reduced. There is an effect that a device structure that can keep the distance between the drain and the semiconductor substrate long without increasing the size can be easily manufactured with a high yield.

According to the third and fourth aspects of the present invention, in addition to the above effects, the second well region and the first well region are formed by using the second well region forming step and the first well region forming step. By forming the second depletion layer region in the vicinity of the channel region sandwiched between the regions, it is possible to achieve an effect that a high-speed response characteristic of the drain current to the application of the gate voltage can be realized.

In forming such a second depletion layer region, there is an effect that the device manufacturing process can be prevented from becoming complicated without increasing the number of masks and the number of lithography used in the device manufacturing process. .

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a basic configuration of a semiconductor device of the present invention.

FIGS. 2A to 2D are process diagrams for explaining a first embodiment of the manufacturing method of the present invention.

FIG. 3 (a) or FIG. 3 (b) is a process diagram for explaining a second embodiment of the manufacturing method of the present invention.

FIGS. 4A to 4C are process diagrams for explaining a third embodiment of the manufacturing method of the present invention.

FIG. 5 is a top view of the semiconductor device of FIG. 1;

FIGS. 6 (a) to 6 (c) are process diagrams for explaining the first half process of the fourth embodiment of the manufacturing method of the present invention.

FIGS. 7 (a) to 7 (c) are process diagrams for explaining a middle stage process following the first half process of the fourth embodiment shown in FIGS. 6 (a) to 6 (c). .

8 (a) to 8 (c) are process diagrams for explaining a latter half process following the middle process of the fourth embodiment shown in FIGS. 7 (a) to 7 (c). .

FIGS. 9A to 9C are process diagrams for explaining the first half process of the fifth embodiment.

FIGS. 10 (a) to 10 (d) show FIG.
FIG. 10 is a process diagram for explaining a middle stage process following the first half process of the fifth embodiment shown in FIGS. 9A to 9C.

FIG. 11 is a view showing a fifth example shown in FIGS. 10 (a) to 10 (d);
FIG. 9 is a process chart for explaining a latter half process following the middle process of the embodiment.

FIG. 12 is a cross-sectional view for explaining a semiconductor device according to the first related art.

FIG. 13 is a cross-sectional view for explaining a semiconductor device according to a second conventional technique.

[Explanation of symbols]

Reference Signs List 10 semiconductor device 11 semiconductor substrate 12 first depletion layer region 13 gate electrode 14 second depletion layer region 15 well region (p-well region, n-well region) 152 source region 154 drain region 156 Polar region 17 Field oxide film 18 Gate oxide film 19 Channel doped region 192 n ^- region 194 p ^- region 20 Resist pattern 21 Side wall 24 Second well region

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ identification code FI H01L 27/092 29/78 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 27/092 H01L 27/088 H01L 29/78 H01L 21/8238 H01L 21/8234 H01L 21/336

Claims (6)

(57) [Claims] A step of forming a channel region well before forming a gate oxide film; a step of forming a gate oxide film on the channel region well; and forming a gate electrode on the gate oxide film. Forming a p-type impurity on the surface on which the gate electrode is provided after the formation of the gate electrode, if the channel region well is p-type, and n if the channel region well is n-type. type impurity by oblique ion implantation, c
And E Le region provided below the gate channel region in a state surrounded by the well region, and a step of forming a counter-polarity region having a conductive heat transfer-type opposite conductivity Den type of the well region A method for manufacturing a semiconductor device, comprising: 2. A step of forming a field oxide film on an n-type silicon semiconductor region having a predetermined concentration, and after the previous step, ion-implanting a p-type impurity with a predetermined acceleration energy and a predetermined ion concentration to form a p-type impurity. A step of forming a channel region well; a step of forming a gate oxide film to a predetermined thickness by thermal oxidation after the previous step; and a step of forming an n-type polysilicon film to a predetermined thickness and forming a gate electrode. Forming the gate electrode by etching according to the following; and, after the previous step, performing ion implantation of an n-type impurity at a predetermined acceleration energy and a predetermined ion concentration to diffuse the n-type low-concentration impurity in the source region or the drain region. Forming a region, and after the pre-process, performing oblique ion implantation of a p-type impurity at a predetermined acceleration energy and a predetermined ion concentration to form a well region ;
Provided below the gate channel region in a state surrounded by the well region, and forming a opposite polarity region having a conductive heat transfer-type opposite conductivity Den type of the well region, after the previous step, After forming a high-temperature CVD oxide film by a predetermined thickness, a step of forming a sidewall by performing an etch-back process, and, after the previous process, performing ion implantation of an n-type impurity at a predetermined acceleration energy and a predetermined ion concentration. Forming an n-type high-concentration impurity diffusion region of a source region or a drain region by using the method described above. 3. A method for manufacturing a semiconductor device, comprising providing an opposite polarity region having a conductivity type opposite to a conductivity type of a well region below a gate channel region in a state surrounded by the well region. Forming a second well region and a channel region well which are deep regions in the well region before forming the electrode, and forming a first well region which is a shallow region in the well region after forming the gate electrode. A method of manufacturing a semiconductor device, comprising forming a well region to form the antipolar region having a conductivity type opposite to that of the well region and surrounded by the well region. 4. forming a second well region below a field region by ion-implanting an n-type impurity with a predetermined acceleration energy and a predetermined ion concentration before forming the gate electrode; Forming the first well region by ion-implanting the same n-type impurity as the second well region at a predetermined acceleration energy and a predetermined ion concentration after the step of forming the gate electrode; 4. The method according to claim 3 , further comprising the step of leaving the opposite polarity region only below the channel region. 5. A step of forming a field oxide film on a p-type silicon semiconductor region having a predetermined concentration, and after the previous step, ion-implanting an n-type impurity with a predetermined acceleration energy and a predetermined ion concentration to form an n-type impurity . forming a switch Yaneru area well, after the previous step, a step of forming a predetermined film thickness of the gate oxide film by thermal oxidation treatment, after forming the p-type polysilicon film by a predetermined thickness, gate Forming the gate electrode by etching according to the shape of the electrode; and performing p-type impurity ion implantation at a predetermined acceleration energy and a predetermined ion concentration by performing p-type impurity implantation at a source region or a drain region after the previous step. forming a doped impurity diffusion regions, before after step, the well region by performing oblique Me ion implanted n-type impurity at a predetermined acceleration energy and a predetermined ion concentration,及
And the gate channel region surrounded by the well region
And a conduction type of the well region.
A step of forming an opposite polarity region having an opposite conductivity type ; a step of forming a high-temperature CVD oxide film by a predetermined thickness after the previous step; and a step of performing an etch-back process to form a sidewall. Performing a p-type impurity ion implantation at a predetermined acceleration energy and a predetermined ion concentration to form a p-type high-concentration impurity diffusion region of a source region or a drain region after the step . Production method. 6. The semiconductor device according to claim 1, wherein:
Semiconductor produced by a method of manufacturing a device
Equipment .