JP3350866B2 - Memory test equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory test apparatus and, more particularly, to a read transfer function test for a memory device called a multiport DRAM or a dual port video RAM having a random access RAM section and a serial access SAM section. In a test in which data for one row address is transferred from the RAM unit to the SAM unit at one time, the transferred data is sequentially read from the SAM unit and compared with an expected value, a failure (failure) occurs. ,
The present invention relates to a memory test device configured to write data indicating a defect at the same address as the original address of the defective bit in the RAM unit in the sub-fail memory.

[0002]

2. Description of the Related Art A conventional memory test apparatus will be described with reference to FIGS. Memory under test (hereinafter also referred to as MUT)
As shown in FIG. 4, the multiport DRAM 2
A RAM unit 2a and a SAM unit 2b are provided. RA
The M section 2a has an address input terminal A and a control signal input terminal C
A TL and a data input / output terminal D are provided, and a clock input terminal CKS and a data input / output terminal D are provided in the SAM section 2b. RAM unit 2 for ease of explanation
a is, for example, a row address at addresses 0 to 255 and 0 to 255
Assuming that a column address of an address is provided, that is, M = N = 255 in FIG. 4, each of the row address signal and the column address signal has an 8-bit configuration. (A) Test of RAM section Main timing generating section 3a constituting timing generator 3
The timing signal is supplied from the sub timing generator 3b to the main pattern generator 4a and the sub pattern generator 4b constituting the pattern generator 4, respectively. The main pattern generator 4a generates a control signal, a test pattern TP, and an address signal MA for writing the test pattern in accordance with a command given from an instruction memory (not shown) in synchronization with the input timing signal.
It is supplied to the RAM unit 2a of the MUT 2. Address signal MA
Are sequentially taken into the RAM unit 2a as a set of a row address and a column address (this set is also referred to as a main address), and pattern data is written to and read from a memory cell selected by the main address.
Generally, a plurality of memory cells are provided at each address position so that a plurality of bits of data can be stored as one word, but one memory cell may be used. The read data is input to the main logic comparison unit 6a, and is compared with the expected value pattern EP input from the main pattern generation unit 4a. When a mismatch is detected at any bit in a word read from a certain address position, a main fail signal MF = "1" is immediately generated and input to the main failure analysis memory 7a. The main failure analysis memory 7a has the same memory space as the RAM unit 2a, and the same main address signal MA supplied to the RAM unit 2a is supplied to the address input terminal A. MF = "1" is written to the same address position as the original address (a set of the row address and the column address) in the RAM section 2a before the transfer of the included word.

A test pattern is sequentially written to all address areas of the RAM section 2a, a similar test is performed, and M is stored in the main failure analysis memory 7a in accordance with the generated failure bit.
F = "1" is written. (B) Read transfer test A row address of the RAM unit to be transferred at a time from the RAM unit 2a to the SAM unit 2b (referred to as a transfer row address).
Is supplied from the main pattern generation unit 4a to the RAM unit 2a, and a column address (SAM start address) indicating from which column address of the data transferred to the SAM unit 2b the serial reading of the data is started,
SA from the main pattern generation unit 4a via the RAM unit 2a
It is provided to the M section 2b. As shown in FIG.
All data of a certain row address transferred to b are read out serially from a designated column address (SAM start address), are sequentially output word by word, and are input to the sub-logic comparison unit 6b to generate a sub-pattern. Part 4
This is compared with the expected value pattern input from b. When a mismatch with the expected value pattern is detected in an arbitrary bit in the read word, the sub-fail signal SF = "1" immediately
Is generated (in the case of coincidence detection, SF = "0") and input to the sub-failure analysis memory 7b. Secondary failure analysis memory 7b
Has the same memory space as the RAM section 2a. SAM section 2b
A sub-address signal SA indicating which address (a set of row address and column address) of the RAM unit 2a where the output data is stored before the transfer is stored in the sub-failure analysis memory 7b from the sub-pattern generating unit 4b. The input and generated sub-fail signal SF = 1 is written to all the memory cells at the address position.

[0004]

The program for generating the sub-address signal SA to be supplied to the sub-failure analysis memory 7b in the above-described read transfer test from the sub-pattern generating section 4b is SA
The data read from the M unit 2b is created in consideration of which address of the RAM unit 2a is the data. In this case, it is necessary to create a program in consideration of the main address signal MA (transfer row address and SAM start address) of the main pattern generation unit 4a, and the problem that the amount of work required to create the program and to debug the program increases. there were.

By the way, in the latest multi-port DRAM, as shown in FIG.
When transferring data to the SAM section 2b, the SAM section 2b is divided into two address areas (for example, 0 to 127 and 128 to 255) at the center of the column address area, and a lower SAM 2b-L and an upper SAM 2b-U are formed. While sequentially outputting data already transferred from the corresponding column address area in the transfer row address of the RAM section 2a, the other alternately receives data transfer from the corresponding column address area in the transfer row address of the RAM section 2a. Split read transfer function (SAM during data output is active SAM, the other is inactive SAM)
) Has appeared. In this case, the lower S
The start addresses S1 and S2 given to the AM2b-L and the upper SAM2b-U respectively correspond to the main pattern generator 4
a to the SAM unit 2b via the RAM unit 2a. The data transferred to the lower SAM unit 2b-L is shown in FIG.
As shown by the arrow, the data is sequentially output from the start address S1 to the lower maximum address AM1 (= 127), and during that time, the data is transferred from the RAM unit 2a to the upper SAM 2b-U. Next, the start address S of the upper SAM 2b-U
7B from 2 to the uppermost address AM2 (= 255)
Are output to the outside in the order shown by the arrows.

In the latest multiport DRAM, when performing a split read transfer, the transfer destination from one of the lower SAM 2b-L and the upper SAM 2b-U to the other is determined by the set value (stop address) of the built-in stop register. Some have a stop register control function to switch between (FIG. 7C). In response to the complicated split read transfer operation in these latest multiport DRAMs, programming the sub-address signal SA to be supplied from the sub-pattern generating unit 4b to the sub-failure analysis memory 7b requires a large amount of work. It is also becoming more and more technically difficult.

An object of the present invention is to newly realize a sub address generator which can generate a sub address signal SA not by software but by hardware as in the prior art.
It is intended to solve conventional problems.

[0008]

According to the present invention, a timing signal is supplied from a timing generator to a main and sub pattern generator, and a test pattern, a control signal and a main address signal are randomly transmitted from the main pattern generator. An input is made to the RAM section of the memory under test having a RAM section for access and a SAM section for serial access, and a test pattern and a clock signal are inputted to the SAM section from the sub-pattern generating section. The read test pattern and the expected value pattern supplied from the main and sub-pattern generating units are compared by a main and sub-logic comparing unit, and when a mismatch is detected between them, a main and sub-fail signal is generated, and the RAM unit generates A memory test apparatus for writing data into main and sub failure analysis memories having the same memory space as Failure analysis memory having a memory and a secondary failure analysis memory providing the sub-address generator for generating a sub-address signal to be supplied to the sub failure analysis memory. The sub-address generator includes: a plurality of counters; a multiplexer for selecting one of the plurality of counters in a counting state and outputting the counted value as the sub-address signal to be supplied to the sub-failure analysis memory; Register means for setting data of a value corresponding to the size of the column address of the memory under test; and comparing at least a part of the output data of the multiplexer with at least a part of the data set in the register means. A comparison means for outputting a match detection signal when a match is detected, and each time the main address signal is supplied, the main address signal is set to one of the non-count states of the counter.
Each time data corresponding to the main address is sequentially output from the SAM unit, the loaded counter is incremented, and in response to a coincidence detection signal from the comparing means, the counter being counted is reset. Control means for stopping the increment and incrementing one of the counters to which a new main address signal is set each time data corresponding to the main address is sequentially output from the SAM unit. .

[0009]

1 to 3 show an embodiment of the present invention, and FIGS.
Parts corresponding to those in FIG. 5 are denoted by the same reference numerals, and redundant description will be omitted. In the present invention, a sub address generator 7c is provided in the failure analysis memory 7. In this example, the multiplexer 7d for selecting either the sub-address signal SA 'output from the sub-address generator 7c or the sub-address signal SA output from the sub-pattern generating unit 4b as required also includes a failure analysis memory 7. It is provided within. Sub address generator 7
A main address signal MA for transferring data from the RAM unit 2a to the SAM unit 2b and a main control signal CSa corresponding to the type of read transfer are supplied from the main pattern generation unit 4a to c. The types of read transfer include the simple read transfer shown in FIG. 6, the split read transfer shown in FIG. 7B, and the stop control split read transfer shown in FIG. 7C. Also S
A sub-control signal CSb corresponding to a data output command to the AM unit 2b is supplied from the sub-pattern generating unit 4b to the sub-address generator 7c.

The main address signal M input from the main pattern generator 4a to the address terminal A of the sub address generator 7c
A has a multiport D which is a memory under test (MUT).
In some RAMs, as shown in FIG. 3A, for example, an 8-bit row address signal is arranged in the LSB half, and an 8-bit column address (or SAM start address) signal is arranged in the MSB half. Things and Figure 3
As shown in row B, there is one in which the positions of the row address signal and the column address signal are arranged opposite to those of row A in FIG. Therefore, in the sub-address generator 7c, the address selector 11 is provided as shown in FIG. 2 so that the column address signal is always located at the half on the LSB side as shown in row C of FIG. Are rearranged as necessary.

The main address MA (16 bits) output from the address selector 11 is a select signal SL.
1 and SL2, the counter C1 as shown in FIG.
And C2 respectively. Counters C1, C2
Is the select signal SL input from the control unit 12
1, SL2 (for example, consisting of 2 bits). That is, the select signals SL1 and SL2 designate one of the load mode, the increment mode, and the hold mode for the counters C1 and C2, respectively. The multiplexer MUX selects either the output of the counter C1 or the output of the counter C2 according to the switching signal SL3 input from the control unit 12, and outputs it as the sub address signal SA '.

The control section 12 controls each section of the sub address generator 7c. In any transfer mode, the counter C1 (or C2) counts (active state).
, The other counter C2 (or C2) in the inactive state in response to the main control signal CSa corresponding to the transfer command given by the main pattern generation unit 4a to the RAM unit 2a.
Select signal SL2 (or SL1) indicating the load mode.
) To load the primary address. Further, the control unit 12
Is the sub-pattern generator 4b in any transfer mode.
Are clocks CK1 and CK for incrementing the count values of the counters C1 and C2 from the SAM start address on the basis of the sub control signal CSb from the sub pattern generator 4b corresponding to the data output command given to the SAM 2b.
Give 2 These clocks CK1 and CK2 are generated by the control unit 12 based on the clock CKS for data output from the sub-pattern generation unit 4b to the SAM unit 2b.

A count enable signal is loaded into the register RG1 at the start of the memory test. Register R
G1 is the same as the number of bits constituting the main address, for example, 16 bits.
The size of the bit. FIG. 3E shows an example of the count enable data set in the register RG1. The maximum value of the column address of the target memory under test (25
5 = 11111111) is the half of the LSB side of RG1 (8 bits)
Then, "0" is written to all the remaining bits (8 bits) on the MSB side. The enable signal loaded to the register RG1 is supplied to counters C1 and C2, and only the bit range of "1" of the enable signal can be counted. The register RG2 is a register for setting a stop address corresponding to the stop register control function described with reference to FIG. 7C.

The comparator 14 selects the register RG1 in the case of the simple read transfer and the split read transfer according to the select signal SL4, and selects the register RG2 in the case of the stop control split read transfer and compares it with the output of the MUX. When a match is detected, a match detection signal “1” is given to the control unit 12. When the coincidence detection signal "1" is supplied, the control unit 12 activates the counter C1 (or C1) in the active state.
The supply of the clock CK1 (or CK2) to 2) is stopped, and the counter C which has been inactive until then is stopped.
Start supplying clock CK2 (or CK1) to 2 (or C1). A stop address is set in the register RG2, and the RAM is placed on the inactive side of the SAM unit 2b.
When data transfer is being performed from the unit 2a, the register R
G2 is selected (see FIG. 7). In the case of split read transfer, the comparator 14 calculates the column address value A, which is the maximum address of each of the lower address area and the upper address area when the entire column address area is divided into two.
It is necessary to detect M1 = "01111111" and AM2 = "11111111", respectively, but it is not necessary to identify whether they are the upper maximum value or the lower maximum value. Therefore, the LSB 1 is obtained from the 16-bit output of the register RG1.
The output of the lower 8 bits excluding the bits, ie, “0111111
"1" is given to the comparator 14. The coincidence detection by the comparator 14 is performed only in the range of consecutive "1" bits of the data set in the register RG1 or RG2. Since data having a desired number of consecutive bits "1" can be set according to the length, MUs having different sizes (word lengths) of the SAM unit 2b can be used together with the format function of the address selector.
The test of T can be performed without any trouble. (A) Simple read transfer test Main address MA consisting of row address and column address (SAM start address) from main pattern generation section 4a
Is given to the RAM unit 2a, and when a transfer command is further given, the RAM unit 2a sets its SAM start address to SA.
The data is supplied to the M unit 2b and all data of the row address is read and transferred to the SAM unit 2b. On the other hand, the same main address MA is loaded into one counter, for example, the counter C1 according to the select signal SL1.

As data is output for each clock CKS from the SAM section 2b of the MUT 2 as shown in FIG. 6B, the counter C1 counts the clock CK1 synchronized with the clock CKS and sequentially increments from the SAM start address. . However, the counter C1 has the LSB corresponding to the range where the register RG1 is set to "1".
The increment operation is enabled only in the range of 8 bits on the side, and the transfer row address (8 bits) on the MSB side set in the counter C1 does not change. The multiplexer MUX always selects and outputs the count value of the counter in the counting state (active state).
Is controlled by The output of the multiplexer MUX is output as a sub address SA 'including a set of a transfer row address and a column address. MU in simple read transfer mode
When operating T, the control unit 12 supplies the control command CSb to the control unit 12 by the sub-pattern generation unit 4b before starting data output from the SAM unit 2b, regardless of the output of the comparator 14. The unit 12 switches the counter C1 to inactive and the counter C2 to active in response to the control signal CSb.
In response to the data transfer instruction of the next row address, the main address MA
Is loaded into the counter C1 and the same operation is performed. In this manner, the counters C1 and C2 alternately supply a series of sets of the transfer row address and the column address to the sub-failure analysis memory 7b during the read transfer test.
As a data output terminal O via a multiplexer MUX
Output to UT. In the simple read transfer operation, data transfer and data output from the SAM unit 2b are performed alternately in different cycles, so that the counters C1, C2
Obviously, the control unit 12 can control the generation of the subaddress using only one of the two. (B) Split-Read Transfer Test When operating the multiport DRAM MUT in the split-read transfer mode (FIG. 7A),
The data of each transfer row address of the section 2a is composed of two areas of lower areas 0 to 127 and upper areas 128 to 255 of all column addresses.
SAM2b-L and upper SAM2b
-U separately. As shown in FIG.
The data from the SAM start address S1 to the address 127 of the AM2b-L is sequentially output, and then the SAM2
bU SAM start address S2 to address 25
The sequential output of data up to 5 is repeated for each row address.

The main pattern generating section 4a has an 8-bit transfer row address R and an 8-bit SAM start address S1.
A main address signal MA consisting of a set of
When the transfer command is further given to the AM section 2a, the RAM section 2a uses the given row address R and the most significant bit of the SAM start address S1, for example, the lower column address areas 0 to 127 represented by "0". All specified data is transferred to the lower SAM 2b-L at one time. on the other hand,
In response to the main control signal CSa corresponding to the transfer instruction, the control unit 12 selects one of the counters C1 and C1 not performing the counting operation, out of the counter states shown in rows D and E in FIG.
2. Load the main address MA = RS1 into, for example, C1 (FIG. 8, row F). However, in FIG. 8, rows E, F, and I show only the column address without the row address R.

Next, the SAM unit 2b converts the transferred data into
In accordance with the clock CKS (row A in FIG. 8) supplied from the sub-pattern generating unit 4b to the SAM unit 2b, the data is sequentially output from the SAM start address S1 to the maximum address AM1 = 127 in the lower address area. At this time, the control unit 12 supplies the clock CK1 (row B) to the counter C1 loaded with the main address MA in synchronization with the clock CKS, and sequentially increments from the SAM start address S1 as shown in row F of FIG. Accordingly, the count value output of the counter C1 (including the set transfer row address R) is used to store the data output from the SAM unit 2b at that time.
a represents the original address in the subaddress S
Output from the multiplexer MUX as A '(row I).

While the data is sequentially output from the lower SAMs 2b-L, the main pattern generator supplies the RAM 2a with a main address signal MA consisting of a set of a row address R and a SAM start address S2. When a transfer command is given, the RAM section 2a stores the row address R and the upper column address area 128 to 255 indicated by the most significant bit "1" of the SAM start address S2, as described above.
Is transferred to the upper SAM 2b-U at a time. Main control signal CS corresponding to this transfer command
In response to a, the control unit 12 loads the main address MA = RS2 into the counter C2 which has not performed the counting operation as shown in FIG. 8, rows E and G. When the value of the lower 7 bits of the count value of the counter C1 reaches the value 127 represented by the lower 8 bits excluding 1 bit of the LSB of the enable data set in the register RG1, that is, the maximum address AM1 of the lower address area, As shown in H, the comparator 14 outputs a coincidence detection signal "1", and the control unit 12 responds to the coincidence detection signal as shown in rows D and E,
The state of C2 is switched.

Next, the SAM unit 2b sequentially outputs the transferred data from the start address S2 to the maximum address AM2 = 255 in the upper address area according to the clock CKS. At the same time, the control unit 12 sets the main address MA =
A clock CK2 (row C) is supplied to the counter C2 loaded with RS2 in synchronization with the clock CKS, and the counter C2 is sequentially incremented from the start address S2 to an address AM2 = 255 at which the comparator 14 outputs a match detection signal (row G).
Multiplexer MUX with count value as sub address SA '
(Line I). During this time, the main pattern generating section 4a updates the row address R (for example, increments by R ← R + 1), and stores the main address MA = RS1 in the RAM as described above.
Data from column address areas 0 to 127 in a new row address R to lower SAM 2b-L
And the select signal S from the control unit 12
The main address MA = RS1 is counted by the counter C1 by L1.
(Row F).

In this manner, the lower SAM 2b-L and the upper S
One of the AM2b-U receives the data transfer from the RAM unit 2a, and the main address MA including the SAM start address is loaded into one of the counters C1 and C2, during which time the other of the lower SAM2b-L and the upper SAM2b-U is already loaded. At the same time as outputting the transferred data, the other of the counters C1 and C2 is sequentially incremented from the start address, and the output of the sub address SA 'is alternately performed in parallel on the lower side and the upper side. (C) Stop Control Split-Read Transfer This transfer operation is basically the same as the above-described split-read transfer operation, and as shown in FIG. 7C, the lower SAM 2b
-Load the main address MA including the SAM start address S1 (or S2) into the counter C1 (or C2) in order to start outputting data from the start address S1 (or S2) to L (or the upper SAM2b-U). However, the difference from the above-described split read transfer operation is that the counter is not incremented to the maximum address of each of the lower and upper address areas, for example, 127 and 225, and a desired address in the middle (stop address set in the register RG2). This is to alternate the active state and the inactive state of each counter at Sp1 and Sp2. However, in the embodiment shown in FIG.
1, since only the range of consecutive "1" bits of the data given from RG2 can be compared, the stop addresses in the lower and upper address areas are 2
^It is necessary to select a value represented by ^m− 1, 2 ⁿ⁻ 1 (m, n is an integer of 0 or more and 7 or less), but the comparator 14 is configured so that the comparison can be performed with an arbitrary value of 0 to 127. It is easily possible.

The register RG2 is loaded with 8-bit stop address data generated by the main pattern generator 4a as a main address signal MA in a desired main address generation cycle. In the comparator 14, the register RG2
Is selected by the select signal SL4, and is compared with the count value from the incremented counter C1 (or C2). When a match is detected by the comparator 14, the control unit 12
Switches the selection of the counter in the multiplexer MUX so as to jump to the start address S2 (or S1) of the opposite address area, and outputs the clock CK2 (or CK) to the selected counter C2 (or C1).
1) Supply. The output of the counter C2 (or C1) selected by the multiplexer MUX is the subaddress SA '.
Is output as The other operations are basically the same as the above-described split read transfer operation, and thus description thereof is omitted.

Although the above-described simple read transfer, split read transfer, and stop control split read transfer have been described separately, to switch from any transfer mode to any other transfer mode during the MUT test, simply use the counter C1. , C2, and the data to be loaded into the register RG2 may be changed as needed.

[0023]

As described above, the failure analysis memory 7
b is generated from the sub-pattern generating section 4b by a program in the related art.
In the present invention, the main address signal MA and the main control signal CSa from the main pattern generator 4a and the sub-control signal CSb from the sub-pattern generator 4b are input to the sub-address generator 7c, respectively. Signal SA '
Can occur. Therefore, problems such as securing an enormous amount of work required for a conventional program and realizing an extremely complicated and difficult program are solved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a block diagram of a sub address generator in FIG. 1;

FIG. 3 is a diagram showing a bit configuration of data of a main part of FIG. 2;

FIG. 4 is a block diagram showing a configuration of a memory under test (MUT).

FIG. 5 is a block diagram of a conventional memory test device.

6A is a diagram for explaining a read transfer function of a memory under test, and FIG. 6B is a diagram for explaining a data output operation of a SAM unit in a simple read transfer mode.

7A is a diagram for explaining a split read transfer function of a memory under test, FIG. 7B is a diagram for explaining a data output operation of the SAM unit in a split read transfer mode, and FIG. 7C is a stop control split read. FIG. 7 is a diagram for explaining a data output operation of the SAM unit in a transfer mode.

FIG. 8 is a time chart for explaining a sub address generation operation at the time of split read transfer.

Claims (4)

(57) [Claims] A timing signal is supplied from a timing generator to a main and sub pattern generator, and a test pattern, a control signal and a main address signal are supplied from the main pattern generator to a random access RAM section and a serial access SAM section. And the test pattern and the clock signal from the sub-pattern generating unit are input to the SAM unit, and the RAM unit and the SA
The test pattern read from the M section and the expected value pattern supplied from the main and sub pattern generation sections are compared by the main and sub logic comparison sections, and when a mismatch is detected between them, a main and sub fail signal is generated, In a memory test apparatus for writing data into main and sub failure analysis memories each having the same memory space as the RAM unit, the failure analysis memory having the main failure analysis memory and the sub failure analysis memory transmits a sub address signal given to the sub failure analysis memory. And a sub-address generator for generating one of the plurality of counters, and selecting one of the plurality of counters in a counting state and supplying the counted value to the sub-failure analysis memory. A multiplexer for outputting as a sub address signal, and data of a value corresponding to the size of the column address of the memory under test. Register means for comparing at least a part of the output data of the multiplexer with at least a part of the data set in the register means, and outputting a match detection signal when they match, Each time a main address signal is applied, it is loaded into one of the non-counting states of the counter, and each time data corresponding to the main address is sequentially output from the SAM unit, the loaded counter is incremented; In response to the coincidence detection signal from the comparing means, the increment of the counting counter is stopped, and one of the counters for which a new main address signal is set is replaced with the data corresponding to the main address by the SAM. Control means for incrementing each time the data is sequentially output from the unit. 2. The memory test apparatus according to claim 1, wherein the sub-failure analysis memory is further provided with a stop address generated by the main pattern generation section as the main address signal, and stores the stop address. Wherein the comparing means is controlled by the control means while the SAM section is outputting data transferred in the stop control split read transfer mode, selects the stop address register, and selects at least one of the outputs of the multiplexer. And outputs a match detection signal when a match is detected. 3. The memory test apparatus according to claim 1, wherein the sub-failure analysis memory further includes a transfer row address of the RAM unit and a start address of the SAM unit from the main pattern generation unit. An address selector to which the main address signal is inputted, and the transfer row address and the start address are arranged in a predetermined order and supplied to one of the plurality of counters. 4. The memory test apparatus according to claim 1, wherein each of said counters is provided with a set value of said register means as enable data, and can count within a continuous "1" bit range of said enable data. And the enable data is "1" having the same number of bits as the column address size of the memory under test.
Is included on the lower side.