JP3353704B2 - Fill-in signal unit processing circuit for multiplex processing - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a fill-in signal unit processing circuit for multiplex processing, and more particularly, to a fill-in signal unit processing circuit for multiplex processing aimed at reducing firmware processing.

[0002]

2. Description of the Related Art Generally, when exchanges transmit and receive signals, exchanges determine a protocol (communication means) between the exchanges in advance and transmit and receive signals according to a predetermined procedure. CC
In the common line signaling system No. 7 recommended by the ITT (International Telegraph and Telephone Consultative Committee), four levels are adopted as protocols. Level 2 is also called a signal link level, and a link is a word indicating a signal line used in level 2. In order to transfer a signal unit to an adjacent exchange through a signal line without error, a function of error checking and retransmission is performed. It is a level to have.

The level 2 processing of the common channel signaling system No. 7 is as follows.
The various functions of identification / synchronization, error detection, error correction, initial setting, error monitoring and flow control of the start / end of the signal unit were processed as one set.

Accordingly, the fill-in signal unit sent out for the purpose of time fill is processed by firmware when a retransmission request or a buffer for a significant signal waiting for acknowledgment is released, so that the level 2 processing capability is determined by the CPU. As a result, as the number of fill-in signal units increases, the processing performance decreases, which causes congestion. Therefore, if multiplex processing is attempted, the number of fill-in signal units is further increased, and there is a possibility that the processing capacity is further reduced.

[0005]

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above, and identifies a fill-in signal unit required for response processing from a received signal unit and deletes a fill-in signal unit for time-fill purposes. Accordingly, an object of the present invention is to provide a fill-in signal unit processing circuit for multiplex processing which reduces firmware processing without lowering link quality.

[0006]

A fill-in signal unit processing circuit for multiplex processing according to the present invention removes a fill-in signal unit transmitted for a time-fill purpose from a received signal unit at level 2 of the No. 7 signal system and responds. A multiplexing fill-in signal unit processing circuit that detects a fill-in signal unit required for processing and performs level 2 processing.
Therefore, the detection of the normal signal unit from the reception signal unit and
A detection circuit for detecting an error, and a detection circuit for detecting the error.
The normal signal unit that has been
Distinction between the signal unit and the link state signal unit
A signal unit identification circuit, and the signal unit identification circuit;
Determines whether the identified fill-in signal unit is necessary or unnecessary
A FISU processing circuit for instructing discard / non-discard processing
Monitoring the error by detecting the error of the detection circuit.
An error monitoring circuit to perform, the error monitoring circuit and the
Abnormal unit is detected by count instruction from FISU processing circuit.
Information statistics that statistics the number of failed units and the number of discarded normal units
And an error signal from the error information statistical circuit.
Error information is used when assembling the frame.
In the received data as a part of the field .

[0007]

[0008]

[0009]

[0010]

[0011]

Embodiments of the present invention will be described below with reference to the drawings.

In the above-mentioned level 2 processing of the No. 7 signal system, when performing multiplexing processing, the fill-in signal unit transmitted for the purpose of time filling when there is no significant signal unit has the most influence on the processing capacity. It can be said that it will come. The fill-in signal unit processing circuit for multiplex processing of the present embodiment performs processing of extracting only fill-in signal units necessary for response processing before performing level 2 processing, and implements multiplex protocol processing without lowering the firmware processing capability. Things.

FIG. 1 is a block diagram showing a fill-in signal unit processing circuit for multiplex processing according to the present invention.

In order to perform a fill-in signal unit process for each of a plurality of links 10 set in advance, the distribution circuit 1 first performs a process of distributing the received data, and determines that the received data and its own link are provided for each link 10. Inform. Each link 10 includes a circuit described below.

In the No. 7 signal system, units are distinguished by flags ("01111110") added before and after the signal unit. For this purpose, first, there is provided a flag detection circuit 2 for detecting a flag pattern to identify the start / end of the transmitted data. After the flag detection circuit 2 recognizes the flag pattern of the signal unit, a check is performed by the error detection circuit 3 which determines whether or not the transmitted signal unit is normal. At this time, when seven or more consecutive “1” s called an abort pattern are detected, it is determined that the link is out of synchronization, and the error monitoring circuit 4 is notified.

The error detection circuit 3 checks the CRC of the transmitted signal unit, and checks whether the signal unit length and octet are positive multiples. At this time, if the check result is abnormal, the error monitoring circuit 4 is notified and a discard instruction is notified. The error monitoring circuit 4 performs abnormal unit count control based on the notified error,
This is reported to the error information statistical circuit 7.

On the other hand, the data is sent from the error detecting circuit 3 to the signal unit identifying circuit 5, where the significant signal unit (MSU) and the link state signal unit (LSS) are sent.
U) and three types of fill-in signal units (FISU). If it is a fill-in signal unit, it notifies the FISU processing circuit 6.

The FISU processing circuit 6 determines whether or not a reception fill-in signal unit is necessary or not. If not, a discard instruction is reported.
Report to. The error information statistic circuit 7 statistically counts the number of abnormal units and the number of normal units discarded based on reports from the error monitoring circuit 4 and the FISU processing circuit 6. In the write control circuit 8, the flag of the sent signal unit and C
By storing signal contents other than K bits in the buffer memory until the discard instruction is notified, and adding the number of errors and the number of normal units discarded as part of the address field after receiving the last byte, the error information is obtained. Report. When the processing in each link is completed, the frame is assembled in the frame assembling circuit 9 and transmitted to the multiplex protocol processing circuit.

The operation of this embodiment will be described below.

Each link 10 receives the received data from the distribution processing circuit 1 and starts a process of receiving the data.

In the present invention, error monitoring of level 2 processing is realized by performing abnormal unit count management shown in the flowchart of FIG. At level 2, synchronization is achieved by a flag, and the received signal unit length is (m + 6)
At this time, it is determined that synchronization has been lost. In error monitoring,
In the case where the synchronization is lost, the count operation is different. For this reason, the flag detection circuit 2 monitors two patterns of the received data, that is, the flag pattern and the abort pattern, while removing 0 from the received data. When the flag pattern is received, the start / end of the received data can be determined, so that the flag reception is notified to each block that processes only a necessary portion from the received data,
Start each operation. On the other hand, if an abort pattern is received, it is determined that synchronization has been lost, and the error monitoring circuit 4
Notify.

The error monitoring operation is as follows. When the abort pattern detection signal is received from the flag detection circuit 2 or the flag is not received for a certain length due to a long unit reception error detected by the error detection circuit 3, the out-of-synchronization detection signal is activated. An error monitoring timer that monitors an out-of-synchronization detection signal is started at each time, and a count instruction is issued only when the timer times out. At this time, even if an error signal from the error detection circuit 3 is reported, no count instruction is performed. Further, the synchronization loss is maintained until a normal signal unit is received, and during that time, counting up by a timer timeout is continued regardless of the reception of the signal unit. The error monitoring timer that operates independently here is determined by the line speed and the transmission cycle of the fill-in signal unit.
Next, when a flag is detected (when synchronization is not lost)
If the error detection circuit 2 receives a CRC check error, short unit reception, long unit reception, or an error signal indicating that the receiving unit is not a positive multiple of octets, the count is incremented unless synchronization is lost. Make instructions. However, for the long unit reception, the flow proceeds after the flag is detected, and the flow is out of the condition of 6 to (m + 6) octets or less in signal unit length. The operation is to activate the out-of-position detection signal. When the above error is detected, all received signal units are discarded, a discard instruction is notified to the write control circuit 8, and discard processing is performed. In this way, the number of errors is counted up. The trigger for resetting the incremented value is after it has been reported.

Next, FIG. 3 shows the processing operation of the fill-in signal unit which becomes a bottleneck in the processing capacity when multiplexing is performed.
This process is an operation performed on the normal signal unit as shown in FIG. First, upon receiving the flag reception report, the signal unit identification circuit 5 starts counting the number of octets of the received data. In the No. 7 signal system, the fill-in signal unit is 3 octets excluding the flag and the CK bit, and therefore, depending on the number of octets of the received signal,
It is determined whether the signal is a fill-in signal unit.

Next, whether the fill-in signal unit is required for the response processing or not is determined by the first two reception units.
It can be determined by the octet sequence number. This is because the fill-in signal unit transmitted for the purpose of time fill is provided with the sequence number of the last significant signal unit transmitted. Therefore, FISU
In the processing circuit 6, the sequence number of the received normal signal unit is updated and held, and when the fill-in signal unit is received, the sequence number is compared with the held sequence number. It can be judged as a unit, and disposal processing is performed. However, this fill-in signal unit is performed after the link is established. Therefore, the processing of the fill-in signal unit is started under the control of the multiplex protocol processing circuit. Here, when the discard processing is performed, it is reported to the error information statistic circuit 7, and the number of normal discards is statistic. This counter value is also reset when reported.

The count results in these two processes are reported by adding them to received data as part of an address field when assembling a frame. By performing the above, the fill-in signal unit processing in the preceding stage can be realized without lowering the link quality.

[0026]

The first effect is that the occurrence of congestion can be reduced. The processing of the fill-in signal unit most depends on the processing capacity, and since the processing is performed by extracting only the fill-in signal unit necessary for the response processing before performing the processing of level 2, it is possible to reduce the occurrence of congestion. .

The second effect is that error monitoring is performed based on error detection of the received signal unit. Since error detection is performed when the fill-in signal unit process is performed, error monitoring can be easily performed. This is performed by hardware logic, and the firmware processing can be reduced.

The third effect is that the link quality can be guaranteed by notifying the error monitoring result and the normal fill-in signal unit by the processing for the first effect.

The error monitoring and the fill-in signal unit processing need only be performed on a link-by-link basis, but the link may not have a processing circuit.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a fill-in signal unit processing circuit for multiplex processing according to the present invention.

FIG. 2 shows a flowchart of error monitoring of level 2 processing.

FIG. 3 shows a processing operation of a fill-in signal unit.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 distribution circuit 2 flag detection circuit 3 error detection circuit 4 error monitoring circuit 5 signal unit identification circuit 6 FISU processing circuit 7 error information statistical circuit 8 write control circuit 9 frame assembly circuit 10 link

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04M 3/00 H04M 7/06

Claims (1)

(57) [Claims] 1. In level 2 of No. 7 signal system, receiving
File sent from the signal unit for the purpose of time fill
Ruin signal unit is deleted and fill-in required for response
Processing for detecting signal units and performing level 2 processing
Signal unit processing circuit for detecting a normal signal unit and an error from a received signal unit
A detection circuit for detecting the
A normal signal unit is a fill-in signal unit and a significant signal
Signal unit that identifies the unit and the link status signal unit.
Unit identification circuit and the signal unit identification circuit.
Judge the necessity / unnecessity of the filled-in signal unit
A FISU processing circuit for instructing discard / non-discard processing
e,An error that is monitored by the detection circuit.
Monitoring circuit, the error monitoring circuit and the FISU
Correct the number of abnormal units by the count instruction from the processing circuit.
An error information statistic circuit that stats the number of units discarded
In addition, The error information from the error information statistical circuit is a frame
As part of the address field when assembling
Characterized in that it is added to the communication data Multi-processing file
In signal unit processing circuit.