JP3362972B2 - Software simulator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a software simulator capable of simulating application software to be operated on a target microcomputer.

[0002]

2. Description of the Related Art Conventionally, when a target microcomputer to be incorporated into a home electric appliance or the like has not been completed and application software operating on the microcomputer is developed or operation verification is performed, ICE is required.
Or it is performed using a software simulator. Here, ICE is an abbreviation for in-circuit emulator, which is a debugging tool peculiar to a microprocessor. Here, a software simulator generally gives another computer an object program of the target application software, creates a state in the other computer that is similar to the operation of the computer of the target model to execute the application software, and simulates it. The purpose is to make this happen.

[0003]

However, the ICE
In the operation verification of the application software using, there is a functional difference from the operation of the target microcomputer, so the operation confirmation becomes insufficient. Therefore, the final confirmation of the operation of the application software must wait until the completion of the target microcomputer.

Therefore, instead of ICE, a software simulator is an effective means. Since the software simulator creates operations such as the instruction sequence and input / output of the microcomputer according to the specifications of the target microcomputer, it is more stable than ICE and can develop the application software and verify the operation.

However, the current software simulator has a problem that the simulation time is much slower than the processing time in the target microcomputer in order to faithfully simulate the instruction. For example, on the target microcomputer or ICE, the processing that is completed in 1 second takes several minutes to tens of minutes.

In view of the above problems, it is an object of the present invention to provide a software simulator capable of shortening the execution time of application software on the software simulator.

[0007]

In order to achieve the above object, the present invention has application software storage means for storing application software to be simulated and an area for holding the memory contents of the target microcomputer. Memory content holding means, register content holding means having an area to hold the register contents of the target microcomputer, and application software stored in the application software storage means. Execution instruction deciding means for deciding one instruction based on the memory content or register content, and simulation execution of the instruction to be executed by simulation based on the memory content or register content, and the modified memory content or register content And a simulation executing means to be held in the register content holding means, a loop detecting means for detecting whether the instruction executed by the simulation executing means constitutes a loop, and a loop detected by the loop detecting means, Shortening execution determination means for determining whether or not the loop can be shortened, and predicting the contents of the memory and the register when it is assumed that the shortened loop has been executed for the number of loops, and storing the result as memory content holding means, It is characterized in that it comprises a memory / register content changing means for reflecting in the register content holding means.

[0008] In the present invention, a loop instruction table which holds an instruction that may cause loops to be al,
A loop non-shortening instruction table holding instructions that cannot be executed by shortening the loop, and the loop detection means has an instruction executed by the simulation execution means in the loop instruction table, and the instruction The address of the instruction to be executed next is smaller than the address of the instruction, and the address of the instruction to be executed next is the address that has already been executed. A loop instruction check means for determining whether or not a loop shortening unexecutable instruction, which is an instruction stored in the loop shortening impossible instruction table, exists in the instruction sequence to be a loop detected by the loop detecting means. And a shortened execution determination unit that determines that the loop can be shortened if it does not exist. To.

[0009] In the present invention, it includes a history storage unit is a region for holding a memory access history is changed history and history of access to the memory of the memory contents and register of the microprocessor of the target is al, The shortened execution determination unit includes an instruction sequence execution unit that executes an instruction sequence to be a loop detected by the loop detection unit for each instruction, and an instruction sequence that is executed each time the instruction sequence execution unit executes an instruction. When an instruction sequence storage unit that stores an instruction sequence and the instruction sequence execution unit execute an instruction, if the executed instruction accesses the memory content holding unit or the register content holding unit to change the content, the change The loop memory access holding unit that holds the history and memory access history in the history holding unit and the instruction sequence stored in the instruction sequence storage unit are executed again. If an instruction that has not been executed is executed, if the memory content holding means or the register content holding means is accessed, and the change in the content cannot be predicted, or if the instruction has not been executed in the instruction sequence. It is characterized in that it is configured in this way from the loop shortening executability judging unit that judges that the loop can be shortened except when there is an instruction that may change the memory contents and the register contents.

Further , in the present invention, the memory / register content changing means detects an instruction that exits the loop when it is determined that the loop can be executed in a shortened manner, and a change history of the instruction and the memory and a change history of the register. And a memory access history, the number of times the loop is executed until the end of the loop is calculated as the number of loops that can be executed in a shortened manner, a memory content holding unit, a register content holding unit, and a history holding unit. The contents of the memory and the register when the number of loops is assumed to be executed are predicted based on the calculated contents and the calculated number of times that the loop can be executed, and the result is reflected in the memory contents holding means and the register contents holding means. And a changing unit for performing the change.

[0011] In the present invention, the start address and the end address of the instruction sequence to a loop In addition, a loop count calculation information which is the address for extracting the information necessary to calculate the number of loops, Loop information storage means for storing when the changing unit reflects in the memory content holding means and the register content holding means, and the start address and end address of the instruction string when the loop calculation means detects an instruction string to be a loop And a loop re-execution judging means for judging that the loop is re-executed by being stored in the loop information storage means, and the loop execution frequency calculation unit judges that the loop is re-executed. Loop count calculation information address is used to extract the information required to calculate the loop count and the number of loops can be shortened When it is determined that the loop is being re-executed, the changing unit executes the loop count based on the information extracted using the loop count calculation information address and the loop count that can be shortened. It is characterized in that the contents are predicted in the memory and the register when it is assumed that the result is reflected in the memory contents holding means and the register contents holding means.

[0012] In the present invention, an interrupt processing means for simulating an interrupt operation in further, the interrupt operation maintains a a is interrupt generation time period to simulate, to the interrupt processing unit to become interrupt generation time An interrupt time management means for simulating an interrupt operation, and an interrupt generation frequency calculation means for calculating an interrupt generation loop frequency that is a loop frequency until an interrupt occurs based on the interrupt generation time managed by the interrupt time management means. An interrupt loop number determining unit that compares the loop number calculated by the loop execution number calculation unit with the interrupt generation loop number, and determines the smaller loop number as a loop number that can be newly shortened and executed. Characterize.

[0013] In the present invention, the I / O event processing means of simulating I / O events further, I / O
An I / O event occurrence time, which is a time at which an event occurs, is managed, and when the I / O event occurrence time comes, the I / O event processing means causes the I / O event processing means to simulate an I / O event. And an I / O event occurrence count for calculating the I / O event loop count, which is the number of loops until the I / O event occurs, based on the I / O event occurrence time managed by the I / O event time managing means. An I / O loop count that compares the loop count calculated by the loop calculation count calculation unit and the loop execution count calculation unit with the I / O event loop count, and determines the smaller loop count as a loop count that can be newly shortened and executed. And a determining means.

[0014]

According to the above configuration, one to be simulated executed next instruction in the application software stored in the application software storage means is determined by the execution instruction determining means based on the memory contents and register contents, simulation The simulation is executed by the execution means. The loop detection means detects whether or not the instructions executed by simulation form a loop, and the shortened execution determination means determines whether or not the detected loop can be shortened. When it is determined that the loop can be executed in a shortened manner, the memory and register contents assuming that the loop has been executed the number of times of the loop are predicted by the memory / register contents changing means, and the prediction result is the memory contents holding means and the register contents. Since it is reflected in the holding means by the memory / register contents changing means, one instruction to be executed in the simulation after exiting the loop is decided by the execution instruction deciding means, and as a result, the loop is shortened and executed.

Further , according to the above configuration, since the loop instruction table is provided, the instruction string to be a loop is detected using the loop instruction table. Since the loop non-shortening instruction table is provided, the loop in the instruction sequence that should be a loop using the loop non-shortening instruction table is
Whether or not the loop can be shortened is determined by the shortening execution determination means.

According to the above configuration, when the instruction sequence to be a loop detected by the loop detection means is executed by the instruction sequence execution unit for each instruction, the instruction sequence is executed in the order of the executed instructions. The change history of the memory contents, the memory access history, and the register change history are saved in the save unit, and are saved by the loop memory access save unit, so it is possible to shorten the loop by using them. It is judged by the judgment unit.

Further , according to the above configuration, when the loop can be shortened, an instruction that exits the loop is detected, and the loop is terminated based on the instruction, the memory change history, the register change history, and the memory access history. The loop execution count calculation unit calculates the number of loops up to. Based on the calculated number of loops, the history of memory changes, and the history of register changes, the contents of the memory and the registers when the number of loops is assumed to have been executed are predicted by the changing unit, and the results are reflected. As a result, the loop is shortened.

Further , according to the above configuration, since the start address, the end address, and the loop count calculation information address of the instruction sequence to be looped are stored in the loop information storage means, the loop detection means has instructions to be looped. When the sequence is detected, the loop re-execution determination unit determines that the loop is re-executed by storing the start address and end address of the instruction sequence in the information storage unit. When it is determined that the loop is being re-executed, the loop count is calculated using the loop count calculation information address, and it is assumed that the loop count is executed using the loop count and the loop count calculation information address. The memory and the register of the above are predicted by the change unit, and the result is reflected.

Further , according to the above configuration, the interrupt generation time is managed by the interrupt time management means, and the interrupt generation loop count is calculated by the interrupt generation count calculation means based on the interrupt generation time. The interrupt loop count and the loop count calculated by the loop execution count calculator are compared by the interrupt loop count determining means, and the smaller loop count is newly determined as the loop count that can be shortened.

Further , according to the above configuration, the I / O event occurrence time is managed by the I / O event occurrence time managing means, and the I / O event loop count is calculated based on the I / O event occurrence time. It is calculated by the O event occurrence frequency calculation means. The I / O event loop count and the loop count calculated by the loop execution count calculation unit are I / O
The number of loops is compared by the O-loop number determining means, and the smaller number of loops is newly determined as the number of loops that can be shortened.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A software simulator according to a first embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a software simulator and an environment surrounding the software simulator according to an embodiment of the present invention. This figure comprises a computer main body 110, a disk device 120, a keyboard 130, and a display 140.

The computer main body 110 has a software simulator 100 inside, and a disk device 120.
Is connected to the keyboard 130 and the display 140. The software simulator 100 has a memory area 1
01, register area 102, instruction execution unit 103, instruction sequence storage unit 104, loop instruction table 105, and loop non-shortening instruction table 106.

The memory area 101 is an area for holding the memory contents of the target microcomputer. When executing the simulation, the target application software to be simulated is also stored. Examples of the application software stored when the simulation is executed are shown in FIG. 9, FIG. 10, FIG. 11, FIG.
3 is shown. The definition of the instruction used in this application software is shown in FIG. 14, and the meaning of each instruction is shown in FIGS. 15, 16 and 17.

The register area 102 is an area for holding the register contents of the target microcomputer to be simulated. The instruction sequence storage unit 104 is an area for storing an instruction sequence to be a loop and an execution number, which is the order in which the instructions in the instruction sequence are executed. The loop instruction table 105 is a table as shown in FIG. 2 and holds instructions that may form a loop.

The loop non-shortening instruction table 106 is a table as shown in FIG. 3, and holds the instructions that cannot be executed by shortening the loop. The history holding unit 107 is an area for holding a memory change history that is a history of memory changes, a register change history that is a history of register changes, and a memory access history that is a history of memory accesses.

The instruction execution unit 103 is a portion for executing and shortening the instruction sequence of the target application software, and is specifically shown in the control flow charts of FIGS. 4 and 5.
First, the target application software to be simulated is loaded from the disk device 120 and placed in the memory area 101 (step S500). Using a program counter (not shown) in the register area 102, the instruction at the position indicated by the program counter is sequentially executed and a loop is detected (steps S501 to S506). The loop is detected by executing the instruction in the loop instruction table 105, the address of the instruction executed next to the instruction is smaller than the address of the instruction, and the address of the instruction executed next is executed earlier. It is performed by being the registered address. Here, the loop is detected by regarding the address of the instruction currently being executed as the loop end address and the address of the next instruction to be executed as the loop start address.

Next, it is judged whether or not there is an instruction that cannot be executed in a shortened manner in the instruction sequence forming the detected loop by comparing with the loop incompressible instruction table 106 ( Steps S507 and S508). If there is no instruction that cannot be shortened and executed, the instructions of the instruction sequence are sequentially executed, and the instructions are stored in the instruction sequence storage unit 104 in the order of execution in the format shown in FIG. The execution number, which is the order of execution, is also added to the instruction and saved (step S50).
9-step S513). It is determined whether or not the next executed instruction has changed the contents of the memory area 101 and the register area 102, and if so, the change history of the memory and the register is changed in the format shown in FIGS. 7 and 8. The history is stored in the history holding unit 107 (steps S514 to S517). Next, when the instructions of all the instruction sequences have been executed (step S511), it is determined whether or not the loop formed by the instruction sequences can be shortened (steps S518 and S519). Here, whether or not the loop can be shortened is determined as follows. First, the instruction sequence of the loop is executed again. At this time, if an instruction that has not been executed previously is executed this time, it is determined that the loop cannot be shortened. Also, when accessing the memory or register to update its contents, and when the change rate, which is the rate of change in the contents of the memory and register at the previous execution, is different from the change rate at the current execution, the loop It is determined that the shortened execution of is impossible. Furthermore, the instruction sequence of the loop is sequentially inspected from the beginning, and an instruction that has not been executed in either the previous execution or the present execution and that may change the contents of the memory and the register (MOV instruction, ADD instruction, SUB
Also, when it is detected that there is an instruction, a MUL instruction, etc.), it is determined that the loop cannot be shortened.

If the shortened execution is not possible, step S50.
In step 5, the number of times of looping is calculated if shortening is possible (step S520). The number of loops is calculated as follows. First, a jump instruction that exits the loop is detected (here, the jump instruction is as shown in FIG.
2 of the conditional branch instruction and the unconditional branch instruction as shown in 4
Types exist). When the detected jump instruction is an unconditional branch instruction, a conditional branch instruction that is a branch source instruction branching to the unconditional branch instruction is detected. Then, the condition for the conditional branch instruction to branch to the unconditional branch instruction is calculated. The number of loops is calculated based on the condition, the memory and register change history, and the memory access history. On the other hand, when the detected jump instruction is a conditional branch instruction, the condition for exiting the loop is calculated by this instruction, and the number of loops is calculated based on the condition, the memory and register change history, and the memory access history. . When it is determined that the number of loops is infinite, a predetermined number of times is set as the number of loops.

Next, the contents of the memory and the register when it is assumed that the loop has been executed for the number of times of the loop are predicted from the number of times of the loop and the change of the memory and the register, and the predicted contents are reflected in the current memory and the register, and the loop Shortened execution (step S521). After that, the value of the program counter in the register area 102 is set to the loop top address, and the normal simulation is resumed.

The disk device 120 holds an application program to be operated by the target microcomputer. The keyboard 130 receives an operation instruction of the software simulator. Display 14
0 displays a simulated result or the like. Next, in order to explain the simulation operation using the specific application software example shown in FIG.
The structure of the application software will be described, and then the simulation operation will be described.

FIG. 9 shows an example of application software to be implemented by the present invention. This is a program written in assembly language. The commands used in the program are defined in FIG. 14 and their meanings are described in FIGS. 15, 16 and 17. The part indicated by 92 is a command part. The part indicated by 91 is an address part indicating the relative address of the instruction line in this program. The part indicated by 93 is the execution number of the instruction sequence attached when the instruction sequence to be a loop is stored.

Next, the simulation operation in the case where the loop can be shortened by using the example of the specific application software shown in FIG. 9 will be described. Here, numbers such as 1 to 10 are attached to the beginning of the following description. This number is a number assigned to each group of processes, and is used later when the simulation operation is described using the application software of FIGS.

1. Normal simulation operation and loop search operation sequentially from the first instruction (steps S501 to S501)
Repeat step S506) up to the line indicated by * 2. 2. In the loop instruction table 105, "JMP" and "B
Assuming that “LT” is held, the instruction in the line of * 2 is the instruction “BL existing in the loop instruction table 105.
However, since the jump destination address is larger than the current address, it is determined that the loop is not formed (steps S503 and S504). Therefore, a normal simulation is performed here.

As in the case of 2, the instructions of the lines 3 and * 3 are also determined not to form a loop (step S50).
3, step S504). Therefore, a normal simulation is performed here. 4. Normal simulation operation and loop search operation are performed until the following * 1 is reached (steps S501 to S506).

The instruction "JMP" in the line of 5, * 1 is an instruction existing in the loop instruction table 105, and the jump destination address is smaller than the current address, so it is judged that a loop is formed (step S503, step S
504). At this time, the start address of the loop is add
It becomes r3, and the end address of the loop becomes * 1. 6. In the loop non-shortening instruction table 106, "MU
It is assumed that “L” is held. When it is determined that the loop is configured, the instruction “MU” held in the loop non-shortening instruction table 106 is included in the instructions in the loop.
It is determined whether "L" does not exist (step S50).
7, step S508). As a result of the judgment, the instruction "MU
Since L ”does not exist, the process proceeds to the next step.

7. Further, FIG. 18, in which the instructions are sequentially executed from the beginning of the loop, the instructions, the execution numbers, and the memory and register change history when the memory and registers are changed by the executed instruction are shown in FIG. As shown in FIG. 19, it is recorded for each execution of each instruction line (step S5).
09, step S517). The diagram in FIG. 18A shows the stored instruction and the change history of the memory and the register after the execution of the instruction indicated by the execution number 1. 181
The part indicated by is the instruction and the execution number saved in the execution number 1. Of these, 181a is the saved instruction,
181b is an execution number. The part indicated by 182 is a part where the change history of the memory should be saved. 1
The part indicated by 83 is the change history of the saved register. Of these, 183a is the name of the register accessed with execution number 1, 183b is the content of the register when the register was last accessed, and 183c is the content of the register when the register is accessed this time.
4d is an execution number. The diagram in FIG. 18 (b) is
After execution of the instruction indicated by execution number 2, the saved history and the change history of the memory and the register are shown. And 18
“→” shown in 5 and the like represents a pointer. Similarly, the diagrams in FIGS. 18 (c), (d), ..., 19 (g) show that after the execution of the instructions indicated by the execution numbers 3, 4, ... Indicates the change history. The change history of the memory is saved as shown in FIG. 182a is the name of the memory accessed with the execution number 6, 182b is the content of the memory when the memory was accessed last time, 182c is the content of the memory when the memory is accessed this time, 184d
Is the run number.

8. The loop is executed again to check whether the loop can be shortened (steps S518 and S519). In this example, it is determined that shortening is possible. 9. Calculate the number of loops that can be shortened (step S
520). In this example, the instruction to exit the loop is J in * 3.
MP command. Since the instruction before this JMP instruction is a conditional branch instruction, in order for the JMP instruction of * 3 to be executed, it is sufficient that the condition of the BLT instruction is not satisfied. B
The condition of the LT instruction is not satisfied unless the flag is negative, that is, Reg1 ≧ 100 in the CMP instruction.
If it is good. Therefore, since the content of Reg1 at execution number 7 is 3, the loop can be shortened 97 times.

10. Shorten the loop (step S)
521). Specifically, the contents of the memory and the register when it is assumed that the loop has been executed for the obtained number of times are predicted, the predicted contents are reflected in the current memory and register, and the loop is shortened. Then return to the normal simulation. Next, a simulation operation in the case where the loop cannot be shortened and executed by using a specific application software example shown in FIG. 10 will be described.

In the operation flow charts of FIGS. 4 and 5, the operations of steps S501 to S504 are performed in the same procedure as the explanations 1 to 5 of the simulation operation described with reference to FIG. 6. In the loop non-shortening instruction table 106, "MU
It is assumed that “L” is held. It is determined whether or not the instruction “MUL” held in the loop unreducible instruction table 106 exists among the instructions in the loop (steps S507 and S508). As a result of the judgment, since the instruction "MUL" exists in the portion indicated by 11, the process returns to step S505, and the normal simulation is performed from the instruction of Addr3, which is the head of the loop that was determined to be the loop.

Next, the simulation operation in the case where the loop cannot be shortened by using the example of the specific application software shown in FIG. 11 will be described. 4 and 5
Steps S501 to S in the operation flow chart of FIG.
The operation of 517 is performed in the same procedure as the description 1 to 7 of the simulation operation described with reference to FIG. After the end of 7, the executed instruction, the execution number, the change history of the memory and the register changed by the executed instruction, and the access history of the memory are recorded as shown in FIG.

8. The loop is executed again to check whether the loop can be shortened (steps S518 and S519). In the case of this example, the change rate of Mem1 in the previous execution is 2 as shown in the memory change history of FIG. When it is re-executed, the change rate of Mem1 becomes 3, so it is determined that shortening cannot be executed.

As described above, the loop instruction is detected,
The actual processing time of the loop can be shortened by setting the same state as in the case of the actual simulation without executing the loop the actual number of times. For example, in verification of application software using a timer, there are many cases in which a loop process waits until the time is up. Therefore, the operation can be confirmed without waiting for the actual time-up time by performing the loop up to the time-up time of the timer. That is, with the software simulator of the present invention, the operation verification of the application software, which waits for a few minutes or tens of minutes on the target, can be verified in a few seconds.

A software simulator according to the second embodiment of the present invention will be described below with reference to the drawings.
FIG. 21 shows the environment surrounding the configuration of the software simulator in the embodiment of the present invention. This figure shows
It is composed of a computer main body 110, a disk device 120, a keyboard 130, and a display 140. Since these are the same as those in the first embodiment, description thereof is omitted, and the software simulator 200 included in the computer main body 110 will be described.

The software simulator 200 has a first configuration except that an instruction execution unit 203 is provided in place of the instruction execution unit 103 of the first embodiment, and a loop shortening instruction information storage unit 210 is newly provided. Same as the embodiment. Only different configurations will be described below. As shown in FIG. 22, the loop shortening instruction information storage unit 210 stores a loop start address, a loop end address, a loop count calculation information address, and a pointer to the next element. Here, the loop count calculation information address is an address of information required when calculating the loop count. Specifically, the memory change history and the memory access history of the loop are held. An address in the history holding unit 107, an address in the register area 102 in which the register change history of the loop is held, and an address in the instruction sequence storage unit 104 in which the instruction sequence forming the loop is stored.

The instruction execution section 203 is a section for executing and shortening the instruction sequence of the target application software, and specifically, it is shown in the control flow charts of FIGS. 23 and 24. Since this control flow chart is almost the same as the control flow charts of FIGS. 4 and 5 in the first embodiment, only different points will be described. There are two differences. First, as a first point, step S5 in FIG. 4 of the first embodiment.
Below 04, a step S523 for determining whether the loop has been executed before is added. The second point is that step S522 is added below step S521. These steps will be described below.

First, in step S522, step S5
As for the loop that has been shortened in step 21, the loop start address, the loop end address, and the loop count calculation information address are stored in the loop shortening instruction information storage unit 210 in a list structure as shown in FIG. In step S523, it is determined whether the loop detected in step S504 has been executed before. The judgment is executed as follows. First, the start address and end address of the loop detected in step S504 are compared with the start address and end address stored in the loop shortening instruction information storage unit 210, respectively. If they do not match, the process proceeds to step S507. If they match, it is determined that the same loop has been executed before. When it is determined that the processing has been executed previously, the processing from step S507 to step S519 is skipped, and the process proceeds to step S520. Further, when the processing from step S507 to step S519 is skipped, the calculation of the loop count in step S520 uses the loop count calculation information address stored in the loop shortening instruction information storage unit 210 to calculate the loop count. Necessary information is extracted and the number of loops is calculated by the same method as in the first embodiment. Similarly, the shortened execution of the loop in step S521 is performed using the calculated loop count and the change rate of the memory and the register derived from the loop count calculation information address, assuming that the memory has been executed for the loop count. This is done by predicting the contents of the register and reflecting the prediction result in the current memory and register.

As described above, when the loop which has been shortened once is executed again, the execution time can be further shortened by omitting a part of the shortening process. A software simulator according to the third embodiment of the present invention will be described below with reference to the drawings. FIG. 25 shows the environment surrounding the configuration of the software simulator in the embodiment of the present invention. This figure shows a computer main body 110, a disk device 120, and a keyboard 13.
0 and a display 140. Since these are the same as those in the first embodiment, description thereof will be omitted, and the software simulator 300 included in the computer main body 110 will be described.

The software simulator 300 has the same configuration as that of the first embodiment except that an instruction execution unit 303 is provided instead of the instruction execution unit 103 of the first embodiment, and an interrupt processing unit 307 and a time management unit 306 are newly provided. It is the same as the implementation of 1. Only different components will be described below. The interrupt processing unit 307 simulates an interrupt operation on the simulator.

The time management unit 308 manages the interrupt generation time when simulating the interrupt operation, and activates the interrupt processing unit 307 when the interrupt generation time is reached. The instruction execution unit 303 is a unit that executes and shortens the instruction sequence of the target application software,
Specifically, it is shown in the control flow charts of FIGS. Since this control flow chart is almost the same as the control flow charts of the first embodiment shown in FIGS. 4 and 5, only different points will be described. Step S52 in the control flow chart of FIG.
The difference is that the processing steps of steps S1301 to S1305 are added between 0 and step S521. These processing steps will be described below.
First, the number of loops until the loop end condition calculated by the same method as step S520 in the first embodiment is satisfied is calculated (step S520). Then, it is determined whether there is an interrupt process by referring to the time management unit 308 (step S1301). here,
If there is no interrupt processing, the number of loops until the loop end condition is satisfied is set to the number of loops that can be shortened and the process proceeds to step S521 (step S1305).
If interrupt processing is present, the number of loops until the occurrence of an interrupt is calculated (step S1302) and compared with the number of loops until the loop end condition is satisfied (step S1303). Here, the number of loops until the interrupt is generated in step S1302 is obtained based on the interrupt generation time managed by the time management unit 308 and the time required for one loop. If the number of loops until the interrupt is generated is smaller than the number of loops until the loop end condition is satisfied, step S521 is executed as the number of times that the number of loops until the interrupt is generated can be shortened (step S521). S1304).
If not, that is, if the number of loops until the loop end condition is satisfied is smaller, this number is set as the number of loops that can be shortened and the process proceeds to step S521 (step S1305).

Next, the simulation operation when the loop can be shortened by using the example of the specific application software shown in FIG. 12 will be described. 26 and FIG.
In the operation flow chart of FIG. 7, the operations of steps S501 to S519 are performed in the same procedure as the descriptions 1 to 8 of the simulation operation described with reference to FIG. Further, the executed instruction, the execution number, the change history of the memory and the register when the memory and the register are changed by the executed instruction, and the access history of the memory are recorded as shown in FIG.

9. The number of loops that can be shortened is calculated (steps S520 to S1305). Specifically, first, the number of loops until the loop end condition is satisfied is calculated (step S520). In this case, since the loop is infinite, an appropriate value of 500 is regarded as the number of loops until the loop end condition is satisfied. Next, the time until the interrupt occurrence managed by the time management unit 308 is 100
If it is 0 cycle and the time required to loop once is 5 cycles, the number of loops until the interrupt is generated is calculated to be 200 (steps S1301 and S1302). Next, comparing the number of loops until the loop end condition is satisfied with the number of loops until an interrupt occurs, the number of times until an interrupt occurs is smaller, so it is determined that an interrupt will occur first, and The number of loops is set to the number of loops that can be shortened (steps S1303 and S1304). At this time, the number of loops up to the occurrence of an interrupt is 200, but the number of times that can be shortened is set to 199. The reason is that if it is set to 200 times, an interrupt occurs at the same time when the loop shortening is executed, so that it is prevented.

10. Shorten the loop (step S)
521). Specifically, the contents of the memory and the register when it is assumed that the loop has been executed for the obtained number of times are predicted, the predicted contents are reflected in the current memory and register, and the loop is shortened. Then return to the normal simulation. As described above, even when an interrupt occurs during looping, the loop is shortened until the interrupt occurs, and when the interrupt occurs, normal simulation processing is resumed, so that the interrupt is generated correctly even when the interrupt occurs. The process can be simulated and the loop can be shortened.

A software simulator according to the fourth embodiment of the present invention will be described below with reference to the drawings.
FIG. 29 shows the environment surrounding the configuration of the software simulator in the embodiment of the present invention. This figure shows
It is composed of a computer main body 110, a disk device 120, a keyboard 130, and a display 140. Since these are the same as those in the first embodiment, description thereof is omitted, and the software simulator 400 included in the computer main body 110 will be described.

The software simulator 400 has a configuration in which an instruction execution unit 403 is provided instead of the instruction execution unit 103 of the first embodiment, and an I / O processing unit 407 and a time management unit 408 are newly provided. Is the same as the first implementation. Only different components will be described below.
The I / O processing unit 407 simulates an I / O event on the simulator.

The time management unit 408 manages the time until the I / O event occurs, and activates the I / O processing unit 407 at the time when the I / O event occurs. The instruction execution unit 403 is a portion that executes and shortens the instruction sequence of the target application software, and is specifically shown in the control flow charts of FIGS. 30 and 31. This control flow chart is the control flow chart of the first embodiment shown in FIG.
Since it is almost the same as FIG. 5, only different points will be described. The difference is that the processing steps of steps S1501 to S1505 are added between step S520 and step S521 in the control flow diagram of FIG. These processing steps will be described below. First, the number of loops until the loop end condition calculated by the same method as step S520 in the first embodiment is satisfied is calculated (step S520). Then, it is determined whether or not there is an I / O event by referring to the time management unit 408 (step S1501). Where I
When there is no / O event, the number of loops until the loop end condition is satisfied is set to the number of loops that can be shortened, and step S521 is executed (step S150).
5). If an I / O event exists, the number of loops until the I / O event occurs is calculated (step S150
2) Compare with the number of loops until the loop end condition is satisfied (step S1503). Here step S1
The number of loops until the occurrence of an I / O event in 502 is calculated based on the time until the occurrence of the I / O event managed by the time management unit 408 and the time required for one loop. If the number of loops until the I / O event occurs is smaller than the number of loops until the loop end condition is satisfied, the number of loops until the I / O event occurs is shortened to Execute S521 (step S130)
4). If not, that is, if the number of loops until the end condition is satisfied is smaller, this number is set as the number of loops that can be shortened, and the process proceeds to step S521 (step S1305).

Next, the simulation operation when the loop can be shortened by using the example of the specific application software shown in FIG. 13 will be described. 30 and 3
In the operation flow chart of FIG. 1, the operations of steps S501 to S519 are performed in the same procedure as the description 1-8 of the simulation operation described with reference to FIG. Further, the executed instruction, the execution number, the change history of the memory and the register when the memory and the register are changed by the executed instruction, and the memory access information are recorded as shown in FIG.

9. The number of loops that can be shortened is calculated (steps S520 to S1505). Specifically, first, the number of loops until the loop end condition is satisfied is calculated (step S520). In this case, since it becomes an infinite loop, the number of loops cannot be measured and an appropriate value 50
0 times is regarded as the number of loops until the loop end condition is satisfied. Next, the I / O managed by the time management unit 408
If the time until the event occurs is 1000 cycles and the time required to loop the instruction string of the loop once is 10 cycles, the number of loops until the interrupt occurs is calculated to be 100 (step S1501, Step S1502). Next, comparing the number of loops until the loop end condition is satisfied with the number of loops until the I / O event occurs, the number of times until the I / O event occurs is smaller, so the I / O event comes first. When it is determined that the I / O event occurs, the number of loops until the I / O event occurs is set to the number of loops that can be shortened (steps S1503 and S1504). At this time, the number of loops until the occurrence of the I / O event is 100, but the number of times that can be shortened is set to 99. The reason is that when set to 100 times, the I / O event is prevented from occurring at the same time when the loop shortening is executed.

As described above, even when an I / O event occurs in the loop, the loop is shortened until the I / O event occurs, and when the I / O event occurs, the normal simulation process is resumed. The simulation can be executed correctly and the loop can be shortened. In addition,
Since only the typical instructions are used, it is naturally conceivable to use other instructions.

The instructions stored in the loop instruction table and the loop non-shortening instruction table are not limited to the illustrated instructions. Although the simulation is performed using the assembly language, it is also possible to use another language.

As described above, according to the present invention, the loop detection means detects a loop, and the shortened execution determination means determines whether or not the loop can be shortened.
Since the loop state is shortened by the register content changing means, the execution time of the application software on the software simulator can be shortened.

Further , according to the present invention, the loops that can be shortened are detected by using the loop instruction table and the loop non-shortening instruction table. Therefore, the loops that can be shortened can be detected quickly, and the loop can be detected on the software simulator. The execution time of application software can be shortened. Further, according to the present invention, whether or not the loop can be shortened by using the instruction sequence storage unit in which the re-executed instruction sequence is stored, the memory content holding unit, the register content holding unit, and the history holding unit is loop shortened execution. Since it is determined by the possibility determination unit, the loop can be executed more accurately and the execution time of the application software on the software simulator can be shortened.

Further , in the present invention, the execution number calculation unit calculates the number of loops, and based on the number of times, the changing unit predicts the contents of the memory and the register when it is assumed that the loop number of times has been executed, and the result is Since it is reflected in the memory content holding means and the register content holding means, the state becomes the same as the state executed by the number of loops, the loop is executed more accurately and the execution time of the application software on the software simulator can be shortened. it can.

Further , according to the present invention, when the loop is executed in a shortened manner, the start address and end address of the instruction sequence and the loop count calculation information address are stored by the loop information holding means, and the loop count is detected when the loop is detected. Whether or not the loop is re-executed can be determined using the calculated information address. If the loop is re-executed, the processing after the detection of the loop, and the processing before the calculation of the number of loops can be omitted. Since the processing required for shortening the loop can be simplified, the execution time of the application software can be further shortened.

Further , in the present invention, the number of loops that can be shortened is determined by the interrupt loop number determining means based on the interrupt generation time managed by the interrupt time managing means, and the loop is executed based on the determined loop number. Because it can be executed in a short time , software simulation can be performed even when interrupt operation is simulated.
It is possible to reduce the execution time of the application software on over data.

Further , in the present invention, the number of loops that can be shortened is determined by the I / O event loop number determining means based on the I / O event occurrence time managed by the I / O event time managing means. Since the loop can be shortened based on the number of loops,
Even when I / O events are simulated,
The execution time of application software on the software simulator can be shortened.

[Brief description of drawings]

FIG. 1 is a diagram showing a software simulator and an environment surrounding a software simulator in a first embodiment.

FIG. 2 is a diagram showing a loop instruction table 105.

FIG. 3 is a diagram showing a loop non-shortening instruction table 106.

FIG. 4 is a diagram showing a control flow of an instruction execution unit 103.

FIG. 5 is a continuation of FIG. 4;

FIG. 6 is a diagram showing a storage format in an instruction sequence storage unit 104.

7 is a diagram showing a memory change history in a history holding unit 107. FIG.

8 is a diagram showing a register change history in the history holding unit 107. FIG.

FIG. 9 shows an example of target application software to be simulated.

FIG. 10 is an example of target application software to be simulated.

FIG. 11 is an example of target application software to be simulated.

FIG. 12 is an example of target application software to be simulated.

FIG. 13 is an example of target application software to be simulated.

FIG. 14 is a table showing the definition of an instruction used in application software.

FIG. 15 is a diagram for explaining a transfer instruction.

FIG. 16 is a diagram for explaining an arithmetic operation instruction.

FIG. 17 is a diagram for explaining a compare / jump instruction.

FIG. 18 is a diagram showing a change history of a memory and a register.

FIG. 19 is a view illustrating a sequel to FIG. 18;

FIG. 20 is a diagram showing a memory and register change history and a memory access history.

FIG. 21 is a diagram showing a software simulator and an environment surrounding the software simulator in the second embodiment.

FIG. 22 is a diagram showing contents stored in a loop shortening instruction information storage unit 210.

FIG. 23 is a diagram showing a control flow of the instruction execution unit 203.

FIG. 24 is a view illustrating a sequel to FIG. 23;

FIG. 25 is a diagram showing a software simulator and an environment surrounding the software simulator in the third embodiment.

FIG. 26 is a diagram showing a control flow of the instruction execution unit 303.

FIG. 27 is a view illustrating a sequel to FIG. 26;

FIG. 28 is a diagram showing a memory and register change history and a memory access history.

FIG. 29 is a diagram showing a software simulator and an environment surrounding the software simulator in the fourth embodiment.

FIG. 30 is a diagram showing a control flow of the instruction execution unit 403.

FIG. 31 is a view illustrating a sequel to FIG. 30;

FIG. 32 is a diagram showing a memory and register change history and a memory access history.

[Explanation of symbols]

110 computer 100 software simulator 101 memory area 102 register area 103 instruction execution unit 104 instruction string storage unit 105 loop instruction table 106 Loop non-shortening instruction table 120 disk unit 130 keyboard 140 display 200 software simulator 203 instruction execution unit 210 Loop shortening instruction information storage unit 300 software simulator 307 Interrupt processing unit 308 Time Management Department 400 software simulator 403 Command execution unit 407 I / O processing unit 408 hour management department

Continuation of the front page (56) Reference JP 62-194549 (JP, A) JP 63-58550 (JP, A) JP 1-1599743 (JP, A) JP 7-295832 (JP , A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) G06F 11/28 G06F 9/44 G06F 9/455

Claims (20)

(57) [Claims] 1. A software simulation apparatus for executing an application software in a pseudo manner to data Getto, by the address of the instruction is previously executed address to be executed next is executed to the next A detection unit that detects the instruction sequence having the address of the instruction as the start address and the current address as the end address from the application software, and shortens the instruction sequence detected by the detection unit without faithfully simulating A shortened execution determination means for determining whether or not it can be executed, and an instruction sequence determined to be shortened and executed by the shortened execution determination means are shortened and executed to perform a faithful simulation. And a shortening execution means for shortening the processing time. Simulation apparatus. Wherein said software simulation apparatus <br/> further that holds the potential is instructions constituting the instruction sequence
Instruction includes a table, before dangerous out means, the current instruction address is present in the instruction table, and,
By the address of the instruction to be executed next the instruction is smaller than the address of the instruction, a further address the address of the instruction previously executed to be executed next, previous
Software simulation apparatus according to claim 1, characterized in that to detect the serial instruction stream. 3. A software simulation apparatus for performing pseudo application software to data Getto, to be present within the instruction sequence, the instruction sequence, to be executed by shortening without faithfully simulate A non-shortenable instruction table that holds instructions that cannot be executed, a detection unit that detects an instruction sequence to be determined, and an instruction that is held in the non-shortenable instruction table among the instruction sequences detected by the detection unit. Whether or not exists, and if it does not exist, the instruction sequence is shortened by the shortening execution determining unit that determines that the instruction sequence can be shortened and executed without faithfully simulating, and shortened by the shortening execution determining unit. Faithfully simulate by shortening and executing the instruction sequence that is determined to be executed And a shortening execution unit that shortens the processing time. 4. A software simulation apparatus for performing pseudo application software to data Getto, to be present within the instruction sequence, the instruction sequence, to be executed by shortening without faithfully simulate A non-shortenable instruction table that holds instructions that cannot be executed, a detection unit that detects an instruction sequence to be determined, and an instruction that is held in the non-shortenable instruction table among the instruction sequences detected by the detection unit. Is present, when the instruction sequence detected by the detection means is executed again, when an instruction not previously executed is executed this time, and when the contents of the memory or the register are updated, Based on the changes in the contents of the memory and registers when it was executed last time and the changes in the contents when this time was executed, If the change in the contents of the register cannot be predicted, or if there is an instruction that has not been executed both last time and this time and that may change the contents of the memory or register, A shortened execution determination unit that determines that the instruction sequence cannot be shortened and executed without faithfully simulating; and the detection unit that is detected and that the shortened execution determination unit determines that the instruction sequence cannot be shortened and executed. A software simulation device, comprising: a shortening execution unit that shortens a processing sequence that is shorter than a faithful simulation by shortening and executing an unsuccessful instruction sequence. 5. A software simulation apparatus for performing pseudo application software to data Getto, a memory change history is altered history memory, and registers the change history is altered history register, A history holding unit that holds a memory access history that is a history of memory access, a loop detection unit that detects a loop that can be executed in a shortened manner from the application software, and a memory or register contents A change rate calculating means for calculating a change rate, which is a rate of change in the contents of the memory and the register when updated, and a condition for exiting a loop which can be executed in a shortened manner detected by the loop detecting means. Then, the calculated condition, the memory change history and the register change held in the history holding means. Based on history and memory access history
Based on the loop execution number calculation means for calculating the number of loops until the loop is terminated, the change rate calculated by the change rate calculation means, and the loop number calculated by the loop execution number calculation means, the loop Is executed for the number of loops, the contents of the memory and the register are predicted, and the result is reflected in the contents of the memory content holding means and the register content holding means to detect the loop detected by the loop detection means. A software simulation device comprising: a shortening execution unit that shortens the processing time by performing the simulation in a shorter time than the faithful simulation. Wherein said software simulation apparatus <br/> is the further, the instruction sequence constituting once for short loop is executed, the start address and the end address, required to calculate the number of loops and loop information storage means for storing the number of loops calculation information is information, when a loop is detected by the loop detecting unit, search
The start address of the issued loop and end address, the head address stored in the loop information storage means the end
Compare each with the address, and if they match, the same loop
A loop re-execution judging means for judging that the loop has been executed before, and the loop execution count calculating means has previously executed the same loop by the loop re-execution judging means.
If it is determined that using the loop count calculation information
Software simulation apparatus according to claim 5, characterized in that to calculate the number of loops that can be shortened. Wherein said software simulation apparatus <br/> is a further, and the interruption processing means for simulating an interrupt operation, and manages the interrupt occurrence time when simulating an interrupt operation, interrupt generation time and interrupt time managing means for simulating an interrupt operation to the said interrupt processing means, and an interrupt generation time managed by the interrupt time managing means, based on the time required to loop once or interrupted compares the interrupt occurrence count calculating means for calculating a loop times remaining before the loop count calculated by the loop execution frequency calculation unit, and a <br/> loop count calculated by the interrupt occurrence count calculating means, the number of loops of the smaller, shorten
Any claim 5 and claim 6, characterized in that Ru and an interrupt loop number determination means shall be the number of loops that can be
Or software simulation apparatus according to item 1. Wherein said software simulation apparatus <br/> is a further, and I / O event processing means of simulating I / O events, manages the time until I / O event occurs hand,
I / O event to simulate the I / O event to the I / O event processing means it is time to generate I
/ A O event time management means, time to I / O event occurs that is more manageable to the I / O event time management means,必to loop once
Based on the main time, and I / O event occurrence count calculating means for calculating a loop times remaining before I / O event occurs, the loop number which is calculated by the loop execution frequency calculation unit, the I / Calculated by O event occurrence frequency calculation means
Has been compared with the number of loops, the number of loops lesser claim 5 and claim, characterized in that Ru and an I / O loop number determination means shall be the number of loops that can be shortened 6
Software simulation instrumentation according to any one of
Place 9. Executing instructions used in a program
An instruction execution device for Program storage means for storing the program, In the program stored in the program storage means
Execute the given instruction sequence in
A change that is the rate of change in the content of the execution result when it is executed twice.
Based on the conversion rate, the content of the execution result of the predetermined instruction sequence is
Instruction execution, characterized in that it comprises an executing means for predicting
apparatus. 10. The executing means comprises: Based on the number of executions of the predetermined instruction sequence in addition to the rate of change
Assuming that the predetermined instruction sequence has been executed that number of times,
Prediction means for predicting the content of the execution result when A short whose execution result is the content predicted by the prediction means.
10. The contraction executing means is included.
Instruction execution unit. 11. The executing means comprises: Re-execute the specified instruction sequence, and change the previous instruction
Determine whether the conversion rate and the change rate when executed this time are different.
If the rate of change is different, it is determined that shortening cannot be performed.
10. The shortening execution determination means is included.
11. The instruction execution device according to any one of 1 to 10. 12. The shortening execution determination means further comprises: If an instruction that was not executed previously is executed this time, and
It was an instruction that was not executed either last time or this time.
And there is an instruction that may change the content of the execution result.
If it does, it is determined that it cannot be shortened.
The instruction execution device according to claim 11, further comprising: 13. The instruction execution device further comprises: Holds instructions that may form the predetermined instruction sequence
Equipped with an instruction table, The execution means further comprises The executed instruction exists in the instruction table and its life is
The address of the instruction to be executed after the
Is smaller than the address of the command, and is the life to be executed next.
If the address of the decree is an address that was previously executed
And then run Start address
And the address of the executed instruction is the final address.
Detecting means for detecting the instruction sequence as the predetermined instruction sequence
It is included in any one of Claims 9-12 characterized by including.
Instruction execution device. 14. The execution means further comprises Detect the instruction sequence that forms a loop as the predetermined instruction sequence
13. The detecting device according to claim 9, further comprising:
The instruction execution device according to any one of claims. 15. Used for stored programs
An instruction execution method for executing an instruction, Predetermined instruction sequence in the stored program
And the previous execution of the specified instruction sequence
Based on the rate of change, which is the rate of change in the content of the result,
Execution step for predicting the content of the execution result of a predetermined instruction sequence
An instruction execution method comprising: 16. The executing step comprises: Based on the number of executions of the predetermined instruction sequence in addition to the rate of change
Assuming that the predetermined instruction sequence has been executed that number of times,
Prediction substep that predicts the content of the execution result when
When, Execution result of the content predicted by the prediction sub-step
And a shortened execution sub-step
The instruction execution method according to claim 15. 17. The executing step comprises: Re-execute the specified instruction sequence, and change the previous instruction
Determine whether the conversion rate and the change rate when executed this time are different.
If the rate of change is different, it is determined that shortening cannot be performed.
A contract characterized by including a shortened execution determination sub-step
The instruction execution method according to any one of claim 15 and claim 16. 18. The shortening execution determination sub-step comprises:
In addition, If an instruction that was not executed previously is executed this time, and
It was an instruction that was not executed either last time or this time.
And there is an instruction that may change the content of the execution result.
If it does, it is determined that it cannot be shortened Characterized by
18. The instruction execution method according to claim 17, wherein 19. The executing step further comprises: It is possible that the executed instructions may form the predetermined instruction sequence.
It exists in the instruction table that holds an instruction and
The address of the instruction to be executed next to
Less than the address of the instruction
If the address of the instruction to be executed is the previously executed address,
If the address of the next instruction to be executed is
The address of the executed instruction as the final address
To detect the instruction sequence to be executed as the predetermined instruction sequence
What is claimed in claims 15-18, characterized in that it comprises steps.
The instruction execution method according to item 1. 20. The execution step further includes Detect the instruction sequence that forms a loop as the predetermined instruction sequence
2. A sub-step of detecting is included.
The instruction execution method according to any one of 5 to 18.