JP5412900B2 - Embedded program simulator and simulation method - Google Patents

Description

  The present invention relates to an embedded program simulator and simulation method.

  When debugging an embedded program, a simulator of a target processor is often used on a computer device such as a PC while the target hardware system is incomplete.

  The embedded program usually includes an input / output operation between the processor and its peripheral devices. In order to simulate the operation of the peripheral device, for example, a simulator for the peripheral device is separately created, or a mechanism for predefining the behavior in the simulator of the target processor is incorporated. is there.

  However, it takes considerable effort to create a mechanism for predefining the behavior for these peripheral devices. If there is no such mechanism, in debugging the program under development, the program is temporarily broken at the instruction part related to input / output with the peripheral device, and then the values of various variables and the program counter are changed. There is a need. In particular, in the case of a program that loops and waits on the condition of the peripheral device as a condition, if such a change is not forced, the program falls into an infinite loop and the program cannot proceed.

  Patent Documents 1 and 2 disclose a technique for detecting a conditional branch portion by defining the operation of a peripheral device and analyzing a processor instruction without executing a program. A technique for defining the operation of a peripheral device and executing a program simulation is disclosed in Patent Document 2. In any case, it is necessary to preliminarily specify the operation of the peripheral device. In the techniques of Patent Documents 1 and 2, the program is not executed. Therefore, in a program that spans multiple source files using indirect addressing, Detection of input / output with the device may be missed.

  The present invention automatically detects a loop portion having a peripheral device state as a waiting condition, sets the peripheral device state on the program to a state that exits the loop, and allows the development program to proceed. The purpose is to provide a simulator for the program.

The present invention has been made to achieve the above object. The simulator according to claim 1 according to the present invention includes:
In a simulator of an embedded program that simulates the operation of the target processor on another computer and detects a conditional branch portion by an instruction of the target processor.
When simulating the programming part that advances the processing based on the status of the peripheral device when inputting / outputting data with the peripheral device connected to the target processor, the combination of instructions of the target processor and its effective address Means for detecting a waiting portion related to data input / output with a peripheral device in the embedded program according to
Means for rewriting the internal register value of the target processor indicating the state of the peripheral device.

The simulator according to claim 2 according to the present invention includes:
The means for detecting the waiting portion is
A combination of a conditional branch instruction and its branch destination address, and an input / output instruction whose effective address is the peripheral device area based on the memory space information of the program area, data area, and peripheral device area specified by the target processor The simulator according to claim 1, wherein the simulator is a means for detecting that is used as a condition.

The simulator according to claim 3 according to the present invention,
The means for detecting the waiting portion is
If the target processor has a dedicated input / output instruction for the peripheral device,
2. The simulator according to claim 1, wherein said simulator is a means for detecting on condition that said peripheral input / output instruction is used together with a combination of a conditional branch instruction and its branch destination address.

The simulation method according to claim 4 according to the present invention includes:
In the simulation method of simulating the operation of the target processor on another host computer, and detecting the conditional branch portion by the instruction of the target processor,
When simulating the programming part that advances the processing based on the status of the peripheral device when performing data input / output with the peripheral device connected to the target processor , the combination of the target processor 's instructions and its effective address A step of detecting a waiting portion related to input / output of data with a peripheral device in the embedded program related to the programming portion ;
Rewriting the internal register value of the target processor indicating the state of the peripheral device, and exiting the waiting portion.

  By utilizing the present invention, in the simulator for the embedded program, automatically detects the loop part having the peripheral device state as a waiting condition, and sets the state of the peripheral device on the program to a state out of the loop, The development program can be advanced.

It is an example of the memory space in the processor in which the installation program to be developed by the simulator according to the present invention actually operates. It is an example (1) of the program simulated with the simulator which concerns on this invention. It is an example (2) of the program simulated with the simulator which concerns on this invention. It is an example (3) of the program simulated with the simulator which concerns on this invention. It is an example (4) of the program simulated with the simulator which concerns on this invention. It is an example (5) of the program simulated with the simulator which concerns on this invention. It is a flowchart which shows operation | movement of the simulator based on this invention which detects the loop part by the state of a side apparatus. The operation content of the instruction described in the program shown in FIGS.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments according to the invention will be described with reference to the drawings. The present invention relates to a processor simulator for developing an embedded program, and operates on a computer device such as a PC.

  FIG. 1 shows an example of a memory space 1 in a processor in which an embedded program to be developed by a simulator according to the present invention is actually operated. The total memory space is 64 Kbytes, addresses 0h to 1FFFh are the peripheral device area 2, 2000h to 7FFFh are the data RAM area 4, and 8000h to FFFFh are the program area 6 (“h” is 16). Indicates a decimal number).

  In accordance with this memory space, the processor simulator according to the present invention can determine which area the effective address of each instruction targets when simulating each instruction. This processor is premised on having a status register indicating the state of the operation result. This status register includes a zero flag that is set to “1” when the operation result is 0, a negative flag that is set to “1” when the result is a negative number, and the like.

  2 to 6 are examples of programs that are simulated by the simulator according to the present invention. FIG. 8 shows the operation content of instructions described in the program.

  The program example shown in FIG. 2 loads the value from the port representing the state of the peripheral device, and returns to the previous address when the condition is satisfied in the conditional branching based on the value. The program example shown in FIG. 3 branches to a later address if the same conditional branch satisfies the condition. The program example shown in FIG. 4 similarly branches to a subsequent address if the condition is satisfied, but there are further conditional branches if the condition is not satisfied, and returns to the previous if the condition is satisfied.

  The program example shown in FIG. 5 has substantially the same contents as those in FIG. 2, except that the peripheral device address is indirectly specified. The program example shown in FIG. 6 has almost the same contents as those in FIG. 4, but differs from FIG. 4 in that there is an unconditional branch after the first conditional branch.

  First, the operation of the simulator according to the present invention will be described with reference to the program example shown in FIG. In FIG. 2, the conditional branch instruction (a) returns before the condition is satisfied. If the instruction that manipulated the flag condition to be referred to in the conditional branch is retrieved retroactively, it can be seen that the instruction is the previous and instruction. The register to be compared by this and instruction is the g0 register. Further, it can be seen that data is loaded back into the g0 register in the previous ld instruction. In addition, it can be seen that the effective address of the ld instruction is in the peripheral device area. In other words, it can be seen that the above conditional branch instruction is conditional on the state of the peripheral device, and the branch destination is an address before the instruction group searched above is executed again. If the conditional branch remains established, the block portion of is found to fall into an infinite loop.

  At this time, the simulator according to the present invention changes the value of g0 targeted by the and instruction, and sets the value so that the condition is not satisfied and the loop is exited. In the example of FIG. 2, g0 may be set to 10h, for example.

  If data loading from the peripheral device area is not detected even after going back to the conditional branch destination address, the detection operation ends there. That is, since this conditional branch is not based on the state of the peripheral device, the simulator according to the present invention does not manipulate the register value.

  In the example of the program shown in FIG. 5, the data load to the g0 register is an indirect address by the g3 register, but from the effective address, the data load from the peripheral device area is performed by the method for the example of FIG. Becomes clear. When the address is set to the g3 register in one source file as shown in FIG. 5, the above-described finding is possible only by the conventional technique for analyzing the source file without executing by the simulator. However, for example, when an address is set to the g3 register in another source file, the above-described determination is impossible only by the conventional technique for analyzing the source file. On the other hand, the simulator according to the present invention can be identified by the method for the example of FIG. 2 even when the address setting to the g3 register is performed by another source file.

  In the example of the program shown in FIG. 3, since the branch destination address of the conditional branch instruction (b) is behind and there is neither a conditional branch instruction nor an unconditional branch instruction until the branch destination address, the instruction (b) And the branch destination address do not become an infinite loop. Therefore, in the program example shown in FIG. 3, it is not necessary for the simulator according to the present invention to operate the register value.

  However, as in the example of the program shown in FIG. 4, although the branch destination address of the conditional branch instruction in (c) is behind, the conditional branch that returns to the front address as in (d) until that branch destination address. When there is an instruction, there is a possibility of falling into an infinite loop depending on the condition (d) as in the example of the program shown in FIG. In this case, contrary to FIG. 2, the value of the g0 register is changed so that the condition of the conditional branch instruction of (c) is satisfied, so that it does not proceed to the conditional branch part of (d). Here, for example, the value of the g0 register may be set to 0h.

  Further, as in the example of the program shown in FIG. 6, although the branch destination address of the conditional branch instruction (f) is behind, there is an unconditional branch instruction as shown in (g) between the branch destination addresses. If it returns to an address ahead of (f), the value of the g0 register is changed so that the condition of (f) is satisfied, as in the example of the program shown in FIG. Here, for example, the value of the g0 register may be set to 0h.

  As described above, the simulator according to the present invention, when a conditional branch instruction is detected, the branch destination is an address ahead of it, and the load from the peripheral device area between the front branch address and the conditional branch instruction. If the condition is determined based on the value, it is determined that the block portion between the front address and the conditional branch instruction is a loop portion waiting for the state of the peripheral device. Here, the simulator according to the present invention forcibly changes the target register value by the conditional branch instruction so that the condition does not hold so that the loop portion does not fall into an infinite loop, exits the loop, Proceed with debugging the program.

  Further, the simulator according to the present invention, when detecting a conditional branch instruction, the branch destination is an address behind it, and an unconditional branch instruction that returns to the front address between the conditional branch instruction and the backward address Or, there is a conditional branch instruction, and the first conditional branch instruction makes a conditional judgment based on the load value from the peripheral device area between the unconditional branch instruction or the conditional branch instruction from the front address. For example, it is determined that the block portion between the above-described forward address and the unconditional branch instruction or the conditional branch instruction is a loop portion that waits for the state of the peripheral device. Here, the simulator according to the present invention forcibly changes the register value that is the target in the first conditional branch instruction so that the loop part does not fall into an infinite loop, and exits the loop, Proceed with debugging the target program.

  FIG. 7 is a flowchart showing the operation of the simulator according to the present invention for detecting a loop portion according to the state of the peripheral device.

  First, an instruction is acquired (S04). If it is not a conditional branch instruction (NO in S06), the next instruction is acquired. If it is a conditional branch instruction (S06: YES), it is determined whether the branch destination is forward or backward (S08). If the branch destination is forward, the process proceeds to S10, and if the branch destination is backward, the process proceeds to S20.

  First, the case where the branch destination is ahead will be described. If the branch destination is ahead, the previous instruction is acquired (S10). It is determined whether this instruction is a change instruction of a flag used in the conditional branch instruction (S12). If it is a change instruction of the flag used in the conditional branch instruction (S12, YES), the process proceeds to S14. If it is not a change instruction for the flag used in the conditional branch instruction (NO in S12), the previous instruction is acquired. If the acquisition of the previous instruction is repeated and the process returns to the position before the branch destination address, an infinite loop does not occur in this block, so the process returns to “A” in the flow to acquire the next instruction.

  In S14, a previous command is acquired, and it is determined whether this command is related to data reading from the peripheral device (S16). If it is related to data reading from the peripheral device (YES at S16), the process proceeds to S18. If it is not related to data reading from the peripheral device (NO in S16), the previous command is acquired. If the acquisition of the previous instruction is repeated and the process returns to the position before the branch destination address, an infinite loop does not occur in this block, so the process returns to “A” in the flow to acquire the next instruction.

  In S18, the register value of the flag used in the conditional branch instruction is rewritten so that the conditional branch is not established. Thereafter, the process proceeds to S04, and the instruction acquisition is continued.

  Next, a case where the branch destination is backward will be described. If the branch destination is backward, the next instruction is acquired (S20). It is determined whether this instruction is a conditional branch instruction or an unconditional branch instruction, and whether or not to branch to an address ahead of the first conditional branch instruction (S22). If “this instruction is a conditional branch instruction or an unconditional branch instruction and branches to an address ahead of the first conditional branch instruction” (YES at S22), the process proceeds to S24. If “this instruction is a conditional branch instruction or an unconditional branch instruction and branches to an address ahead of the first conditional branch instruction” (S22 / NO), the next instruction is further acquired. If the acquisition of the next instruction is repeated until the branch destination address is reached, an infinite loop does not occur in this block, so the flow returns to “A” in the flow to acquire the next instruction.

  In S24, the previous instruction is acquired based on the first conditional branch instruction (S24). It is determined whether this instruction is a change instruction of a flag used in the conditional branch instruction (S26). If it is a change instruction of a flag used in the conditional branch instruction (S26 / YES), the process proceeds to S28. If it is not a change instruction of the flag used in the conditional branch instruction (NO in S26), the previous instruction is acquired. If the acquisition of the previous instruction is repeated and the process returns to the position before the branch destination address, an infinite loop does not occur in this block, so the process returns to “A” in the flow to acquire the next instruction.

  In S28, the previous command is acquired, and it is determined whether this command is related to data reading from the peripheral device (S30). If it is related to data reading from the peripheral device (S30, YES), the process proceeds to S32. If it is not related to data reading from the peripheral device (S30, NO), the previous command is acquired. If the acquisition of the previous instruction is repeated and the process returns to the position before the branch destination address, an infinite loop does not occur in this block, so the process returns to “A” in the flow to acquire the next instruction.

  In S32, the register value of the flag used in the conditional branch instruction is rewritten so that the conditional branch is not established. Thereafter, the process proceeds to S04, and the instruction acquisition is continued.

  When the instruction has been acquired to the end in S04, the entire process is completed.

  The simulator according to the present invention described above is not limited to the above-described content. For example, in the determined loop part, the corresponding register value is set so as to execute the loop for an arbitrary number of times, rather than exiting without executing the loop, and then the register value is changed to change the loop. You may make it escape. Such a setting can be used for adjusting the timing of program execution.

  Further, if the target processor has an input / output instruction dedicated to the peripheral device, it is possible to detect the loop part and control the execution of the loop part using the instruction itself instead of the effective address described above. .

DESCRIPTION OF SYMBOLS 1 ... Memory space, 2 ... Peripheral device area | region, 4 ... Data RAM area | region, 6 ... Program area | region.

Japanese Patent Publication No. 8-20972 Japanese Patent Publication No. 8-20973 JP 2004-94800 A

Claims (4)

In a simulator of an embedded program that simulates the operation of the target processor on another computer and detects a conditional branch portion by an instruction of the target processor.
When simulating the programming part that advances the processing based on the status of the peripheral device when inputting / outputting data with the peripheral device connected to the target processor, the combination of instructions of the target processor and its effective address Means for detecting a waiting portion related to data input / output with a peripheral device in the embedded program;
A simulator comprising means for rewriting an internal register value of a target processor indicating the state of the peripheral device and exiting the waiting portion. The means for detecting the waiting portion is
A combination of a conditional branch instruction and its branch destination address, and an input / output instruction whose effective address is the peripheral device area based on the memory space information of the program area, data area, and peripheral device area specified by the target processor The simulator according to claim 1, wherein the simulator is a means for detecting that is used as a condition. The means for detecting the waiting portion is
If the target processor has a dedicated input / output instruction for the peripheral device,
2. The simulator according to claim 1, wherein said simulator is a means for detecting on condition that said peripheral input / output instruction is used together with a combination of a conditional branch instruction and its branch destination address. In the simulation method of simulating the operation of the target processor on another host computer, and detecting the conditional branch portion by the instruction of the target processor,
When simulating the programming part that advances the processing based on the status of the peripheral device when performing data input / output with the peripheral device connected to the target processor , the combination of the target processor 's instructions and its effective address A step of detecting a waiting portion related to input / output of data with a peripheral device in the embedded program related to the programming portion ;
And rewriting the internal register value of the target processor indicating the state of the peripheral device to exit the waiting portion.

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