JP3363066B2 - Logic circuit verification device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is used in a CAD device or the like for supporting the design of an electronic circuit, and a logic circuit in the created electronic circuit complies with the rules. those related to the logic circuit verification equipment to verify whether performing the correct connection. 2. Description of the Related Art In recent years, the scale of semiconductor chips has increased dramatically, and the development of such semiconductor chips has become the mainstream using CAD devices. Further, it is very difficult to manually check those connection rules, and a method using a CAD device that performs automatic verification has been proposed. FIG. 3 is a block diagram showing a schematic configuration of a conventional logic circuit verification device. In FIG. 3, reference numeral 1 denotes a logic circuit diagram creation device including a CAD device main body, 2 denotes a netlist input unit for inputting a netlist indicating connection information between logic circuits, and 5 denotes an error / warning output unit for outputting a verification result. Reference numeral 6 denotes a verification rule storage area that stores the verification rules of the logic circuit. Reference numeral 9 denotes a verification unit. Reference numeral 10 denotes a library input unit that inputs a library indicating circuit information of the logic circuit. This conventional logic circuit verification device extracts a netlist indicating connection states of logic circuits from a circuit diagram created by a logic circuit diagram creation device 1 and inputs it to a netlist input unit 2. The connection information of the logic circuit was transmitted to the verification unit 9. In addition, a library having no information on high impedance control is input to the library input unit 10 and information for each logic circuit is transmitted to the verification unit 9. Based on these, the verification unit 4 determines whether or not the connection state of the logic circuit in the circuit diagram complies with the rules based on the verification rules stored in the verification rule storage area 6, and determines the result as an error. / Warning output unit 5. [0005] However, according to such a conventional check method, when a floating or short check is performed, a pin to which a high impedance value may be output in a library is provided. Since only the information is written and the state of the control terminal when outputting a high impedance value from the pin is not known, the following problem has occurred. For the floating check, when the control terminal is directly connected to the ground or directly to the power supply so as not to output a high impedance value from the tri-state output pin, the tri-state output pin is not configured as a bus and is used alone. It had to be used, but a floating pseudo error message was output even though it was used alone. For example, as shown in the circuit diagram of FIG.
Is a pin to be checked, and a logic circuit 11 having a tri-state output pin 12 and a control terminal 13 for controlling the tri-state output pin 12 and a logic circuit 14 at the next stage are connected as shown in FIG. Since the terminal 13 is directly grounded so as not to output a high impedance value from the tri-state output pin 12, the tri-state output pin 12 is not configured as a bus, but is used alone as one of the logic circuits 14 in the next stage. The floating pseudo error message was output even though it was connected to the input. Further, regarding the short error, when the pin type is a tri-state output pin, it is assumed that a high impedance value is always output from the pin regardless of the state of the control terminal.
It was excluded from short check. Therefore, if the control terminal is connected directly to ground or directly to the power supply so as not to output a high impedance value from the tri-state output pin, the tri-state output pin must be used independently without a bus configuration. Nevertheless, there is a problem that short errors are not displayed and short errors cannot be picked up even when the bus is configured and used. For example, as shown in the circuit diagram of FIG. 5, a logic circuit 15 having a tristate output pin 16 as a check target pin and having the tristate output pin 16 and a control terminal 17 and a logic circuit 18 at the next stage are illustrated in FIG. In this case, the control terminal 17 is grounded, and the tri-state output pin 16 which is controlled not to output a high impedance value is connected to the other pin 19, so that the next stage is connected. Because of the connection to the logic circuit 18, a short error has occurred, but such a short error could not be picked up as described above. As described above, when the pin type is the tri-state output pin, the floating and short-circuit check cannot be performed by the logic circuit verification device and must be visually checked. And the efficiency of work has been reduced. The present invention can perform connection check tristate output pins had to check the conventional visual observation automatically, Hakare be shortened and the efficiency of the design period, the logic circuit verifying apparatus which can realize an improvement in working efficiency The purpose is to provide. [0009] A logic circuit verification device according to the present invention.
Is a netlist showing connection information between logic circuits.
Input the netlist input section and the circuit information of the logic circuit.
Library input section for inputting the library to be
Rules storage area for storing rules, and netlist entry
Input to the netlist and library input
Is written to the validation rule storage area using the
The connection state of the logic circuit is correct based on the
A verification unit that determines whether the
Logic circuit with error / warning output
Verification device, the verification unit input to the library input unit.
High impedance for tri-state output pins.
State, high level state, or low level state.
Control terminal connection status according to each output status
And a library describing the level state indicating polarity.
Based on this, the pin to be checked is a tri-state output pin.
A first step of determining whether the
Pin to be checked is a tri-state output pin
Is determined, the control of the tri-state output pin
Check the connection status and polarity of the
Based on the connection status and polarity of the control
Output state of the tri-state output pin
-Dance state or not high impedance state
A second step of determining whether the
Is connected to the next logic circuit by itself
The third step to judge and the second step to try
Tate output pin is in high impedance state
It is determined that there is, and the third step alone
If it is determined that the
The state of connection to the logic circuit at the next stage of the
Is determined to be a tracking error, and
Output state of the state output pin is high impedance
Is determined to be the state, and in the third step,
If it is determined that the circuit is not connected to the
The state of the connection of the Lystate output pin to the next logic circuit is
Determined to be normal, and tri-state in the second step
If the output state of the output pin is not in the high impedance state
The logic circuit of the next stage which is determined and is independently used in the third step
If it is determined to be connected to
If the connection status of the output pin to the next logic circuit is normal
Judgment and output of tri-state output pin in the second step
If the force state is determined not to be in the high impedance state,
One third in the steps are connected individually to the next stage of logic circuits
If it is determined that there is no
If the connection status to the next logic circuit is a short error
The fourth operation of the verification unit is performed in the fourth step of determining.
The error / warning output section outputs the judgment result of the step.
Things. According to this verification apparatus , the level state of the control terminal according to the output state of the tri-state output pin is described in the library. If it is determined that the level does not correspond to the high-impedance state and only the tri-state output pin is connected to one input of the next-stage logic circuit, it is not determined that an error has occurred. By judging a short error when another pin is connected to the same input of the next logic circuit, it is possible to automatically check for a short error according to the connection status of the control terminal and the tri-state output pin. it can. [0011] In the case where the control terminal from the connection information of the control terminal Ru to be determined na level state corresponding to the high impedance state of the tri-state output pins, only tri-state output pin of the next stage logic circuit- The control terminal determines that a floating error is detected when connected to one input and does not determine an error when another pin is connected to the same input of the next stage logic circuit together with the tri-state output pin. Also, a floating error check according to the connection state of the tri-state output pin can be automatically performed. As described above, the connection check of the tri-state output pin, which had to be visually checked conventionally, can be automatically performed, so that the design period can be shortened and the efficiency can be improved, and the work efficiency can be improved. be able to. In addition,
The determination as to whether the control terminal is in a level state corresponding to the high impedance state of the tri-state output pin is made when the control terminal has negative logic and is directly grounded. Judge that the level state does not correspond to the high impedance state, the control terminal is negative logic,
And when it is directly power connection, when the control terminal is determined to ing to the level state corresponding to the high impedance state of the tri-state output pins, a control terminal is a positive logic, and which is grounded directly, determines that the control terminal is ing the level state corresponding to the high impedance state of the tri-state output pin is a control pin positive logic, and when it is directly power connection, high control terminals of the tri-state output pins It can be determined that the level does not change according to the impedance state. Further, the control terminal determines whether or not the control terminal attains a level state corresponding to the high impedance state of the tri-state output pin.
Regardless of negative logic is not grounded control terminal directly, and when not directly power connection, adding to determine the control terminal ing the level state corresponding to the high impedance state of the tri-state output pins Can also. Thus, the level state of the control terminal can be determined based on the polarity of the control terminal and the connection destination of the control terminal. Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a logic circuit verification device according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a logic circuit diagram creation device including a CAD device main body, 2 denotes a netlist input unit for inputting a netlist indicating connection information between logic circuits, and 3 denotes a library indicating circuit information of the logic circuit. 4 is a verification unit, 5 is an error / warning output unit that outputs the verification result of the verification unit 4, and 6 is a verification rule storage area that stores the verification rules of the logic circuit. The feature of this embodiment is that the library input to the library input unit 3 is improved, and the control when a high impedance value or a high / low level is output from the tristate output pin is performed from the pin. The value of the terminal is described in the library, and when the connection of the tri-state output pin is checked by the verification unit 4 based on the verification rule stored in the verification rule storage area 6, the control terminal and the tri-state output pin are checked. The floating and short check are performed in consideration of the connection state. Hereinafter, a method of verifying the short-circuit of the tri-state output pin and the floating check will be described in detail with reference to FIG. FIG. 2 is a flowchart illustrating a method of verifying a short-circuit and a floating check of a tri-state output pin in the verification unit 4.
The verification unit 4 first determines whether the pin to be checked is a tri-state output pin based on the library (step S1). If the pin to be checked is not a tri-state output pin but a normal output pin,
A normal output pin connection check is performed (step S1).
8). In this case, regardless of the connection state or presence or absence of the control terminal, when there is another pin other than the input pin in the net to which the output pin is connected, that is, the output pin is connected to another pin. When connected to the next logic circuit, a short error occurs. As a result of step S1, if the pin to be checked is a tri-state output pin, the content of the error differs depending on the polarity and connection state of the control terminal for controlling the pin, so the output value of that pin is determined from the library. First, check the connection state of the control terminal. That is, it is checked where the control terminal is connected (step S2). As a result of step S2, if the control terminal is directly connected to GND (ground),
The polarity of the control terminal is checked (step S3). Here, as a result of steps S2 and S3, if the control terminal is directly connected to GND and the logic is positive, it is determined that a high impedance value may be output from the tristate output pin, and the control terminal is GND
Is connected directly to the input terminal, and in the case of negative logic, it is determined that the state is fixed such that a high impedance value is not output from the tristate output pin. As a result of step S3, if the control terminal is of a positive logic, that is, if there is a possibility that a high impedance value is output from the tristate output pin, then that pin is not connected to the bus but It is checked whether or not it is connected to the next stage logic circuit (step S4). As a result of step S4, if the logic circuit is independently connected to the next-stage logic circuit, it is determined that a floating error has occurred because a through current may flow through the chip (step S5). If it is determined in step S4 that the logic circuit is not independently connected to the next logic circuit, it is determined that the logic circuit is normal (step S6). Also, as a result of step S3, if the control terminal is of negative logic, that is, if the state where the high impedance value is not output from the tristate output pin is fixed, then the pin is not connected to the bus. Next, it is checked whether or not it is independently connected to the next-stage logic circuit (step S7). If the result of step S7 is that the tri-state output pin is independently connected to the next-stage logic circuit, it is determined that it is normal ( step S8 ). For example, as shown in FIG. 4, when the control terminal 13 is directly grounded, the high impedance value is fixed to a state where no high impedance value is output. Although a floating pseudo error message was output, here, in steps S2 and S3, the floating error is excluded, and in step S7, the tri-state output pin 1
2 is independently connected to the next-stage logic circuit 14,
It was decided not to cause a short error. As a result of step S7, if the tristate output pin is not connected to the next logic circuit alone, that is, a plurality of tristate output pins or normal output pins, input / output pins, etc. If it is connected to the logic circuit of the stage, it is determined that a short error has occurred because a signal collision occurs (step S9). For example, as shown in FIG. 5, the control terminal 17 is directly grounded so as not to output a high impedance value, the tristate output pin 16 is connected to another pin 19, and is connected to the logic circuit 18 in the next stage. In this case, a short circuit occurs, and thus a short error is determined. As described above, a short check of the tri-state output pin, which has not been conventionally performed, can be performed. As a result of step S2, even if the control terminal is directly connected to VDD (power supply), the polarity of the control terminal is checked (step S10). Here, as a result of steps S2 and S10, if the control terminal is directly connected to VDD and the logic is positive, it is determined that the state where the high impedance value is not output from the tristate output pin is fixed, and the control terminal is determined. Is directly connected to VDD and has negative logic, it is determined that a high impedance value may be output from the tri-state output pin. As a result of step S10, if the control terminal is of positive logic, that is, if the state where the high impedance value is not output from the tri-state output pin is fixed, then that pin is not connected to the bus but It is checked whether or not it is connected to the next stage logic circuit (step S11). If the result of step S11 is that the tri-state output pin is independently connected to the next-stage logic circuit, it is determined to be normal (step S12). Also,
If the result of step S11 is that the tri-state output pin is not independently connected to the next-stage logic circuit, a signal collision occurs, so that a short error is determined (step S13). Also, as a result of step S10, if the control terminal has negative logic, that is, if there is a possibility that a high impedance value is output from the tristate output pin, then that pin is not connected to the bus, but It is checked whether the logic circuit is independently connected to the next stage logic circuit (step S14). As a result of step S14, when the logic circuit is connected to the next stage alone, it is determined that a floating error has occurred because a through current may flow through the chip (step S15). If it is determined in step S14 that the logic circuit is not independently connected to the next logic circuit, it is determined that the logic circuit is normal (step S16). If the result of step S2 is that the control terminal is not directly connected to VDD or GND,
A pseudo floating error (step S1)
7). The verification result performed by the verification unit 4 in this manner is as follows:
It is output from the error / warning output unit 5 and can be confirmed by the designer. As described above, according to this embodiment, the connection check of the tri-state output pin, which had to be visually checked by the conventional designer, can be automatically performed.
An error can be found before the execution of the logic simulation, and a human error such as an oversight of a check can be reduced, and the number of confirmation steps can be further reduced. As a result, the design period can be shortened and the efficiency can be improved, and the work efficiency can be improved. In FIG. 2, when the control terminal is not directly connected to VDD and GND as a result of step S2, a pseudo floating error is determined (step S17). Is not directly connected to VDD, GND,
Regardless of the positive / negative logic polarity of the control terminal,
Determine whether the tri-state output pin is likely to output a high-impedance value from the tri-state output pin, and check whether the tri-state output pin is independently connected to the next-stage logic circuit. If it is connected to a circuit, it may be determined as a floating error, and if it is not independently connected to a next-stage logic circuit, it may be determined that it is normal. In any case, in this embodiment, when the control terminal is not directly connected to VDD or GND, that is, when the control terminal is connected to VDD or GND via a gate, or completely, When the gates are controlled in combination, the value output from the tri-state output pin cannot be determined unless a logic simulation is performed, so that an accurate error cannot be detected. As described above, according to the present invention, a short circuit and a floating check according to the connection state of the control terminal and the tristate output pin can be automatically performed. As described above, the connection check of the tri-state output pin, which had to be visually checked conventionally, can be automatically performed, so that the design period can be shortened and the efficiency can be improved, and the work efficiency can be improved. .

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a schematic configuration of a logic circuit verification device according to an embodiment of the present invention. FIG. 2 is a logic circuit verification device according to an embodiment of the present invention.
9 is a flowchart showing the verification operation of FIG. FIG. 3 is a block diagram showing a schematic configuration of a conventional logic circuit verification device. FIG. 4 is a circuit diagram for explaining a conventional problem. FIG. 5 is a circuit diagram for explaining a conventional problem. [Description of Signs] 1 Logic circuit diagram creation device 2 Netlist input unit 3 Library input unit 4 Verification unit 5 Error / warning output unit 6 Verification rule storage area

Claims (1)

(57) [Claims] [Claim 1] A net indicating connection information between logic circuits
A netlist input unit for inputting a list, and the logic circuit
Library input to input a library showing the circuit information of
Part, a verification rule storage area for storing the verification rules, and
The netlist input to the netlist input section;
And the library input to the library input unit.
The verification rule stored in the verification rule storage area using
Whether the connection state of the logic circuit is correct based on the rule
And a verification unit for determining the verification result, and outputting a verification result of the verification unit.
Logic circuit verification device having error / warning output unit
A is, the verification unit is input to the library input unit, tri-state output
High impedance state, high level state for pins
Or according to each output state which becomes low level state
Level indicating the connection status and polarity of the control terminal
Check target based on the library where the status is described
Determine if a pin is the tri-state output pin
Disconnecting the pin to be checked in the first step.
If the output pin is determined to be
Connection state of the control terminal of the
And polarity, and check the control
Based on the connection status and polarity of the
Tate output pin is in high impedance state
And whether it is in a high impedance state
Step 2 and the tri-state output pin is used alone to the next logic circuit.
A third step of determining whether or not the connection is made; and outputting the tri-state output pin in the second step.
If the force state is determined to be high impedance,
In the third step, only the logic circuit of the next stage is independently connected.
The tri-state output
The connection status of the pin to the next logic circuit is floating
Determines that the error, the tri by the second steps
Output state of state output pin is high impedance state
And in the third step alone the next
If it is determined that it is not connected to the logic circuit of the stage,
Connection of the tristate output pin to the next stage logic circuit
It is determined that the state is normal, and in the second step,
Output state of tri-state output pin is high impedance
Is not in the standby state, and the third step
When it is judged that it is connected to the next logic circuit by itself
To the logic circuit at the next stage of the tristate output pin.
It is determined that the connection state is normal, and in the second step,
The output state of the tri-state output pin is high impedance.
It is determined that the user is not in the dance state and the third step
Is not connected to the next logic circuit by itself
The logic circuit at the next stage of the tri-state output pin.
4th judgment that the connection state to the road is a short error
And the verification unit determines the result of the fourth step as the error.
-/ Logic circuit verification device output by the warning output unit.