JP3366766B2 - Method for producing silicon single crystal - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention provides a device characteristic represented by a withstand voltage characteristic (hereinafter referred to as an oxide film breakdown voltage) of an insulating oxide film manufactured by the Czochralski method (hereinafter referred to as a CZ method). The present invention relates to an excellent silicon single crystal and a method for manufacturing the same.

[0002]

2. Description of the Related Art CZ silicon single crystal has been widely used as a material for LSI since it has excellent characteristics such as high crystal strength. However, it is known that the breakdown voltage of an oxide film of a silicon single crystal is largely different due to a fundamental difference in the manufacturing method, and the breakdown voltage of an oxide film of a CZ silicon single crystal is a silicon single crystal manufactured by the floating zone method or CZ silicon. It is significantly lower than that of a wafer in which a silicon thin film is epitaxially grown on the wafer. However, with the recent increase in the degree of integration of MOS devices, it is strongly desired to improve the reliability of the gate oxide film, and the oxide film breakdown voltage is one of the important material characteristics that determine the reliability. Development of manufacturing technology of CZ silicon single crystal having excellent withstand voltage characteristics has been emphasized.

As a method for producing a CZ silicon single crystal having an excellent oxide film withstand voltage, a method for producing a silicon single crystal having a diameter of 100 mm or more by the CZ method in Japanese Patent Laid-Open No. 2-267195, has a crystal growth rate of 0.8 mm / Disclosed is a method characterized in that the time is less than or equal to minutes. However, this method is not practical because of poor productivity.

Further, in Japanese Patent No. 1742752, a silicon single crystal which is being pulled up is heated from 1100 ° C. to 900 ° C.
Although a temperature control method of gradually lowering the temperature to 0 ° C. over 3 hours is performed to reduce the oxygen precipitate density in the semiconductor device process, it is described below.
The present inventors have different gradual cooling temperatures for reducing oxygen precipitate density and gradual cooling temperature ranges for improving oxide film withstand voltage characteristics,
It was found that the gradual cooling of the temperature range in which the density of oxygen precipitates is gradually decreased rather deteriorates the oxide film withstand voltage characteristics.

Further, in Japanese Unexamined Patent Publication (Kokai) No. 5-70283, when a silicon single crystal is manufactured, the temperature range of 1150 ° C. or higher of the growing silicon single crystal is 2 above the silicon melt.
Pulling method to be 80 mm or more, that is, 1150 ° C
A pulling method has been proposed in which the temperature range limited above is gradually cooled. In addition, from the same applicant, JP-A-5-9096
In order to suppress the occurrence of stacking faults and improve the oxide film withstand voltage characteristics, a crystal production rate of 0.8 mm / mm is used by using a limited temperature control mechanism for slowing the crystal cooling rate. It has been proposed to limit the speed to 1.1 mm / min. As described above, the conventional methods for improving the breakdown voltage of the oxide film are only the method of gradually cooling a certain limited temperature range or performing crystal production at a limited production rate while using a certain limited temperature control mechanism. Didn't.

[0006] References / Semiconductor Science and Technology
Technology), Vol. 7, page 406 (1992), describes the variability of the critical temperature related to the oxygen precipitation characteristics in the crystal manufacturing process, but does not mention any device characteristics such as oxide film breakdown voltage characteristics. .

Therefore, there has been a need for a method for producing a CZ silicon single crystal having an excellent withstand voltage of an oxide film, which does not limit the annealing temperature region and does not limit the crystal production rate, but such a method has hitherto existed. I didn't. Further, no patent document and technical document describing the relationship between the temperature gradient in the crystal axis direction at the solidification interface between the melt and the crystal in the crystal manufacturing process and the device characteristics represented by the oxide film breakdown voltage have been found so far.

The withstand voltage characteristic of the insulating oxide film is such that the upper layer is made of aluminum and the lower layer is made of doped polycrystalline silicon.
A MOS diode having a layered gate electrode and having an electrode area of 20 mm ² and an insulating oxide film thickness of 25.0 nm is mounted on the entire surface of a silicon wafer cut out from the silicon single crystal, and majority carriers are injected from the substrate silicon. The voltage is applied to each MOS diode with the polarity as described above and evaluated by the voltage ramping method. A region in which the average electric field applied to the oxide film when the current density flowing through the oxide film is 1 μA / cm ² is 8.0 MV / cm or more is called an intrinsic breakdown region or a C-mode region, and the breakdown voltage characteristic of the oxide film in the crystal is defined. Defects that cause deterioration of the voltage (hereinafter referred to as breakdown voltage deterioration factor)
Is an area indicating that there is no. When the average electric field applied to the oxide film is 1.0 MV / cm to 8.0 MV / cm when the current density flowing through the oxide film is 1 μA / cm ² , it is called a B-mode region, and breakdown voltage deterioration occurs in the crystal. This is an area showing that a factor exists. In the conventional CZ silicon crystal, the ratio of the number of MOS diodes that cause dielectric breakdown in the C mode region to the total number is about 10 to 30% per wafer, and MO that causes dielectric breakdown in the B mode region.
The ratio of the number of S diodes to the total number is also large. Therefore, the ratio of the number of MOS diodes that cause dielectric breakdown in the C mode region to the total number is 40% or more, and the number of diodes that breakdown in the B mode region is small, or the minimum breakdown electric field value is high (for example, 6.0 MV / cm). A CZ silicon single crystal in which a diode that breaks below is less than 20%) is a CZ silicon crystal having excellent oxide film withstand voltage characteristics.

[0009]

Therefore, the present invention is representative of a method for producing a CZ silicon crystal having excellent device characteristics represented by oxide film withstand voltage characteristics and an oxide film withstand voltage characteristic which do not limit the annealing temperature region. The present invention aims to provide a CZ silicon crystal having excellent device characteristics.

[0010]

In order to achieve the above object, in the present invention, among the methods for producing a silicon single crystal by the CZ method, the silicon single crystal which is being produced is gradually cooled in a certain crystal temperature region. cold methods odor Te, the temperature gradient in the crystal axis direction of the solidification interface of the melt and the crystal and G ° C. / mm, the temperature at which the cooling rate is minimum in the cooling temperature region (hereinafter, the outermost cooling temperature) to T When the temperature is C, it is gradually cooled so that T becomes 1025-54.5 × G <T <1375-54.5 × G (method ( 1 ) of the present invention). further,
In order to improve the oxide film withstand voltage characteristic, the cooling rate in the temperature region of T ± 100 ° C. is set to 1.0 ° C./min or less (invention method ( 2 )).

[0011]

[0012]

The present invention will be described below with reference to the drawings and tables.

FIG. 1 is a cross section of a MOS diode mounted on a silicon wafer when evaluating the oxide film breakdown voltage of the silicon single crystal subjected to the heat treatment of the present invention. 2 is formed, and a two-layer gate electrode 5 having a diameter of 5 mm and having an upper layer of aluminum 3 and a lower layer of doped crystalline silicon 4 is formed thereon.

Next, the means for evaluating the oxide film breakdown voltage characteristics of the silicon single crystal subjected to the heat treatment of the present invention will be described with reference to Table 1. Table 1 is a table showing a manufacturing process of a MOS diode manufactured for measuring an oxide film breakdown voltage.

[0015]

[Table 1]

The CZ silicon ingot is sliced, lapping, polishing, and other processes necessary for industrially manufacturing a normal silicon wafer are performed, and the obtained wafer is cleaned (1) and oxidized by gate oxidation. A silicon film is formed (2), a polycrystalline silicon film is deposited (3), and this polycrystalline silicon is ion-implanted and doped (6). Pre-oxidation cleaning (4) and polycrystalline silicon oxidation (5) are pre-treatments for ion implantation (6). Then,
Pre-anneal cleaning (7) is performed, drive annealing is performed to solidify the dopant in the polycrystalline silicon (8), the polycrystalline silicon film is removed by etching (9), and aluminum is deposited to form an aluminum layer (10). ). Next, a positive resist film is coated by lithography (11) to mount a two-layer gate electrode having a diameter of 5 mm, and after patterning, the aluminum film is etched (1
2) The polycrystalline silicon film is etched (13) and the resist film is removed (14). After stabilizing the silicon / silicon oxide film interface by hydrogen annealing (1
5) A resist film is applied to the front surface to protect the MOS diode (16), and the back surface polycrystalline silicon film is removed by plasma etching (17). The surface is recoated with a protective resist film (18), the backside oxide film is removed by etching (19), and gold is deposited for p-type and gold-antimony alloy is deposited for n-type. Forming a back electrode (20). Finally, after removing the protective resist film (2
1), the oxide film breakdown voltage characteristic is evaluated by the voltage ramping method (22). The voltage ramping method is a method of applying a DC voltage having a polarity in which majority carriers are injected from the substrate silicon between the aluminum layer 3 and the back electrode in FIG. 1 and increasing the voltage stepwise with respect to time. Is. In the present invention, the voltage increase per step of the voltage ramping method is 0.25 MV / cm in terms of electric field, and the holding time is 200 ms / step.

The present inventors have investigated in detail the temperature gradient in the crystal axis direction of the crystal melt and the solidification interface of the crystal having various oxide film pressure resistance characteristics and the cooling conditions during production, and as a result, the temperature of the solidification interface has been determined. It was discovered that there is the following relationship between the gradient, the cooling conditions and the formation of the pressure resistance deterioration factor. That is, in the silicon manufacturing process by the CZ method, the intrinsic point defects existing at the thermal equilibrium concentration near the solidification interface are taken into the crystal together with the solidification, and become supersaturated as the crystal is cooled. Although the concentration of supersaturated point defects decreases due to outward diffusion to the crystal surface and slope diffusion to the solidification interface,
Since the crystal is cooled at a high rate, the degree of supersaturation of point defects is increased. When the cooling progresses and the degree of supersaturation of the point defects exceeds a certain critical value, the point defects start to form aggregates. Oxygen precipitates are formed by using the aggregates as nuclei, and the oxygen precipitates become a pressure resistance deterioration factor. The size of the oxygen precipitate has a strong influence on the oxide film withstand voltage characteristic, and the larger the size, the lower the dielectric breakdown electric field of the oxide film, and the oxide film withstand voltage characteristic deteriorates. On the contrary, when the size of the oxygen precipitates is small, the oxide film breakdown voltage does not deteriorate even if the oxygen precipitates are present at a high density. On the other hand, the supersaturated point defect causes intense pair annihilation on the high temperature side immediately before the start of aggregation, and the concentration decreases. This decrease in the concentration lowers the aggregation start temperature of the point defects, that is, the formation start temperature of the oxygen precipitates, suppresses the growth of the oxygen precipitates, reduces the size of the oxygen precipitates, and consequently improves the oxide film withstand voltage characteristics. Improve.

Due to these mechanisms, in a crystal that has been gradually cooled at a temperature not higher than the temperature at which point defects start to agglomerate, point defect agglomeration progresses, and the density of oxygen precipitates remarkably decreases, but the size increases and oxidation occurs. The film withstand voltage characteristic is significantly deteriorated. On the other hand, in the crystal that has been gradually cooled on the high temperature side immediately before the point defect agglomeration start temperature, pair annihilation of point defects progresses, the size of oxygen precipitates decreases, and the oxide film breakdown voltage improves.

When the temperature gradient at the solidification interface is steep, the rapid increase in the supersaturation degree of the point defects near the solidification interface causes
The point defects that are incorporated into the crystal frequently diffuse uphill toward the interface and the concentration of point defects decreases significantly.Therefore, the point defects are supersaturated at a position far from the solidification interface as compared to when the temperature gradient is gentle. On the contrary, the increase of the degree becomes moderate. Therefore, when the temperature gradient at the solidification interface is steep, the temperature at which the point defects start to agglomerate moves to the low temperature side. That is, the formation start temperature of oxygen precipitates moves to the low temperature side. The temperature at which pair annihilation of point defects occurs (hereinafter, also referred to as oxide film withstand voltage improving temperature) moves following the movement of the formation start temperature of oxygen precipitates. Therefore, the oxide film breakdown voltage improving temperature is variable depending on the temperature gradient of the solidification interface, and moves to the lower temperature side as the temperature gradient of the solidification interface increases. The present inventors set the temperature gradient of the solidification interface to G ° C./mm and set the slowest cooling temperature to T ° C.
Then, it was discovered that the oxide film breakdown voltage is improved when T is 1025-54.5 × G <T <1375-54.5 × G. Furthermore, the cooling rate in the temperature range of T ± 100 ° C is 1.0 ° C.
It was found that the breakdown voltage of the oxide film was further improved when it was set to be not more than / minute.

[0020]

EXAMPLES Examples of the present invention will be described below.
It goes without saying that the invention is not limited by the description of these examples.

Example 1 A silicon single crystal production apparatus used in the present invention is usually C
There is no particular limitation as long as it can be used for manufacturing a silicon single crystal by the Z method, and the manufacturing apparatus shown in FIG. 2 was used in this example.

This CZ silicon single crystal manufacturing apparatus has a crucible 26 composed of a quartz crucible 26a containing a silicon melt M and a graphite crucible 26b protecting the same, and a crystal containing a grown silicon single crystal ingot S. The pulling furnace 21. A heater 2 is provided on the side surface of the crucible 26.
4 and the heating heater 24 are installed so as to surround the heat insulating member 23 in order to prevent the heat from escaping to the outside of the crystal pulling furnace. The crucible 26 is connected by a driving device (not shown) and a rotating jig 25. The driving device rotates the crucible 26 at a predetermined speed and moves the crucible 26 up and down in order to compensate for the decrease in the silicon melt surface as the silicon melt in the crucible 26 decreases. In the pulling furnace 21, the suspended pulling wire 27
A chuck 29 for holding the seed crystal 28 is provided at the lower end of the wire 27. The upper end side of the pulling wire 27 is taken up by the wire hoisting machine 22,
A pulling device adapted to pull a silicon single crystal ingot is provided. Then, Ar gas is introduced into the pulling furnace 21 from a gas inlet 30 formed in the pulling furnace 21, flows through the pulling furnace 21, and flows into the gas outlet 31.
Emitted from. The Ar gas is circulated in this way so that SiO generated in the pulling furnace 21 due to melting of silicon is not mixed into the silicon melt. The temperature control device 40 is installed in the pulling furnace 21 for gradually cooling the crystal. The gradual cooling temperature range is changed by moving the position of the temperature control device 40 in the vertical direction. As the temperature control device 40, an adiabatic heat insulating material such as graphite and a heater installed so as to surround the silicon single crystal to be manufactured are effective. The temperature gradient control device 50 is installed in the pulling furnace 21 to control the temperature gradient in the crystal axis direction of the solidification interface. Temperature gradient control device 50
For this, a graphite plate or a metal plate installed so as to surround the silicon single crystal to be manufactured is effective for cooling, and the graphite plate or the metal plate may be forcibly cooled by using a gas or a liquid. On the other hand, an adiabatic heat insulating material such as graphite and a heater installed so as to surround the silicon single crystal are effective for slow cooling.

Using this apparatus, a plurality of silicon single crystals were manufactured under the following conditions. When the temperature gradient in the crystal axis direction at the solidification interface between the melt and the crystal is G ° C./mm and the slowest cooling temperature is T ° C., all of these crystals are 1025-54.5 ×, as shown in FIG. The relationship of G <T <1375-54.5 × G 2 is satisfied, and the cooling rate of any crystal in the temperature region of T ± 100 ° C. is not always 1.0 ° C./min or less.

Table 2 shows the manufacturing conditions of a plurality of silicon single crystal ingots grown under these conditions.

[0025]

[Table 2]

The oxide film breakdown voltage of the wafer cut out from this ingot was measured and shown in FIG. The current density flowing through the oxide film of these silicon wafers is 1 μA / c
The average electric field applied to the oxide film at m ² is 8.0 MV / c
The ratio of the total number of MOS diodes showing m or more (C mode ratio) is 40% or more, and the ratio of the total number of MOS diodes destroyed by an electric field of 6.0 MV / cm or less to one total wafer is 1 wafer. 20 per
%, Which indicates that the wafer cut out from the silicon single crystal ingot manufactured by the method of the present invention has good oxide film withstand voltage characteristics.

Example 2 Using the apparatus of Example 1, a plurality of silicon single crystals were manufactured under the following conditions. When the temperature gradient in the crystal axis direction of the solidification interface between the melt and the crystal is G ° C./mm and the slowest cooling temperature is T ° C., all of these crystals are 1025-54.5 ×, as shown in FIG. The relationship of G <T <1375-54.5 × G 3 is satisfied, and the cooling rate of any crystal in the temperature region of T ± 100 ° C. is always 1.0 ° C./min or less.

Table 3 shows the manufacturing conditions of a plurality of silicon single crystal ingots grown under these conditions.

[0029]

[Table 3]

The oxide film breakdown voltage of the wafer cut out from this ingot was measured and shown in FIG. The current density flowing through the oxide film of these silicon wafers is 1 μA / c
The average electric field applied to the oxide film at m ² is 8.0 MV / c
The ratio of the total number of MOS diodes showing m or more (C mode ratio) is 40% or more, and the ratio of the total number of MOS diodes destroyed by an electric field of 6.0 MV / cm or less to one total wafer is 1 wafer. 20 per
%, Which indicates that the wafer cut out from the silicon single crystal ingot manufactured by the method of the present invention has good oxide film withstand voltage characteristics.

Comparative Example 1 In this comparative example, a plurality of silicon single crystals were manufactured under the following conditions using the apparatus of Example 1. When the temperature gradient in the crystal axis direction of the solidification interface between the melt and the crystal is G ° C./mm and the slowest cooling temperature is T ° C., all of these crystals are 1025-54.5 ×, as shown in FIG. The condition of G <T <1375-54.5 × G is not satisfied, and all the crystals have T ± 10.
The cooling rate in the temperature range of 0 ° C. is not always less than 1.0 ° C./min.

Table 4 shows the manufacturing conditions of a plurality of silicon single crystal ingots grown under these conditions.

[0033]

[Table 4]

The oxide film breakdown voltage of the wafer cut out from this ingot was measured and shown in FIG. The current density flowing through the oxide film of these silicon wafers is 1 μA / c
The average electric field applied to the oxide film at m ² is 8.0 MV / c
The ratio of the total number of MOS diodes showing m or more (C-mode ratio) is less than 40%, and at the same time, the ratio of the total number of MOS diodes destroyed by an electric field of 6.0 MV / cm or less to one wafer is 1 wafer. 20 per
% Or more, indicating that the oxide film withstand voltage characteristic is not good.

Comparative Example 2 In this comparative example, a plurality of silicon single crystals were manufactured under the following conditions using the apparatus of Example 1. When the temperature gradient in the crystal axis direction of the solidification interface between the melt and the crystal is G ° C./mm and the slowest cooling temperature is T ° C., all of these crystals are 1025-54.5 ×, as shown in FIG. The condition of G <T <1375-54.5 × G is not satisfied, and all the crystals have T ± 10.
The cooling rate in the temperature range of 0 ° C. is always 1.0 ° C./minute or less.

Table 5 shows the manufacturing conditions and the like of a plurality of silicon single crystal ingots grown under these conditions.

[0037]

[Table 5]

The oxide film breakdown voltage of the wafer cut out from this ingot was measured and shown in FIG. The current density flowing through the oxide film of these silicon wafers is 1 μA /
The average electric field applied to the oxide film is 8.0 MV / cm ²
The ratio (C-mode ratio) of the total number of MOS diodes exhibiting cm or more is less than 40%, and at the same time, the ratio of the total number of MOS diodes destroyed by an electric field of 6.0 MV / cm or less is 1 wafer. 2 per
It is 0% or more, indicating that the oxide film withstand voltage characteristic is not good.

[0039]

The silicon single crystal of the present invention or the silicon single crystal obtained by the manufacturing method of the present invention is excellent in device characteristics represented by oxide film withstand voltage characteristics. Suitable for

[Brief description of drawings]

FIG. 1 is a partial cross-sectional view of a MOS diode mounted to evaluate withstand voltage characteristics of a silicon single crystal insulating oxide film by a conventional method.

FIG. 2 is a schematic view of a CZ method silicon single crystal manufacturing apparatus used in an example of the present invention.

FIG. 3 is a diagram showing a relationship between a temperature gradient G ° C./mm in a crystal axis direction of a melt of a plurality of crystals and a solidification interface of the crystals and a slowest cooling temperature T ° C. in Example 1 of the present invention.

FIG. 4 is a diagram showing oxide film breakdown voltage characteristics of a plurality of crystals in Example 1 of the present invention.

FIG. 5 is a diagram showing a relationship between a temperature gradient G ° C./mm in the crystal axis direction of a melt of a plurality of crystals and a solidification interface of the crystals and a slowest cooling temperature T ° C. in Example 2 of the present invention.

FIG. 6 is a diagram showing oxide film breakdown voltage characteristics of a plurality of crystals in Example 2 of the present invention.

FIG. 7 is a temperature gradient G ° C./mm in the crystal axis direction of the melt of a plurality of crystals and the solidification interface of the crystals of Comparative Example 1 and the slowest cooling temperature T ° C.
It is a figure which shows the relationship of.

8 is a diagram showing oxide film breakdown voltage characteristics of a plurality of crystals in Comparative Example 1. FIG.

9 is a temperature gradient G.degree. C./mm in the crystal axis direction of the melt of a plurality of crystals and the solidification interface of the crystals of Comparative Example 2 and the slowest cooling temperature T.degree.
It is a figure which shows the relationship of.

10 is a diagram showing oxide film breakdown voltage characteristics of a plurality of crystals in Comparative Example 2. FIG.

[Explanation of symbols]

1 ... Silicon wafer, 2 ... Silicon oxide film (insulating oxide film), 3 ... Aluminum film, 4
... polycrystalline silicon, 5 ... two-layer gate electrode, 21 ... crystal pulling furnace (CZ method silicon single crystal manufacturing apparatus), 22 ... wire hoisting machine, 23 ... heat insulating member, 24 ... heating heater, 25 ... rotating jig , 26 ... crucibles, 2
6a ... Quartz crucible, 26b ... Graphite crucible,
27 ... Pulled wire, 28 ... Seed crystal, 29
… Chuck, 30… Gas inlet, 31
... residue discharge port, 40 ... temperature control device (crystal gradual cooling device), 50 ... temperature gradient control device, M ... silicon melt, S ... silicon single crystal ingot.

Front page continuation (72) Inventor Masamichi Okubo 3434 Shimada, Hikari City, Yamaguchi Prefecture Nittetsu Electronics Co., Ltd. (56) Reference JP-A-6-340490 (JP, A) JP-A-2-267195 (JP, A ) JP-A-8-12493 (JP, A) JP-A-7-223893 (JP, A) JP-A-5-70283 (JP, A) JP-A-5-9096 (JP, A) (58) Field (Int.Cl. ⁷ , DB name) C30B 1/00-35/00 H01L 21/208

Claims (2)

(57) [Claims] 1. A silicon single bond produced by the Czochralski method.
When manufacturing the crystal,
In the method of gradually cooling a crystal in a certain crystal temperature region, the temperature gradient in the crystal axis direction at the solidification interface between the melt and the crystal is G ° C /
mm, and when the temperature at which the cooling rate in the slow cooling temperature region is the minimum is T ° C., T changes with the following relational expression 1025-54.5 × G <T <1375-54.5. A method for producing a silicon single crystal, characterized in that a gradual cooling temperature region is changed so as to satisfy × G 2. 2. The method for producing a silicon single crystal according to claim 1 , wherein when the temperature at which the cooling rate in the slow cooling temperature range is the minimum is T ° C., the cooling rate in the temperature range of T ± 100 ° C. Is 1.0 ° C./min or less, a method for producing a silicon single crystal.