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JP3367688B2 - Circuit board - Google Patents
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JP3367688B2 - Circuit board - Google Patents

Circuit board

Info

Publication number
JP3367688B2
JP3367688B2 JP24487092A JP24487092A JP3367688B2 JP 3367688 B2 JP3367688 B2 JP 3367688B2 JP 24487092 A JP24487092 A JP 24487092A JP 24487092 A JP24487092 A JP 24487092A JP 3367688 B2 JP3367688 B2 JP 3367688B2
Authority
JP
Japan
Prior art keywords
circuit board
thin film
ceramic substrate
conductor pattern
protective film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP24487092A
Other languages
Japanese (ja)
Other versions
JPH0697613A (en
Inventor
恭章 安本
晃司 山川
靖 五代儀
馨 小岩
暢男 岩瀬
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP24487092A priority Critical patent/JP3367688B2/en
Publication of JPH0697613A publication Critical patent/JPH0697613A/en
Application granted granted Critical
Publication of JP3367688B2 publication Critical patent/JP3367688B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Parts Printed On Printed Circuit Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Description

【発明の詳細な説明】 【0001】 【産業上の利用分野】本発明は、セラミック基体を使用
した回路基板に関する。 【0002】 【従来の技術】近年のコンピュータシステムの高速化、
小型化指向はこれらに使用する半導体素子の高集積化を
より加速し、最近ではチップ当りの消費電力30W以上
の半導体素子が実用化されつつある。これに伴い、この
ような半導体素子を実装する回路基板に対し、配線の高
密度化や放熱性の向上等が、素子特性をシステム特性に
反映するために要求されている。 【0003】このような点に鑑みて、セラミック基体上
に薄膜導体パターンを配線として形成してなる回路基板
が広く用いられている。放熱性を考慮すると、この回路
基板は、前記セラミック基体としてAlN、SiC等の
高熱伝導率が特に好適に使用され得る。以下に、このよ
うな回路基板の製造プロセスを説明する。 【0004】まず、上記セラミック基体の一表面の全体
に亘って導体薄膜を形成する。続いて、この薄膜を常法
に従ってウェットエッチングまたはドライエッチングす
ることによりパターニングし、この上に所定の厚さとな
るまでめっき処理を施して、所望のパターンからなる配
線を形成する。 【0005】しかしながら、上記プロセスでは、前記セ
ラミック基体の表面が、様々な環境にさらされる。例え
ば、めっき工程前における酸による洗浄、めっき工程後
における高温の酸またはアルカリ溶液への浸漬、エッチ
ング時に使用される酸またはアルカリエッチャント中の
活性ラジカル種との接触、更にセラミック基体と導体薄
膜の接合を行うための高温雰囲気への露出等である。こ
のため、前記セラミック基体の表面は、これら環境下で
付着する様々な汚染物質によって劣化し、変質、溶解、
ピンホール発生、更には、表面に形成される薄膜導体パ
ターンの剥離等の欠陥が生じる。 【0006】また、製造後の回路基板において、セラミ
ック基体表面に付着した汚染物質は洗浄等によっても除
去され得ず永続的に残存する。更に、当該回路基板で
は、細線としての薄膜導体パターンのライン間において
露出したセラミック基体の表面が、再度周囲の環境にさ
らされて劣化し、ひいては回路に欠陥が生じる。この結
果、回路基板の長期信頼性が著しく損なわる。 【0007】 【発明が解決しようとする問題点】本発明は上記問題点
を解決するためになされたもので、製造プロセス中およ
び製造後長期に亘って、セラミック基体表面の耐環境性
が向上した、高信頼性の回路基板を提供することを目的
とする。 【0008】 【問題点を解決するための手段及び作用】本発明の回路
基板は、セラミック基体と、該セラミック基体の一表面
全体を被覆した、Ti、Cr、Ta、Nb、Zr、M
o、W、Vおよびこれら金属の化合物の少なくとも一種
からなる膜厚200pm〜5nmの保護膜と、該保護膜
上に形成された薄膜導体パターンとを具備する回路基板
である。 【0009】本発明の回路基板は、セラミック基体と配
線に相当する薄膜導体パターンとの間に、上述したよう
な保護膜が介在する点で特徴的である。前記保護膜は、
セラミック基体の一表面全体を被覆しており、薄膜導体
パターンの形成等の回路基板の製造プロセス中、および
回路基板を製造した後永続的に、セラミック基体の表面
を環境から保護する。即ち、薄膜導体パターンの形成時
には、酸、アルカリ溶液、活性ラジカル種、および高温
雰囲気によるセラミック基体表面の変質、汚染、腐食、
これに伴う薄膜導体パターンの剥離等による不良品の発
生が防止される。また、薄膜導体パターンの形成後で
は、特に当該パターンのライン間において露出したセラ
ミック基体表面の劣化が防止され、回路の欠陥の発生、
薄膜導体パターン剥離等が防止される。こうして、本発
明の回路基板では、製造プロセス中および製造後長期に
亘って、セラミック基体表面の耐環境性が向上し、更
に、薄膜導体パターンの剥離が抑えられ、諸性能に関し
て長期的な信頼性が実現され得る。 【0010】本発明の回路基板において、前記保護膜の
材料には、上記の如くTi、Cr、Ta、Nb、Zr、
Mo、W、V、またはこれら金属の化合物等が用いられ
る。この化合物としては、具体的には、上記金属の窒化
物、炭化物、ほう化物、上記金属と下層のセラミック基
体を構成する金属元素あるいは他の金属元素との金属間
化合物等が挙げられる。またこのとき、窒素、炭素、ほ
う素や上述したような金属元素等は、一部保護膜中で固
溶、拡散してもよく、更にAr等の微量の不純物元素の
混入も許容される。 【0011】本発明における、前記保護膜の材料の限定
理由は以下の通りである。Ti、Cr、Ta、Nb、Z
r、Mo、W、およびVは、いずれも活性な金属であ
り、セラミック基体および薄膜導体パターン間に介在し
て良好な密着強度を付与し、また、周囲の環境に因って
は、セラミック基体および薄膜導体パターン中の構成元
素と窒化物、炭化物、および金属間化合物等を形成し、
より密着強度を高める。特に、セラミック基体としてA
lNを使用する場合は、このような保護膜を介在させる
ことにより、薄膜導体パターンの密着強度が著しく向上
する。更に、これら金属およびその化合物は、耐酸性、
耐アルカリ性、耐熱性に非常に優れるため、セラミック
基体表面上を膜の形で被覆した場合、当該表面を周囲の
様々な環境から遮断することが可能である。よって、上
記金属およびこれら金属の化合物は、前記保護膜として
好適な材料である。 【0012】一方、本発明の回路基板において、前記保
護膜の膜厚は上記の如く200pm〜5nmの範囲にあ
る。前記保護膜は、膜厚が当該範囲にあることによっ
て、約9×109 〜2×1013Ω程度の適度な抵抗値を
示す。従って、前記保護膜が、セラミック基体の表面を
被覆し、薄膜導体パターンのラインおよびライン間の下
層一面に設けられているにもかかわらず、当該パターン
のライン間、即ち配線間は絶縁され、回路基板上に実装
される半導体素子等は異常なく作動することが可能にな
る。 【0013】ここで、前記保護膜の膜厚が200pm
であると、セラミック基体表面を周囲の環境と充分に
遮断することができない。また、前記保護膜の膜厚が5
nmを越えると薄膜導体パターンのライン間、即ち配線
間の抵抗が1×109Ω以下に低下するため、実装され
る半導体素子の動作に異常が生じる。更に好ましくは、
前記保護膜の膜厚は、250pm〜3nmの範囲であ
る。 【0014】この他、本発明の回路基板における、セラ
ミック基体、および薄膜導体パターンを形成する導体と
しては、特に限定されるわけではないが、一般的な材料
が使用され得る。セラミック基体としては、例えば、A
lN、BN、SiO2 、SiC、ほうけい酸ガラス等の
低誘電率材料、および高熱伝導率材料が使用され得る。
これらセラミック基体の材料を適宜選択することによっ
て、信号伝搬速度が高く、または放熱性に優れた回路基
板を得ることができる。一方、導体としては、例えば、
Au、Cu、Ni、Ag、Pt等の金属が使用され得
る。また、薄膜導体パターンは、Ti、Cr、Ta、N
b、Zr、Mo、W、V等からなる接合層と、Ni、P
t、Mo、Nb、W、V、Ti等からなるバリアメタル
層と上記金属からなる導体薄膜が、この順で積層された
多層構造であってもよい。次に本発明の回路基板の製造
プロセスについて説明する。 【0015】まず、上述したようなセラミック基体を用
意し、その一表面を必要に応じて湿式洗浄法、逆スパッ
タ法、ドライエッチング法等により清浄化する。続い
て、当セラミック基体表面全体に亘って、Ti、Cr、
Ta、Nb、Zr、Mo、W、Vおよびこれら金属の化
合物の少なくとも一種を膜厚200pm〜5nmに製膜
することによって保護膜を形成する。この製膜方法に
は、真空蒸着法、スパッタ、クラスタイオンビーム、イ
オンプレーティング、イオンミキシング、CVD等の一
般的な方法が採用される。各方法では、保護膜の材料に
応じて、基体温度、雰囲気、真空度、製膜速度等の条件
を調整する必要がある。 【0016】次に、前記保護膜の表面に、必要に応じて
厚さ1〜100nm程度の接合層、厚さ90〜500n
m程度のバリアメタル層を形成した後、例えば、スパッ
タまたは真空蒸着法によって導体薄膜を形成する。続い
て、この導体薄膜および必要に応じて形成されたバリア
メタル層と接合層をウェットエッチングまたはドライエ
ッチングしてパターニングし、またこの上に導体薄膜と
の合計厚さが200nm〜10μm 程度となるまで、適
宜電解または無電解めっき処理を施して、配線となる薄
膜導体パターンを形成する。尚、この後、薄膜導体パタ
ーン上に、必要に応じて誘電体層、層間絶縁膜、上部配
線等を形成してもよいが、本発明における保護膜は、こ
のような工程中の環境から、セラミック基体の表面を遮
断する機能をも備えている。 【0017】 【実施例】以下、本発明を実施例に沿って詳細に説明す
る。尚、これら実施例は、本発明の理解を容易にする目
的で記載されるものであり、本発明を特に限定するもの
ではない。 実施例 下記表1に示す如く条件で、セラミック基体の一表面
に、保護膜、および薄膜導体パターンを形成し、回路基
板の試料No.1〜21を作製した。 【0018】即ち、まずセラミック基体の一表面に表1
に示した組成および膜厚の保護膜をスパッタにより形成
し、次いでMoからなる厚さ300nmのバリアメタル
層およびAuからなる厚さ500nmの導体薄膜を順次
スパッタにより形成した。 【0019】この後、フォトリソグラフィ技術によって
前記導体薄膜およびバリアメタル層をパターニングし、
更にこの上にアルカリ系Au無電解溶液を用いた90℃
での無電解めっき処理により、薄膜導体との合計厚さが
4μm となるまでめっき膜を成長させ、幅50μm 、ピ
ッチ70μm の薄膜導体パターンを配線として形成し
た。 【0020】次に、これらの試料について、薬品または
プラズマを使用した信頼性試験を行った。即ち、試料を
夫々表1に示した薬品、プラズマの雰囲気、条件下に置
き、この後、配線間(薄膜導体パターンのライン間)表
面粗さ、配線間の線間抵抗値、薄膜導体パターンの剥離
の有無を評価した。結果を同表に併記する。表1に示す
結果より、上記実施例の回路基板では配線間表面粗さ、
線間抵抗値、薄膜導体パターンの密着強度には、実用上
何等問題がないことが確認された。 比較例 【0021】下記表1に示す如く条件で、実施例と同様
にしてセラミック基体の一表面に、保護膜、および薄膜
導体パターンを形成し、回路基板の試料No.22〜2
5を作製した。但し、これら試料No.22〜23の回
路基板では、保護膜の膜厚が200pm〜5nmの範囲
から外れており、試料No.24〜25の回路基板で
は、セラミック基体上に保護膜が形成されておらず、配
線間でセラミック基体表面が露出している。これら試料
について、上記実施例と同様に諸特性に関して信頼性を
評価した。結果を同表に併記する。 【0022】表1に示す結果より、保護膜の膜厚が所定
の範囲内から外れて薄い回路基板(試料No.22)で
は、配線間のセラミック基体表面を充分に周囲の環境か
ら遮断することができないため、信頼性試験後の配線間
表面粗さが増大しており、配線間でセラミック基体表面
の劣化が進んでいた。 【0023】また、保護膜の膜厚が所定の範囲内から外
れて厚い回路基板(試料No.23)では、線間抵抗値
が小さく、当該回路基板上に半導体素子を実装して動作
させた場合、誤動作を生じる可能性が大きい。 【0024】更に、保護膜の形成されていない回路基板
(試料No.24および25)においては、配線間表面
粗さが著しく大きい上に、信頼性試験後に薄膜導体パタ
ーンの剥離が発生して、薄膜導体パターンの密着強度が
不充分であることが確認された。 【0025】 【表1】【0026】 【発明の効果】以上詳述したごとく、本発明によれば、
製造プロセス中および製造後長期に亘ってセラミック基
体表面の耐環境性が向上した、高信頼性の回路基板が提
供される。
Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board using a ceramic substrate. [0002] In recent years, the speeding up of computer systems,
The trend toward miniaturization has further accelerated the high integration of semiconductor devices used in these devices. Recently, semiconductor devices having a power consumption of 30 W or more per chip have been put into practical use. Along with this, a circuit board on which such a semiconductor element is mounted is required to have higher wiring density and improved heat dissipation in order to reflect element characteristics to system characteristics. [0003] In view of the above, a circuit board formed by forming a thin film conductor pattern as a wiring on a ceramic base has been widely used. In consideration of heat dissipation, this circuit board can particularly suitably use a high thermal conductivity such as AlN or SiC as the ceramic substrate. Hereinafter, a manufacturing process of such a circuit board will be described. First, a conductive thin film is formed over the entire surface of the ceramic substrate. Subsequently, the thin film is patterned by wet etching or dry etching according to a conventional method, and a plating process is performed thereon until a predetermined thickness is obtained, thereby forming a wiring having a desired pattern. However, in the above process, the surface of the ceramic substrate is exposed to various environments. For example, washing with an acid before the plating step, immersion in a high-temperature acid or alkali solution after the plating step, contact with active radical species in an acid or alkali etchant used at the time of etching, and bonding of the ceramic substrate and the conductive thin film Exposure to a high temperature atmosphere for performing the above. For this reason, the surface of the ceramic substrate is deteriorated by various contaminants attached in these environments,
Defects such as generation of pinholes and peeling of the thin film conductor pattern formed on the surface occur. [0006] In the manufactured circuit board, the contaminants adhering to the surface of the ceramic base cannot be removed even by washing or the like and remain permanently. Furthermore, in the circuit board, the surface of the ceramic base exposed between the lines of the thin-film conductor pattern as a thin wire is again exposed to the surrounding environment and deteriorates, thereby causing a defect in the circuit. As a result, the long-term reliability of the circuit board is significantly impaired. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has improved the environmental resistance of the ceramic substrate surface during the manufacturing process and for a long time after the manufacturing. It is an object of the present invention to provide a highly reliable circuit board. A circuit board according to the present invention comprises a ceramic substrate and Ti, Cr, Ta, Nb, Zr, M, which cover the entire surface of the ceramic substrate.
A circuit board comprising a protective film of at least one of o, W, V and a compound of these metals having a thickness of 200 pm to 5 nm, and a thin film conductor pattern formed on the protective film. The circuit board of the present invention is characterized in that the above-mentioned protective film is interposed between the ceramic base and the thin film conductor pattern corresponding to the wiring. The protective film,
The coating covers the entire surface of the ceramic substrate, and protects the surface of the ceramic substrate from the environment during the manufacturing process of the circuit board such as formation of a thin film conductor pattern and permanently after manufacturing the circuit board. That is, at the time of forming the thin film conductor pattern, the deterioration, contamination, corrosion, and the like of the ceramic substrate surface due to acid, alkali solution, active radical species, and high temperature atmosphere.
This prevents the occurrence of defective products due to peeling of the thin film conductor pattern and the like. Further, after the formation of the thin film conductor pattern, deterioration of the surface of the ceramic base exposed particularly between the lines of the pattern is prevented, and the occurrence of circuit defects,
Peeling of the thin film conductor pattern is prevented. Thus, in the circuit board of the present invention, the environmental resistance of the surface of the ceramic substrate is improved during the manufacturing process and for a long time after the manufacturing, the peeling of the thin film conductor pattern is suppressed, and the long-term reliability of various performances is reduced. Can be realized. In the circuit board of the present invention, the material of the protective film includes Ti, Cr, Ta, Nb, Zr,
Mo, W, V, or a compound of these metals is used. Specific examples of the compound include nitrides, carbides, and borides of the above-mentioned metals, and intermetallic compounds of the above-mentioned metals with the metal elements constituting the lower ceramic substrate or other metal elements. At this time, nitrogen, carbon, boron, the above-described metal elements, and the like may be partially dissolved and diffused in the protective film, and a small amount of impurity elements such as Ar may be mixed. The reasons for limiting the material of the protective film in the present invention are as follows. Ti, Cr, Ta, Nb, Z
r, Mo, W, and V are all active metals and are provided between the ceramic substrate and the thin film conductor pattern to provide good adhesion strength. Also, depending on the surrounding environment, the ceramic substrate And constituent elements in the thin film conductor pattern and nitride, carbide, and intermetallic compound, etc.
Increase the adhesion strength. In particular, A as a ceramic substrate
When 1N is used, the adhesion strength of the thin film conductor pattern is significantly improved by interposing such a protective film. Furthermore, these metals and their compounds are acid resistant,
Since it is very excellent in alkali resistance and heat resistance, when the surface of the ceramic substrate is coated in the form of a film, the surface can be shielded from various surrounding environments. Therefore, the above metals and compounds of these metals are suitable materials for the protective film. On the other hand, in the circuit board of the present invention, the thickness of the protective film is in the range of 200 pm to 5 nm as described above. When the thickness of the protective film is in the above range, about 9 × 10 9 It shows an appropriate resistance value of about 2 × 10 13 Ω. Therefore, even though the protective film covers the surface of the ceramic substrate and is provided on the entire lower layer between the lines of the thin-film conductor pattern, the lines of the pattern, that is, the wiring are insulated, and the circuit is insulated. A semiconductor element or the like mounted on the substrate can operate without any abnormality. [0013] In this case, the thickness of the protective film is 200pm Not
If it is full , the surface of the ceramic substrate cannot be sufficiently shielded from the surrounding environment. Further, the thickness of the protective film is 5
If it exceeds nm , the resistance between the lines of the thin film conductor pattern, that is, between the wirings is reduced to 1 × 10 9 Ω or less, so that the operation of the semiconductor element to be mounted becomes abnormal. More preferably,
The thickness of the protective film is in the range of 250 pm to 3 nm. In addition, the ceramic substrate and the conductor forming the thin film conductor pattern in the circuit board of the present invention are not particularly limited, but common materials can be used. As the ceramic substrate, for example, A
Low dielectric constant materials such as 1N, BN, SiO 2 , SiC, borosilicate glass, and high thermal conductivity materials can be used.
By appropriately selecting the material of the ceramic base, a circuit board having a high signal propagation speed or excellent heat dissipation can be obtained. On the other hand, as a conductor, for example,
Metals such as Au, Cu, Ni, Ag, Pt may be used. The thin film conductor pattern is made of Ti, Cr, Ta, N
b, Zr, Mo, W, V, etc .;
A barrier metal layer made of t, Mo, Nb, W, V, Ti, or the like, and a conductive thin film made of the above metal may have a multilayer structure in which they are stacked in this order. Next, the manufacturing process of the circuit board of the present invention will be described. First, a ceramic substrate as described above is prepared, and one surface thereof is cleaned as necessary by a wet cleaning method, a reverse sputtering method, a dry etching method or the like. Subsequently, over the entire surface of the ceramic substrate, Ti, Cr,
A protective film is formed by forming at least one of Ta, Nb, Zr, Mo, W, V, and a compound of these metals to a thickness of 200 pm to 5 nm. As the film forming method, a general method such as a vacuum deposition method, a sputtering method, a cluster ion beam, an ion plating, an ion mixing, and a CVD is adopted. In each method, it is necessary to adjust conditions such as a substrate temperature, an atmosphere, a degree of vacuum, and a film forming speed according to the material of the protective film. Next, if necessary, a bonding layer having a thickness of about 1 to 100 nm and a thickness of 90 to 500 n are formed on the surface of the protective film.
After forming about m barrier metal layers, a conductive thin film is formed by, for example, sputtering or vacuum evaporation. Subsequently, the conductor thin film and, if necessary, the barrier metal layer and the bonding layer are patterned by wet etching or dry etching, and further patterned until the total thickness of the conductor thin film is about 200 nm to 10 μm. Then, a thin film conductor pattern to be a wiring is formed by appropriately performing electrolytic or electroless plating. After this, a dielectric layer, an interlayer insulating film, an upper wiring, and the like may be formed on the thin film conductor pattern as necessary. It also has the function of blocking the surface of the ceramic base. Hereinafter, the present invention will be described in detail with reference to examples. These examples are described for the purpose of facilitating understanding of the present invention, and do not particularly limit the present invention. Example A protective film and a thin-film conductor pattern were formed on one surface of a ceramic base under the conditions shown in Table 1 below. Nos. 1 to 21 were produced. That is, first, on one surface of the ceramic base,
Was formed by sputtering, and then a barrier metal layer made of Mo and having a thickness of 300 nm and a conductive thin film made of Au and having a thickness of 500 nm were sequentially formed by sputtering. Thereafter, the conductor thin film and the barrier metal layer are patterned by photolithography,
90 ° C. using an alkaline Au electroless solution
, A plated film was grown until the total thickness with the thin film conductor became 4 μm, and a thin film conductor pattern having a width of 50 μm and a pitch of 70 μm was formed as a wiring. Next, these samples were subjected to reliability tests using chemicals or plasma. That is, the samples were placed in the chemical and plasma atmospheres and conditions shown in Table 1, respectively, and thereafter, the surface roughness between the wirings (between the lines of the thin film conductor pattern), the resistance between the wirings, and the resistance of the thin film conductor pattern The presence or absence of peeling was evaluated. The results are shown in the same table. From the results shown in Table 1, in the circuit board of the above embodiment, the surface roughness between wirings,
It was confirmed that there was no practical problem in the line resistance value and the adhesion strength of the thin film conductor pattern. COMPARATIVE EXAMPLE Under the conditions shown in Table 1 below, a protective film and a thin film conductor pattern were formed on one surface of a ceramic substrate in the same manner as in the example. 22-2
5 was produced. However, these sample Nos. In the circuit boards Nos. 22 to 23, the thickness of the protective film was out of the range of 200 pm to 5 nm, and In the circuit boards 24 to 25, the protective film is not formed on the ceramic base, and the surface of the ceramic base is exposed between the wirings. These samples were evaluated for reliability with respect to various characteristics in the same manner as in the above examples. The results are shown in the same table. From the results shown in Table 1, in the case of a circuit board (sample No. 22) in which the thickness of the protective film is out of the predetermined range, the surface of the ceramic substrate between the wirings must be sufficiently shielded from the surrounding environment. Therefore, the surface roughness between the wirings after the reliability test was increased, and the deterioration of the ceramic base surface between the wirings was advanced. In the case of a circuit board (sample No. 23) in which the thickness of the protective film is out of the predetermined range, the line resistance is small, and the semiconductor element is mounted on the circuit board for operation. In this case, there is a high possibility of malfunction. Further, in the circuit board on which no protective film is formed (Sample Nos. 24 and 25), the surface roughness between the wirings is remarkably large, and the thin film conductor pattern is peeled off after the reliability test. It was confirmed that the adhesion strength of the thin film conductor pattern was insufficient. [Table 1] As described in detail above, according to the present invention,
A highly reliable circuit board having improved environmental resistance on the surface of a ceramic substrate during a manufacturing process and for a long time after the manufacturing is provided.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 小岩 馨 神奈川県川崎市幸区小向東芝町1番地 株式会社東芝総合研究所内 (72)発明者 岩瀬 暢男 神奈川県川崎市幸区小向東芝町1番地 株式会社東芝総合研究所内 (56)参考文献 特開 平2−205096(JP,A) (58)調査した分野(Int.Cl.7,DB名) H05K 1/09 H05K 3/38 C04B 37/00 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kaoru Koiwa 1 Toshiba-cho, Komukai-shi, Kawasaki-shi, Kanagawa Prefecture Inside Toshiba Research Institute, Inc. (72) Inventor Nobuo Iwase 1 Toshiba-cho, Komukai-shi, Kawasaki-shi, Kanagawa Address Toshiba Research Institute, Inc. (56) References JP-A-2-205096 (JP, A) (58) Fields investigated (Int. Cl. 7 , DB name) H05K 1/09 H05K 3/38 C04B 37 / 00

Claims (1)

(57)【特許請求の範囲】 【請求項1】 セラミック基体と、該セラミック基体の
一表面全体を被覆した、Ti、Cr、Ta、Nb、Z
r、Mo、W、Vおよびこれら金属の化合物の少なくと
も一種からなる膜厚200pm〜5nmの保護膜と、該
保護膜上に形成された薄膜導体パターンとを具備する回
路基板。
(57) [Claims 1] Ti, Cr, Ta, Nb, Z coated on a ceramic substrate and an entire surface of the ceramic substrate
A circuit board comprising: a protective film of at least one of r, Mo, W, V, and a compound of these metals having a thickness of 200 pm to 5 nm; and a thin-film conductor pattern formed on the protective film.
JP24487092A 1992-09-14 1992-09-14 Circuit board Expired - Lifetime JP3367688B2 (en)

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JP3367688B2 true JP3367688B2 (en) 2003-01-14

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Publication number Priority date Publication date Assignee Title
US20050064724A1 (en) * 2001-09-10 2005-03-24 Takashi Sugino Method and apparatus for forming low permittivity film and electronic device using the film

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