JP3376239B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a circuit formed inside is protected from noise and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, for a semiconductor device formed by forming a predetermined circuit on a semiconductor substrate, noise shielding is performed so as to protect the formed circuit from noise.
That is, as in the first conventional technique whose cross-sectional view of the main part is shown in FIG. 14, noise shielding is performed on the semiconductor substrate 1 in the vicinity of the circuit region 2 where the circuit that is the object of noise protection of the semiconductor substrate 1 is formed. The diffusion layer 3 for the is formed. Then, the first metal layer 4 and the second metal layer 5 are electrically connected to the diffusion layer 3.
Is provided, and the diffusion layer 3 is kept at a predetermined potential through the metal layers 4 and 5 to protect it from noise.
In addition, 6 is a well, 7 is a gate, 8 is a source / drain diffusion layer, 9 is a source / drain formed in the same step as the first metal layer 4, and 10 is a plurality of insulating layers. Is an insulating layer formed by.

In such a structure, the adjacent circuit or the like on the semiconductor substrate 1 is used as a generation source, and the noise coming from the lateral direction along the substrate surface is relatively well shielded. . However, it is relatively weak against noise coming from the direction crossing the substrate surface, for example, from above.

Therefore, after the second metal layer 5 is formed, as in the second conventional technique whose cross-sectional view of the main part is shown in FIG. 15 so as to shield the noise from the direction crossing the substrate surface, a new metal layer 5 is formed. Covers the upper part of the circuit area 2 that requires noise shielding,
The third metal layer 11 is formed on the diffusion layer 3 so as to be electrically connected through the first metal layer 4 and the second metal layer 5. In addition, 12 is an insulating layer formed by laminating a plurality of insulating films.

With the above-described structure, similar to the first prior art, the noise is relatively well shielded against the noise from the lateral direction generated by the adjacent circuit or the like on the semiconductor substrate 1, and It also relatively well shields noise from above that intersects the substrate surface. However, in order to form the third metal layer 11 covering the upper part of the circuit region 2,
It is necessary to newly form a mask to form a metal layer and to form an insulating layer 12 by adding an insulating film.

On the other hand, when a capacitor is added for noise protection of a circuit formed inside the semiconductor device, the additional capacitor must be provided outside the semiconductor device.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above situation, and it is possible to reduce the noise of a circuit formed inside at a low cost with a simple structure without causing an increase in the manufacturing process. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can be protected from the heat.

[0008]

The semiconductor device of the present invention comprises:
In a semiconductor device in which a noise shielding layer is provided for noise shielding with respect to a predetermined circuit formed on a semiconductor substrate, the noise shielding layer is located at a position lower than the peripheral surface of an insulating layer formed on the semiconductor substrate. A conductive film applied so as to cover the upper side of a predetermined circuit on the upper surface formed as
When the conductive film is formed by coating, it conducts to a predetermined portion in the semiconductor substrate through the opening formed in the insulating layer,
It is characterized in that a predetermined potential is applied to the conductive film, and further, an opening is opened on a power supply wiring formed around a predetermined circuit for shielding noise. it is intended, characterized in, also half
A noise shielding layer is applied to the specified circuit formed on the conductor board.
Provide noise shielding and layer on top of semiconductor substrate
Applied the identification paint on the upper surface of the insulating layer
In the conductor device, the identification paint is used as the conductive paint to form the insulating layer.
Formed on the insulating film while covering the upper surface of the predetermined circuit above
Conduction through the opening to the noise shielding layer in the semiconductor substrate
And the first conductive film formed on the first conductive film.
Do not contact the dielectric film and the first conductive film on this dielectric film
And a second conductive film that is stacked .

The semiconductor device manufacturing method of the present invention is
A test process for determining the characteristics of a plurality of semiconductor chips provided with a predetermined circuit that needs to shield noise formed on a semiconductor wafer, and to cover the upper side of the predetermined circuit only for the semiconductor chips of the semiconductor wafer that have been determined to be good. A good product identification paint formed of a conductive substance is applied to the semiconductor chip surface, and the application of the good product identification paint is conducted to a predetermined internal portion through an opening opening on the surface of the semiconductor chip that has been judged good. And a dicing step of cutting and separating the semiconductor wafer into individual semiconductor chips after the coating application step and collecting only the semiconductor chips coated with the non-defective product identification coating. .

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

First, a first embodiment will be described with reference to FIGS. 1 is a cross-sectional view of an essential part, FIG. 2 is a plan view of the essential part, FIG. 3 is a plan view of a semiconductor wafer after a test process, and FIG. 4 is an essential part of a semiconductor chip in a first modification. 5 is a plan view of an essential part of a semiconductor chip in a second modification, FIG. 6 is a plan view of a semiconductor chip in a third modification, and FIG. 7 is a fourth view. It is a top view of a semiconductor chip in a modification.

In FIGS. 1 to 7, reference numeral 21 denotes a semiconductor device in which a circuit is formed on a semiconductor substrate 22, and a semiconductor wafer 23 is provided on each semiconductor chip 24 on which a circuit is formed. It is formed by being cut and separated in the dicing process. The semiconductor device 21 also includes a circuit formed on the semiconductor substrate 22 that includes a predetermined circuit that requires noise shielding for protection from noise.

A well 26 is formed in a predetermined portion above the semiconductor substrate 22 in a circuit region 25 in which a predetermined circuit requiring noise shielding is formed, and a source / drain diffusion layer is further provided at a predetermined position above the well 26. 27 is formed, and a diffusion layer 28 for noise shielding is formed. In addition, a gate 30 is formed on the semiconductor substrate 22 via a gate insulating film 29.
, 31n and second metal layers 32a, 32b, ..., 32n are formed on the semiconductor substrate 22 while forming a plurality of insulating films on the semiconductor substrate 22. Then, an insulating layer 33 is formed. The first metal layers 31a, 31b, ... Are provided so as to be electrically connected to the respective source / drain diffusion layers 28 to form a required circuit, and the second metal layers 32a, 32b.
b, ... Corresponding predetermined first metal layers 31a, 31b,
It is provided so as to be connected to.

Further, the noise shielding diffusion layer 28 is also formed so as to conduct the corresponding first metal layer 31n so that the second metal layer 32n conducts to the first metal layer 31n. It is provided. On the other hand, on the upper surface of the insulating layer 33, a conductive film 34 is provided by applying and curing a conductive paint in a predetermined range so as to cover above the circuit region 25 where the circuit requiring noise shielding is formed. Then, the conductive film 34 fills the inside of the opening 35 formed in the insulating layer 33 above the circuit region 25 at the time of applying the conductive paint, and is electrically connected to the upper surface of the second metal layer 32n exposed in the opening 35. Membrane 3
4, the conductive film 34 and the diffusion layer 28 are connected to each other through the first metal layer 31n and the second metal layer 32n, and a predetermined potential is applied to the conductive film 34. . In addition, 36 is an insulating layer 33 for connecting to the outside.
The opening for bonding formed in the
The upper surface of the metal layer 32b is exposed.

Further, the semiconductor device 2 having the above structure
The manufacturing process of No. 1 is as follows. That is, a predetermined circuit or the like for forming the semiconductor device 21 is formed in each of the portions where the semiconductor chips 24 are formed on the semiconductor wafer 23, and the insulating layer 33 is formed on the semiconductor substrate 22 to form the openings 35, The semiconductor wafer 23 in which 36 is opened is formed. After this, the semiconductor wafer 23
In the test process, the characteristics of the circuits and the like formed on the individual semiconductor chip 24 forming portions are checked, and the individual semiconductor chips 2 formed on the semiconductor wafer 23 are checked.
A pass / fail judgment of 4 is performed.

Then, in the next coating process, only the semiconductor chip 24 which has been judged good in the test process is colored in a predetermined portion of its surface by a conductive material so that it can be easily identified. A conductive paint, which is a non-defective product identification paint, is applied and cured, whereby the conductive film 34 is attached to the upper surface of the insulating layer 33. The predetermined portion of the surface of the semiconductor chip 24 to which the conductive paint is applied is an upper portion of the circuit region 25 in which a predetermined circuit that requires noise shielding formed in the semiconductor chip 24 is formed, and its range is also the circuit region. It covers the upper part of 25. Further, regarding the application of the conductive paint, for example, by using a stamp formed so as to match the shape of the tip with the shape of the application portion,
It is performed by applying with a brush. Note that the opening 35 of the insulating layer 33 is buried by applying the conductive paint, and the formed conductive film 34 is electrically connected to the upper surface of the second metal layer 32n exposed in the opening 35.

Next, in the dicing process, the semiconductor wafer 23 which has finished the coating process is cut and separated into individual semiconductor chips 24. Among the separated semiconductor chips 24, the semiconductor chip 24 to which the conductive coating material of the non-defective product, which is a non-defective product, is applied is picked up by a transfer unit (not shown) and transferred to a predetermined place. Then, the transferred semiconductor chip 24 is mounted on a lead frame and resin-sealed, though not shown.

Since the semiconductor device 21 is constructed as described above, the conductive film 3 is formed in the circuit region 25 requiring noise shielding.
4 is provided, and relatively good noise shielding is performed against noise from the lateral direction originating from an adjacent circuit or the like on the semiconductor substrate 22, and also against noise from above crossing the substrate surface. Noise is shielded by the conductive film 34 to which a predetermined potential is applied, so that the circuit formed inside can be protected from noise. Further, regarding the formation of the conductive film 34, particularly, it is not necessary to newly form a metal layer or to additionally form a plurality of insulating films, and it is possible to easily form the conductive film simply by applying a conductive paint. be able to. Furthermore, in the step of applying the conductive paint, when the quality of the semiconductor chip 24 on the semiconductor wafer 23 is determined, the marking with the identification paint that is conventionally performed on the defective semiconductor chip 24 is replaced. Then, by applying the conductive paint as the non-defective product identifying paint to the non-defective semiconductor chip 24, the pass / fail identification and the formation of the conductive film 34 can be performed at the same time, and the manufacturing process is further simplified. .

Further, in the above structure, the opening 35 formed in the insulating layer 33 is formed in the circuit region 25. However, the present invention is not limited to this, and FIG. 4 shows a first modification. As shown in the plan view of the main part, the semiconductor chip 24a has an insulating layer 33a formed on the semiconductor substrate.
A plurality of openings 35a are formed so as to be arranged along the boundary of the circuit region 25. In this way, when a conductive film (not shown) is formed by coating so as to cover the circuit region 25, the contact resistance between the conductive film (not shown) exposed in the opening 35a and the conductive film is reduced, and the opening is also reduced. Three
In the portion where 5a is arranged, it is possible to excellently shield noise in the lateral direction along the substrate surface.

Further, as shown in the plan view of the main part in the second modification in FIG. 5, the semiconductor chip 24b is arranged on the insulating layer 33b formed on the semiconductor substrate along the boundary of the circuit region 25. An opening 35b is formed above the power supply wiring (not shown) provided along the power supply wiring. By doing so, when a conductive film (not shown) is formed by coating so as to cover the circuit region 25, the opening 35 is formed.
The contact resistance between the power supply wiring exposed in b and the conductive film is reduced, and noise in the lateral direction along the substrate surface can be shielded well.

Further, as shown in the plan view of the third modification in FIG. 6, the semiconductor chip 24c is provided with a power supply wiring (not shown) at a position apart from the circuit region 25 of the insulating layer 33c formed on the semiconductor substrate. An opening 35c ₁ is formed in the upper part along the power supply wiring, and an opening 35 in which a metal layer electrically connected to a diffusion layer for noise shielding (not shown) is exposed inside.
c ₂ is formed. By doing so, when a conductive film (not shown) is formed by coating so as to cover the circuit region 25 and to electrically connect to the power supply wiring at the opening 35c ₁ and to the metal layer at the opening 35c ₂ , 35c ₁ , 3
The contact resistance between the power supply wiring and the metal layer and the conductive film is reduced within 5c ₂ . Further, when the integration density in the vicinity of the circuit region 25 is high, the conductive film can be easily electrically connected to the power supply wiring and the noise shielding diffusion layer at a position away from the circuit region 25.

Further, as shown in the plan view of the fourth modification in FIG. 7, in the semiconductor chip 24d, the opening 35 is formed in the circuit region 25 in the insulating layer 33d formed on the semiconductor substrate. In addition, a plurality of openings 35a are arranged along the boundary of the circuit region 25, and an opening 35b is formed above the power supply wiring (not shown). An opening 35c ₁ is formed on the upper side, and an opening 35c _{2 for} exposing a metal layer electrically connected to a noise shielding diffusion layer (not shown) is formed inside. By doing so, the upper side of the circuit area 25 is covered and the openings 35, 35a,
When a conductive film (not shown) is formed by coating 35b, 35c ₁ and 35c ₂ so as to be electrically connected to the metal layer and the power supply wiring, respectively, the same effect as in the above-described embodiment and modification can be obtained.

Next, a second embodiment will be described with reference to FIG. FIG. 8 is a partial sectional view.

In FIG. 8, reference numeral 41 denotes a semiconductor device having a circuit formed on the semiconductor substrate 22.
An insulating layer 42 formed by laminating a plurality of insulating films is provided on the wiring 2, and a circuit region 25 including a predetermined circuit that requires noise shielding is provided. And circuit area 25
Is provided with a power supply wiring 44 having a step 43 in the width direction along the boundary portion thereof. The lower side of the power supply wiring 44 with the step 43 as a boundary is the circuit area 25 side, and the higher side is the opposite side of the circuit area 25. Further, the power supply wiring 4 is provided above the step 43 portion of the power supply wiring 44.
Insulating layer 42 so that the upper surface is exposed along the arrangement direction of 4
Is formed with an opening 45.

Power supply wiring 4 having a step 43 in the width direction
Reference numeral 4 denotes a plurality of metal layers formed while laminating a plurality of insulating films. The shape of the upper surface of the insulating layer 42 before the opening 45 is formed is shown by a chain double-dashed line in FIG. It has a shape having such a step 46. Therefore, the opening 4
5, the height difference between the upper surface of the insulating layer 42 on the circuit region 25 side of the opening 45 and the upper surface of the insulating layer 42 on the side opposite to the circuit region 25 is low, and the upper surface of the circuit region 25 side is low. It has become a thing.

Then, on the upper surface of the insulating layer 42 above the circuit region 25 which is one step lower than the surroundings in this way, for example, in the same way as in the first embodiment, the quality of the semiconductor wafer is judged to be good or bad. The conductive film 47 is applied so as to cover the circuit region 25 by a technique such as identification marking for applying a conductive paint to the semiconductor chip. In addition, when the conductive film 47 is formed, the conductive paint fills the opening 45, and the conductive film 47 and the exposed upper surface of the power supply wiring 44 are electrically connected.

Further, the deposited conductive film 47 has a deposition thickness smaller than the height difference of the insulating layer 42 in the opening 45, so that the opening 45 has a higher side of the insulating layer 42. The side wall limits the flow of the conductive paint so that the excess conductive film 47 does not inadvertently flow out to a portion other than above the circuit region 25. As described above, according to the present embodiment, the conductive film 47 that covers only the upper portion of the circuit region 25 can be formed easily and reliably.

Next, a third embodiment will be described with reference to FIGS. 9 is a cross-sectional view of the main part, FIG. 10 is a plan view, FIG. 11 is a cross-sectional view of the main part in the first modification, and FIG. 12 is a cross-sectional view of the main part in the second modification. FIG. 13 is a plan view of a main part in the second modification.

9 to 13, reference numeral 51 denotes a semiconductor device having a circuit formed on the semiconductor substrate 22, and an insulating layer 52 formed by laminating a plurality of insulating films is provided on the semiconductor substrate 22. Thus, a circuit area 25 including a predetermined circuit that needs noise shielding is provided. And
On the upper surface of the insulating layer 52 above the circuit region 25, for example, the first
The first conductive film 53 covers the upper part of the circuit region 25 by a technique such as identification marking in which a conductive paint is applied / cured on the semiconductor chip that is judged good by the quality judgment on the semiconductor wafer as in the embodiment. Have been worn.
The deposited first conductive film 53 fills the opening 35 formed in the insulating layer 52 and is exposed in the opening 35.
Is electrically connected to the upper surface of the metal layer 32n.

On the upper surface of the first conductive film 53, a dielectric film 54 formed by applying and hardening a dielectric substance so as to have a predetermined film thickness is deposited, and further on the upper surface of the dielectric film 54. The second conductive film 55 is applied so as not to contact the first conductive film 53 by applying and curing the conductive paint. As a result, the capacitor 56 for noise protection is formed on the insulating layer 52 by the first conductive film 53, the dielectric film 54, and the second conductive film 55. On the other hand, the deposited second conductive film 55 fills the opening 57 formed in the insulating layer 52 and is exposed in the opening 57.
It is in continuity with the upper surface of m. As a result, the second conductive film 55
Is electrically connected to the noise shielding diffusion layer 58 provided on the semiconductor substrate 22 through the second metal layer 32m and the first metal layer 31m.

And, in the case of such a configuration,
In the semiconductor device 51, the circuit region 25 requiring noise shielding is covered with the first conductive film 53 and the like, and the noise shielding is relatively good against the noise from the lateral direction originating from the circuit adjacent to the semiconductor substrate 22. In addition to the above, the first conductive film 53 is also provided against noise from above that intersects the substrate surface.
The noise is shielded by the above, and the circuit formed inside can be protected from the noise. Also, the noise protection capacitor 56 does not need to be provided externally, and the first conductive film 53, the dielectric film 54, and the second conductive film 55 are attached to the insulating layer 52 so as to have the largest possible area. By doing so, it is relatively easy to
6 can be formed.

In the above structure, the capacitor 56 formed on the insulating layer 52 is formed by sequentially coating the first conductive film 53, the dielectric film 54, and the second conductive film 55. However, in the semiconductor device 51a, the capacitor 56a is connected to the insulating layer 52 as shown in FIG.
After depositing the first conductive film 53 on the top surface of the first conductive film 53 in the same manner as in the first embodiment, a flat plate-shaped dielectric 54a having a predetermined shape and a predetermined film thickness is adhered to the upper surface of the first conductive film 53, and the dielectric Body 54
The second conductive film 55a is deposited so as not to come into contact with the first conductive film 53 by applying and curing a conductive paint on the upper surface of a. The second conductive film 55a fills the opening 57 formed in the insulating layer 52 and is electrically connected to the upper surface of the second metal layer 32m exposed in the opening 57.

With this structure, the same action and effect as those of the third embodiment can be obtained, and the capacitance can be made accurate.

Further, in the semiconductor device 51b, the capacitor 56b is formed on the insulating layer 52 as in the second modification in which FIG. 12 is a cross-sectional view of the main part and FIG. 13 is a plan view of the main part. After depositing the first conductive film 53 as in the first embodiment, a flat plate-shaped dielectric 54b having a predetermined shape and a predetermined thickness is adhered to the upper surface of the first conductive film 53, and the dielectric 54b is further formed. A flat plate-shaped conductor 55b having a predetermined shape and a predetermined thickness is adhered to the upper surface of the first conductive film 53 by a conductive adhesive so as not to come into contact with the first conductive film 53. Then, one end of the bonding wire 59 is bonded to the upper surface of the conductor 55b, and the other end of the bonding wire 59 is bonded to the bonding pad 61 such as the mounting substrate 60 on which the semiconductor device 51b is mounted.

Even with this configuration, the above third
It is possible to obtain the same operation and effect as those of the embodiment and to make the capacitance accurate.

[0036]

As is apparent from the above description, according to the present invention, a conductive film is formed by coating on the upper surface of an insulating layer formed on a semiconductor substrate so as to cover the upper side of a circuit requiring noise protection. With the structure in which a predetermined part in the substrate and the conductive film are electrically connected through the formed opening, noise can be shielded without going through a complicated manufacturing process, and a simple structure can be provided inside at low cost. There is an effect that noise protection of the formed circuit can be performed.

[Brief description of drawings]

FIG. 1 is a sectional view of an essential part showing a first embodiment of the present invention.

FIG. 2 is a plan view of a main part according to the first embodiment of the present invention.

FIG. 3 is a plan view of a semiconductor wafer after a test process according to the first embodiment of the present invention.

FIG. 4 is a plan view of a main part of a semiconductor chip according to a first modification of the first embodiment of the present invention.

FIG. 5 is a plan view of a main part of a semiconductor chip according to a second modification of the first embodiment of the present invention.

FIG. 6 is a plan view of a semiconductor chip according to a third modification of the first embodiment of the present invention.

FIG. 7 is a plan view of a semiconductor chip according to a fourth modification of the first embodiment of the present invention.

FIG. 8 is a partial cross-sectional view of the second embodiment of the present invention.

FIG. 9 is a cross-sectional view of a main part according to a third embodiment of the present invention.

FIG. 10 is a plan view of the third embodiment of the present invention.

FIG. 11 is a sectional view of an essential part in a first modified example of the third embodiment of the present invention.

FIG. 12 is a cross-sectional view of a main part in a second modification of the third embodiment of the present invention.

FIG. 13 is a plan view of an essential part in a second modification of the third embodiment of the present invention.

FIG. 14 is a cross-sectional view of a main part showing a first conventional technique.

FIG. 15 is a sectional view of an essential part showing a second conventional technique.

[Explanation of symbols]

22 ... Semiconductor substrate 25 ... Circuit area 28 ... Diffusion layer 31n ... first metal layer 32n ... second metal layer 33 ... Insulating layer 34 ... Conductive film 35 ... Opening

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kazuhiko Ohashi, Kazuhiko Ohashi 25-1, Ekimaehonmachi, Kawasaki-ku, Kanagawa Prefecture Toshiba Microelectronics Stock Association In-house (72) Inventor Kimio Maruyama 25-1, Kawasaki-ku, Kawasaki-ku, Kanagawa Prefecture 1 Toshiba Microelectronics Stock Company In-house (72) Inventor Seiichi Kureya 25-1 Ekimaehonmachi, Kawasaki-ku, Kawasaki, Kanagawa Toshiba Microelectronics Stock Company In-house (56) Reference JP-A-57-30344 (JP, A) JP-A-4- 179126 (JP, A) JP-A-6-318597 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/3205 H01L 21/301 H01L 21/822 H01L 27/04

Claims (4)

(57) [Claims] 1. In a semiconductor device in which a noise shielding layer is provided for a predetermined circuit formed on the semiconductor substrate to shield the noise, the noise shielding layer is an insulating layer formed on the upper portion of the semiconductor substrate. Lower than the surrounding surface of
Is formed on the upper surface of the semiconductor substrate through the opening formed in the insulating layer by coating the conductive film. A semiconductor device which is configured to conduct to a predetermined portion and to apply a predetermined potential to the conductive film. 2. The semiconductor device according to claim 1, wherein the opening is formed on a power supply wiring formed around a predetermined circuit for shielding noise. 3. A predetermined circuit formed on a semiconductor substrate
A noise shielding layer is provided to shield noise, and
Apply an identification paint on the top surface of the insulating layer that is layered on top of the conductor board.
In a semiconductor device adapted to be applied, the identification paint
As conductive paint on the upper surface of the insulating layer above the predetermined circuit
And covers the above through the opening formed in the insulating film.
A first conductive layer connected to the noise shielding layer in the semiconductor substrate;
A conductive film, and a dielectric film laminated on the first conductive film,
Laminating on the dielectric film so as not to contact the first conductive film
And a second conductive film that has been formed.
Conductor device. 4. A noise shield formed on a semiconductor wafer
Characteristics of multiple semiconductor chips with required circuits
Test process to determine the quality of the semiconductor wafer
Above the specified circuit only for the separated semiconductor chip
A non-defective paint that is made of a conductive material to cover
The good product identification paint applied to the surface of the semiconductor chip
The semiconductor chip that has been successfully judged by applying
Conduction is conducted to a predetermined internal part through an opening that opens on the surface.
And a semiconductor coating step after the coating step.
The wafer is cut and separated into individual semiconductor chips, and the non-defective product is coated.
Dice that collects only the semiconductor chips coated with the material
Of a semiconductor device, characterized by comprising:
Production method.