JP3384008B2 - Image memory processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image memory processing device used for time axis correction processing and two-dimensional digital filtering processing of image data. It is applied to a video tape recorder or the like having a processing function. 2. Description of the Related Art Generally, in a reproducing system of a video tape recorder, reproduced image data obtained by digitizing a reproduced signal containing a jitter component in a tape running system is written in a memory device, and the read image data is read from the memory device by a reference read clock. A time axis correction process for removing the jitter component in the tape running system by reading the reproduced image data with a reference read clock is performed. This time axis correction processing includes a memory device having a storage capacity for several lines,
A frame memory having storage for frames has been used. [0003] Conventionally, a memory device for time axis correction processing provided in a reproduction system of a video tape recorder is often used only for reproduction signal processing. Even when used in a recording system, it is only used as a fixed delay line with a 1H delay for delay adjustment of a luminance signal and a chroma signal. In recent years, with the development of digital image processing technology, image processing functions such as image enlargement and reduction processing by interpolation using an image memory have been developed. Video tapes equipped with such image processing functions in the recording system In the recorder, a memory device for image processing in a recording system and a memory device for time axis correction processing in a reproduction system are separately provided. The memory device for image processing was used only for signal processing in the recording system, and the memory device for time axis correction processing was used only for signal processing in the reproduction system. There was a problem that the efficiency was extremely low. SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to increase the efficiency of use of a memory and to simplify the system configuration of a video tape recorder, and to provide a memory for image processing in a recording system and a time axis correction processing in a reproduction system. The present invention provides an image memory processing device having a function of performing a filtering process and a time axis correction process by sharing a memory for image processing. [0005] In order to solve the above-mentioned problems, an image memory processing apparatus according to the present invention comprises:
A plurality of line memories each including a random access memory having a storage capacity for storing image data for a line, and a random access having a storage capacity for storing image data for a plurality of lines by each of the line memories in the first operation mode A storage unit that functions as a memory, and in the second operation mode, functions as a delay unit that outputs in parallel image data provided with a delay amount of one to several lines by each of the line memories; A writing control unit that controls writing of input image data, a reading control unit that controls reading of image data from the storage unit, and an image data that is output in parallel from the storage unit in the second operation mode. A filter unit for performing at least a filtering process of a vertical method of an image using the filter unit; And a mode setting means for switching between the first operation mode and the second operation mode. In the first operation mode, image data which has been subjected to time axis correction processing by the storage unit in the first operation mode is output. In the second operation mode, the image data filtered by the filter unit is output. In the image memory processing apparatus according to the present invention, the operation modes of the write control means and the read control means for controlling writing and reading of image data to and from the storage section are set by the mode setting means to the first operation mode. And switch to the second operation mode. In the first operation mode, the storage unit functions as a random access memory having a storage capacity for storing image data for a plurality of lines in each line memory, and the image obtained after the time axis correction processing is performed by the storage unit. Output data. In the second operation mode,
Using the image data output in parallel from the storage unit, the filter unit outputs image data that has been subjected to at least a vertical filtering process of the image. An embodiment of an image memory processing device according to the present invention will be described below in detail with reference to the drawings. An image memory processing apparatus according to the present invention is applied to a recording / reproducing system of a video tape recorder as shown in FIG. [0009] In FIG. 1, the video signal processing circuit 1, a reproduced signal PB obtained in the imaging signal S _IN and reproducing system obtained by the imaging unit (not shown) in the recording system is supplied. The video signal processing circuit 1 generates a chroma signal C and a luminance signal Y formed from the imaging signal S _IN and the reproduction signal PB. The chroma signal C and the luminance signal Y generated by the video signal processing circuit 1 are independently taken out,
The signals are digitized by A / D converters 2 and 3 with an AFC clock (not shown). The chroma signal digitized by the A / D converter 2 is converted by the decoder 4 into a color difference signal RB /
The image data is decoded into BY and supplied to the image memory processing device 5. Here, the band of the color difference signal RB / BY obtained by the decoder 4 is limited by a low-pass filter (not shown), and the data rate is set to fsc. Also,
When the A / D is 8 bits, for example, the color difference signal is divided into upper 4 bits (H) and lower 4 bits (L), and R-Y
Multiplexing as (H) / BY (H) / RY (L) / BY (L) can reduce the number of pins of the interface. The luminance signal digitized by the A / D converter 3 is directly supplied to the image memory processing device 5. The image memory processing device 5 has an image processing function such as a time axis correction process and an interpolation filter process as described later, and performs a predetermined image process according to an operation mode on the basis of the luminance signal and the color difference signal. Apply to The color difference signal that has been subjected to the image processing by the image memory processing device 5 is returned to a chroma signal by the encoder 6 and is converted to an A / D converter 7.
Is supplied to the video signal processing circuit 1 via the. The luminance signal subjected to the image processing by the image memory processing device 5 is supplied to the video signal processing circuit 1 via the A / D converter 8. The image memory processing device 5 is, for example, shown in FIG.
And the input luminance signal Y
And the color difference signals RB / BY are control signals such as a composite sync (C. sync), a vertical synchronization signal (VD), a horizontal synchronization signal (HD), a line alternate (LAT), and a field determination signal (FLT). At the same time. And
The luminance signal Y and the color difference signals RB / BY are sent to a storage unit (MEMORY) 13 via a write buffer (WRITE BUFFER) 12.
Is written to. Here, as shown in FIG. 3, the storage section 13 is a random access memory having a storage capacity for storing a luminance signal Y and a color difference signal RB / BY for one line (1). A 5-line memory consisting of
32, 33, 34, 35, and the line memories 31,
32, 33, 34, and 35, an input selector 36 for selecting data to be written to the line memories 31, 32,
It is provided with three output selectors 37, 38 and 39 for selecting read data from 33, 34 and 35. The writing control unit (WRITE ADDRESS CONTROL) 18 controls the writing of data into the storage unit 13.
The write control unit 18 controls the write clock W
Input buffer (INPUT BUFFER) 11 in synchronization with CK
The data fetched into the storage unit 13 is written in order in the storage unit 13. The data written in the storage unit 13 is read out in synchronization with a read clock RCK according to a read address from a read control unit (READ ADDRESS CONTROL) 19, and is read out by a read buffer (READ BUFFER) 1.
5 taken out. Here, the luminance signal Y and the color difference signals RB / B
In the sync portion of the −Y video signal section, the sync switching is performed by the sync level change block 15. The replacement section is given by the read control unit 19. The first operation mode includes a time axis correction (TB
C) The operation mode of the processing, and the SYNCMUX block 16
Output buffer (OUTPUT BUFFER) 17
Is output in synchronization with RCK. In addition, control signals such as the field determination signal (FLT) other than the video signal pass through the delay latch unit 11 and are output through the SYNC MUX block 16 and the output buffer 17. When the TBC is OFF, the SY
The NC MUX block 16 operates in synchronization with WCK, and outputs the signal directly input from the input buffer 11 and the control signal from the delay latch unit 11 via the output buffer 17 as it is. The ON / OFF of the TBC is determined by the TBC ON / OF serially communicated via the serial interface 14 with a JOG determination signal from a signal input terminal (not shown).
F signal is sent to timing control unit (JOG TIMING CONTROL) 12
To control. Also, the write clock W at the time of TBCON
To match the average frequency of CK with the read clock RCK, the REFVD control unit 23 generates a phase reference signal (reference vertical synchronization signal REFVD) to be returned to the drum servo from the read clock RCK. In the first operation mode, as shown in FIG. 4, each of the line memories 31, 32, 3
Reference numerals 3, 34, and 35 are used by being divided into a first half and a second half, respectively. After writing a predetermined number of data from the head of H in synchronization with the write clock WCK, the write control unit 18 looks at the HD, and writes a predetermined number of data again from the head of H in the horizontal direction. A write address is generated by an address counter, and the input selector 36 is controlled so that each line memory is sequentially selected by a 5H counter incremented by 1H. When the write address is 2.5H, a WRST signal is generated. The 5H counter counts from 0 and returns to 0 when counting up to 4. On the other hand, the read control unit 19 counts in synchronization with the read clock RCK so as to start reading data from a position 2H away from the write address at the moment when TBCON is turned on in the first operation mode. The read address is controlled by the address counter and the 5H counter that perform the operation. Here, the clock overtaking detection section 40 generates a phase reference signal to be returned to the drum servo based on the positional relationship between the currently read RAM area and the WRST signal from the write control section 18.
The initial value of the VD control unit 23 is changed. This manages so that the read RCK does not overtake the write clock WCK. If the clock is likely to overtake, the read address is forcibly set to 2H.
The read control unit 1 outputs an RRST signal so as to cause a jump.
Give 9 Here, the read control unit (READ ADDRESS C)
ONTROL) is arranged so that the order of the read addresses can be changed in accordance with the mode information given via the serial interface 14, so that inverted output and folded output can be performed. The storage unit 13
Of the data of the color difference signal on the memory of RY (H) /
In the case of BY (H) / RY (L) / BY (L), if the read address is simply reversed, BY−Y
(L) / RY (L) / BY (H) / RY (H), and the system for unifying the data arrangement is broken and subsequent processing becomes complicated. Therefore, the control is performed so that the color difference signal among the read addresses can be read in units of 4 bytes. this is,
Since the lower 2 bits of the address counter correspond to a sequence of 4 bytes of color difference data, the lower 2 bits must be RY
The address can start from (H). In the case of inversion output or loopback output, processing can be easily performed by setting the start address and loopback address in 4-byte units. Next, the second operation mode is an operation mode of the filter processing, and is the one read out from the storage unit 3.
The H-delayed data is read in parallel and supplied to the filter unit 20 via the read buffer (READ BUFFER) 15. The filter section 20 functions as a linear interpolation filter having a configuration as shown in FIG. In the filter unit 20, the data rearranging circuit 51 converts the 4-bit multiplexed chrominance signal into 8 bits, and then delays the luminance signal and the chrominance signal. Then, the filtering in the vertical direction and the filtering in the horizontal direction are independently performed on the luminance signal and the color difference signal. That is, data Y1 for continuous 2H
H, Y2H. C1H and C2H are fetched from the storage unit 13 into the vertical filter block 52 via the data rearranging circuit 51, and vertical interpolation processing is performed using the vertical filter coefficient k given by the vertical filter coefficient generator 53. . Further, the filtering outputs VY and VC from the vertical filter block 52 are taken into a horizontal filter block 54, and a horizontal interpolation process is performed using a horizontal filter coefficient h given by a horizontal filter coefficient generator 55. The filtering outputs HY and HC output from the horizontal filter block 54 are output after the data rearrangement circuit 56 performs delay matching and data rearrangement. Here, the filtering process for the luminance signal will be specifically described. The filtering output VY of the vertical filter block 52 is obtained by the following equation: VY = Y1H · k + Y2H · (1-k). Here, Y1H is a luminance signal delayed by 1H, and Y2H is a luminance signal delayed by 2H. Also,
k is a coefficient of the interpolation filter. If this operation is performed directly, two multipliers are required, and the circuit scale becomes large. Therefore, as shown in FIG. 6, VY = Y1H ・ k + Y2H ・ (1-k) = Y2H + k ・ (Y1H-Y2H), and as shown in FIG. The vertical filter block 52 is configured. The filtering output HY of the horizontal filter block 53 is obtained by the following equation: HY = VY.h + VYD. (1-h) = VYD + h (VY-VYD). Such a horizontal filter block 5
3, two D delay circuits 65 and 66, as shown in FIG.
, A switch 67, a polarity inverter 68, and two adders 69,
71 and a multiplier 70. Here, VYD is a signal obtained by delaying VY by one or two read clocks RCK by the D delay circuits 65 and 66, and h is a coefficient of the interpolation filter. The switch 67 is
Switching control is performed by the horizontal direction filter coefficient generator 55. Since the color difference signal is a set of 4 bytes, the amount of delay D in the horizontal direction is equal to 4 bits of the read clock RCK.
Or eight. Here, the vertical direction filter coefficient generator 53 and the horizontal direction filter coefficient generator 55 load the initial value given via the serial interface 24 into the IIR filter, and thereafter correspond to the initial value. By continuously inputting the set values, each filter coefficient is obtained. When the output of the IIR filter exceeds the dynamic range, the read address is held. The hold signal of the vertical method is transmitted to the image memory processor 13.
Control signal VSTO so that the input signal to
It is output to the outside as P. The value corresponding to the initial value can be read from a ROM table or serial data. In the second operation mode, as shown in FIG. 7, each of the line memories 31, 32, 3
3, three lines are used. Then, the write control unit 1
8 and a reading control unit 19, a horizontal counter, and a 3H counter for controlling the input selector 36 and the output selector. The VH holding pulse from the filter coefficient generator 50 stops the increment of each counter. Sort data for filtering. The horizontal counter can change the read start address according to the filter coefficient. And
The write control unit 18 and the read control unit 19 access the line memories 31, 32, and 33 at independent addresses when writing and reading data, and further, read from and write to the line memory that is performing the writing. The access is made so that it is always different from the line memory being used. In writing, all data in the H direction is fetched, and in reading, only necessary data is read. Therefore, the same data can be read continuously from the same address. Further, for reading, all the line memories are accessed so that the addresses in the H direction are the same. As a memory input, common data is given to each line memory,
For the input address, data of 1H is written only to the line memory to which the write permission is given. The memory output simultaneously and independently reads out two line memories other than the line memory to which writing is being performed. The read address is accessed at the same point in the H direction of the two line memories. In this way, an independent address can be specified for each of the two port outputs. In the memory control in the first operation mode for performing the above-described time axis correction processing, the written data is read out without changing the order. However, the left-right inverted read, right return read, and left return read are also performed. I can do it. However, if the data is simply read from the reverse address, the arrangement of the color difference signals will be out of order. In the image memory processing device 5 of this embodiment, the ratio of the data of one sample of the chrominance signal to the data of four samples of the luminance signal is used. The color difference signal is simply read from the opposite direction, and the color difference signal is RY (H) /
Processing is performed such that one set of four samples maintaining the order of BY (H) / RY (L) / BY (L) is read in reverse order.
This means that if the address counter in the H direction has 10 bits, the luminance signal counts down from the last address, the color difference signal counts down the upper 8 bits out of 10 bits every 4 clocks, and the lower 2 bits are 0, 0.
Operate as a 2-bit up counter of 1, 2, 3, 0, 1, 2,... As described above, if the processing is performed at the addresses where the color difference signals are well separated, the right and left return reading can be easily performed. Further, in the second operation mode in which the above-described filter processing is performed, the read address processing of the memory is an arbitrary point, so that it is slightly complicated, but basically the above-described read address processing is performed. . For example, if the read address is in the phase of BY (H), the luminance signal is read from that address, and the color difference signal is the RY (H) paired with the designated BY (H). H)
The signal is read from a certain address (in this case, the previous address). This means that the upper 8 bits of the address are incremented every 4 clocks and the lower 2 bits are 2
Operate as a bit up counter. The resulting deviation from the originally designated address can be processed with the initial value of the filter coefficient. As described above, the memory read control in the horizontal read operation, the right turn readout, the left turn readout, and the filter readout process in the memory readout control in the normal time axis correction process lower the color difference signal readout in the lower order. It can be dealt with simply by handling two bits independently. As a result, processing can be performed without changing the timing and specifications of input / output signals. In addition, signal processing can be performed without being limited to modes such as recording and reproduction. As described above, in the image memory processing device according to the present invention, the operation modes of the write control means and the read control means for controlling the writing and reading of image data to and from the storage unit are set. Means for providing a first mode of operation and a second mode of operation.
In the first operation mode, the storage unit is made to function as a random access memory having a storage capacity for storing a plurality of lines of image data in each line memory. Can output image data subjected to
In the operation mode, image data that has been subjected to at least a vertical filtering process of an image by the filter unit can be output using the image data output in parallel from the storage unit. Therefore, according to the present invention, an image memory having a function of performing filter processing and time axis correction processing by sharing a memory for image processing in the recording system and a memory for time axis correction processing in the reproduction system. A processing device can be provided, the use efficiency of the memory can be increased, and the system configuration of the video tape recorder can be simplified.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a main configuration of a recording / reproducing system of a video tape recorder to which an image memory processing device according to the present invention is applied. FIG. 2 is a block diagram showing a configuration of an image memory processing device according to the present invention. FIG. 3 is a block diagram illustrating a schematic configuration of a storage unit in the image memory processing device. FIG. 4 is a block diagram for explaining a function of the image memory processing device in a first operation mode; FIG. 5 is a block diagram illustrating a schematic configuration of a filter unit in the image memory processing device. FIG. 6 is a block diagram showing a specific configuration of the filter unit. FIG. 7 is a block diagram for explaining a function of the image memory processing device in a second operation mode. [Description of Signs] 5 ... Image memory processing device 13 ... Storage unit 18 ... Write control unit 19 ... Read control unit 24 ... Serial interface 31-35 Line memory 36 Input selector 37-39 Output selector

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI H04N 9/808 H04N 9/89 C 9/896

Claims (1)

(57) [Claim 1] A plurality of line memories each comprising a random access memory having a storage capacity for storing image data for one line, and each line memory in the first operation mode is provided. Functions as a random access memory having a storage capacity for storing image data for a plurality of lines. In the second operation mode, image data given a delay amount of one to several lines by each line memory can be used in parallel. A storage unit functioning as a delay unit for outputting, a write control unit for controlling writing of input image data to the storage unit, a read control unit for controlling reading of image data from the storage unit, A filter unit that performs at least a vertical filtering process on an image using image data output in parallel from the storage unit in the operation mode , The operation mode of the write control means and read control means first
And a mode setting means for switching between the first operation mode and the second operation mode. In the first operation mode, image data which has been subjected to the time axis correction processing by the storage unit is output to the input image data. An image memory processing device for outputting image data that has been subjected to filter processing by the filter unit in the operation mode of (1).