JP3386083B2 - Silicon wafer processing method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for treating a silicon wafer, and more particularly to removing fine defect nuclei on the surface of the silicon wafer.

[0002]

2. Description of the Related Art Although a small number of microdefect nuclei are present on the surface of a silicon wafer formed by a pulling method, a method for removing the defects is disclosed in Japanese Patent Laid-Open No. 3-233936.
There is one disclosed in the publication. That is, in the publication,
It is disclosed that heat treatment of a silicon wafer at 1100 ° C. for 2 hours reduces defects.
The heat treatment of Hr cannot reduce the defects,
It is described that heat treatment at 0 ° C. and 18 hours causes new defects.

[0003]

According to the description of the above publication, defects are reduced by heat treatment at 1100 ° C. and 2 Hr, and heat treatment at 700 ° C. and 5 Hr and 1100 ° C., 18
Although the finding that heat treatment of Hr is unfavorable is certainly obtained, there is practically no teaching as to which range of heat treatment conditions should be selected. Therefore, it is an object of the present invention to provide preferable heat treatment conditions for removing minute defects on the surface of a silicon wafer, and at the same time, prevent the gettering effect from decreasing.

[0004]

The present inventor has conducted extensive research to achieve the above-mentioned object, and has obtained a preferable heat treatment condition for removing micro defects. That is, according to the present invention, the silicon wafer formed by the pulling method is treated with 11.1-
1.04 × 10 ⁻² × T <log (t) <6.0-4.3 ×
10 ⁻³ × T (where T is the heat treatment temperature in ° C, t
Is a heat treatment time within the range of Hr unit), and is a method for treating a silicon wafer.
At that time, 17.5-1.57 × 10 ⁻² × T <log (t)
It is more preferable to perform the heat treatment within the range of <4.4-3.2 × 10 ⁻³ × T. Further, subsequent to the above heat treatment (hereinafter referred to as high temperature heat treatment), a lower temperature heat treatment (hereinafter referred to as low temperature heat treatment) can prevent the gettering effect from decreasing.

[0005]

EXAMPLES Examples of the present invention will be described below. A silicon single crystal is manufactured by the Czochralski method.
After performing each process of slicing, lapping, chamfering, and chemical polishing, high temperature heat treatment was performed under various conditions. Then, polishing was performed to obtain a mirror-finished wafer. N on this mirror wafer
After performing H cleaning (NH ₄ OH / H ₂ O ₂ / H ₂ O), the diameter of the silicon present on the silicon surface is 0.1 μm when irradiated with laser light
The above defects were counted by a particle counter. SP measured by the particle counter
It is called D (Surface Particle and Defect).

FIG. 1 shows the above measurement results. As is clear from the figure, the effect of reducing the SPD density is small when the heat treatment temperature is about 900 ° C. or lower, and the SPD density decreases when the heat treatment temperature is higher than 900 ° C. However, it can be seen that the higher the heat treatment temperature, the more the SPD density decreases at the heat treatment temperature of a short time. It is also understood that the SPD density sharply decreases when the heat treatment temperature exceeds about 1100 ° C.

Therefore, in order to obtain preferable high temperature heat treatment conditions, SPD≈1 (pieces / cm ² ) which is the lowest SPD density when the heat treatment temperature is about 900 ° C. is selected, and SPD <
FIG. 2 shows the result of determining the range of the high-temperature heat treatment condition of 1 (pieces / cm ² ). As shown in the figure, SPD <1 (pieces /
cm ² ), the heat treatment time t (Hr) required to obtain
Assuming that the heat treatment temperature is T (° C.), almost the following upper limit line a and lower limit line b, a: log (t) = 6.0-4.3 × 10 ⁻³ × T b: log (t) = 11.1 It has been found that it must be between −1.04 × 10 ⁻² × T.

In order to obtain more preferable high temperature heat treatment conditions, the minimum SP when the heat treatment temperature is about 1050 ° C.
Select SPD ≈ 0.3 (pieces / cm ² ) which is the D density,
FIG. 2 also shows the results of determining the range of high-temperature heat treatment conditions such that SPD <0.3 (pieces / cm ² ). As shown in the figure, the heat treatment time t required for SPD <0.3 (pieces / cm ² ) is approximately the following upper limit line c and lower limit line d, c: log (t) = 4.4− It was found that it must be between 3.2 × 10 ⁻³ × T d: log (t) = 17.5−1.57 × 10 ⁻² × T.

As described above, if the high temperature heat treatment condition between the upper limit line a and the lower limit line b is selected, or more preferably, the high temperature heat treatment condition between the upper limit line c and the lower limit line d is selected. , SPD density can be reduced, and thus the defect rate of semiconductor elements can be reduced. In this example, the test was performed in an oxygen atmosphere, but even if the test is performed in an atmosphere containing several% of oxygen in nitrogen and an atmosphere containing several% of oxygen in argon, almost the same SPD is obtained.
It was also found that a reduction in density was obtained. Further, in this example, after chemical polishing, high temperature heat treatment was performed under various conditions, and then polished to obtain a mirror-like wafer.
The chamfering, chemical polishing, polishing, high-temperature heat treatment under various conditions, and then re-polishing also gave a mirror-like wafer, and the same effect was obtained.

Next, it has been found that the high temperature heat treatment can reduce the fine defects in the active layer, but at the same time, the amount of oxygen precipitated in the silicon wafer after the device process may be reduced, resulting in intrinsic gettering. There is a risk that the yield of products will deteriorate due to lack of
Then, following the above high temperature heat treatment, a low temperature heat treatment of 700 ° C. × 2 Hr was performed to manufacture a MOS type memory IC device, and its hold time was measured. Figure 3 shows the hold time measurement results, where A is 1175 ° C x 0.5.
Wafers that have been subjected to a low temperature heat treatment of 700 ° C. × 2 Hr following a high temperature heat treatment of Hr, B is 1175 ° C. × 0.5 H
r indicates a wafer which was subjected to only the high temperature heat treatment and not the low temperature heat treatment, and C indicates a wafer which was not subjected to the heat treatment at all. As is clear from the figure, the hold time is remarkably improved by performing the high temperature heat treatment, but it is understood that the hold time is further improved by performing the low temperature heat treatment subsequent to the high temperature heat treatment. The conditions for the low temperature heat treatment are 600 to 800 ° C. and 0.5 to 10 hr.

[0011]

According to the present invention, preferable high temperature heat treatment conditions for removing minute defects on the surface of a silicon wafer can be obtained, and at the same time, a method for treating a silicon wafer which can prevent a reduction in gettering effect is obtained. .

[Brief description of drawings]

FIG. 1 is a diagram showing the relationship between SPD density and heat treatment conditions.

FIG. 2 is a diagram showing a range of preferable heat treatment conditions.

FIG. 3 is a diagram showing a measurement result of a hold time.

[Explanation of symbols]

a ... upper limit line b ... lower limit line c ... more preferable upper limit line d ... more preferable lower limit line

   ─────────────────────────────────────────────────── ─── Continued front page       (56) Reference JP-A-3-233936 (JP, A)                 JP-A-55-77170 (JP, A)                 JP-A-58-44724 (JP, A)                 JP-A-58-87833 (JP, A)                 JP-A-1-136343 (JP, A)

Claims (3)

(57) [Claims] 1. A silicon wafer formed by a pulling method has a log (t) = 11.1-1.04 × 10 ^-2.
× T, log (t) = 6.0−4.3 × 10 ⁻³ × T
, Log (t) = 4.9 × 10 ⁻³ × T-7.39.
, T = temperature of the melting point of silicon, within a range surrounded by four straight lines (however, the above four straight lines are not included and 800 ° C. or higher).
Excluding the range of 1250 ° C or lower and 10 hours or shorter . )
A heat treatment method for reducing the SPD density of a silicon wafer, which is characterized in that the heat treatment is performed under the conditions of. Here, T is the heat treatment temperature expressed in the unit of ° C, and t is the heat treatment time expressed in the unit of Hr. 2. Log (t) = 17.5-1.57 × 1
0 ⁻² × T, log (t) = 4.4−3.2 × 10
^-3 x T, log (t) = 4.9 x 10 ^-3 x T-
7.39, T = temperature of melting point of silicon, within a range surrounded by four straight lines (however, the above four straight lines are not included , and 80
0 ° C or more and 1250 ° C or less and 10 hours or less
Excluding . The heat treatment method for reducing the SPD density of a silicon wafer according to claim 1, wherein the heat treatment is performed under the condition of (1). Where T is the heat treatment temperature in ° C and t is Hr.
It is the heat treatment time expressed in units. 3. A heat treatment method for reducing the SPD density of a silicon wafer, which comprises performing heat treatment at a lower temperature subsequent to the heat treatment according to claim 1.