JP3387104B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP3387104B2 JP3387104B2 JP20934291A JP20934291A JP3387104B2 JP 3387104 B2 JP3387104 B2 JP 3387104B2 JP 20934291 A JP20934291 A JP 20934291A JP 20934291 A JP20934291 A JP 20934291A JP 3387104 B2 JP3387104 B2 JP 3387104B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- pattern
- island
- semiconductor device
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は、半導体装置に係り、特
に配線パタ−ン形状に関する。
【０００２】
【従来の技術】図３は従来における交差する二層の配線
パタ−ン形状の一例を示したものである。７は第一の配
線パタ−ンてあり、これと重なって８の第二の配線が交
差する。この例に依れば、第二の配線８が通過する第一
の配線７の段差部は９で示した部分であり第一の配線７
の一方向のみの段差である。この場合、第二の配線を形
成する時、第一の配線７の段差が特定の方向で第二の配
線がパタ−ン切れを発生してしまう。特に第二の配線材
料をスパッタ−に依り形成する場合、第一の配線の段差
方向に依り、良質な膜が形成される方向と、良質な膜が
形成されず後工程でのパタ−ニングの時に切れを発生さ
せる方向とがある事は良く知られた事である。
【０００３】
【発明が解決しようとする課題】上記の様に従来技術で
は、互いに交差する第一と第二の配線パタ−ンで、第一
の配線パタ−ンの段差が特定の方向の場合、第二の配線
が該段差部で切れてしまい、製品の歩留まりを著しく低
下させてしまっていた。本発明の目的は、第一と第二の
配線の交差部分がどの様な方向を向いていても、第二の
配線が、第一の配線の段差部で切れる事なく、良好な歩
留まりで製品を作れる様にする事にある。
【０００４】
【課題を解決するための手段】本発明の半導体装置は、
基板上に、互いに交差する第１の配線パターンと第２の
配線パターンを有する半導体装置において、前記第１の
配線パターンから延在する延在部を介して設けられた島
状パタンーンを有し、前記延在部を前記島状パターンの
幅より狭く形成し、前記島状パターンで形成される段差
の方向を、互いに直角な四方向あるいは３６０度の方向
に存在させてなり、前記第２の配線パターンは、前記島
状パターン及び前記延在部を覆って前記第１の配線パタ
ーンに交差することを特徴とする。
【０００５】
【作用】従来第二の配線が横切る領域で第一の配線パタ
−ン段差は一方向のみであったが、島状パターンで形成
される段差の方向を互いに直角な四方向あるいは３６０
度の方向に存在させることにより、この段差の内少なく
とも一方向の段差において、第二の配線材料が良好な膜
質で形成される様になり、パタ−ニング時に、第一の配
線の段差部において、第二の配線が完全に切れてしまう
事を防止できる。
【０００６】また、例えばスパッタ−の様に段差方向に
依り膜質が異なって形成される手段で第二の配線材料を
形成しても、その配線は第一の配線段差に於いて少なく
とも一方向の段差部ではパタ−ンが切れる事なく、第二
の配線は全体として切れを発生しない。
【０００７】
【実施例】以下、本発明を図１及び図２に依り詳細に述
べる。
【０００８】図１は本発明の一実施例を示した平面図で
ある。１は第一の配線であり、２は第二の配線である。
第二の配線２は第一の配線１の段差部を通過している
が、その部分で第一の配線１より延在した島状のパタ−
ン３を設ける。この島状のパタ−ン３は長方形をしてお
り、従って図中に矢印で示したごとく、方向ａ、方向
ｂ、方向ｃ、方向ｄと４方向の段差が存在する事にな
り、この島状のパタ−ンに重なって第二の配線２が配置
される。これに依り、第二の配線２が通過する部分の第
一の配線１の段差の方向は四方向の存在が達成される。
従って第二の配線２は島状パターンの四方向の段差の少
なくともその内の一方向の段差に於いて、良好なステッ
プカバ−を有する事になり、パタ−ンが切れる事が防止
される。図１では本発明による島状のパタ−ン３は第二
の配線２に完全に被われているが、第二の配線２の範囲
外まで延在する事も可能である。
【０００９】図２は本発明の他の実施例を示した平面図
である。４が第一の配線、５が第二の配線である。第二
の配線５は第一の配線４の段差部を通過しており、その
部分で第一の配線４に円形の島状パタ−ンが延在してい
る。図１の実施例の場合、第一の配線１に設けた段差は
互いに直角な四方向であるので、これに対して４５度の
方向など他の方向のほうが第二の配線材料を形成する場
合もっとも膜質が良好となる場合も有る。従って図二の
様に第一の配線４に円形のパタ−ンを延在して設けれ
ば、段差の方向は３６０度のどの方向にも存在する事に
なり、より完全な切れ防止を達成できる。この円形パタ
−ンは真円のみならず楕円であっても効果は変わらず、
又図１の場合同様にこの島状のパタ−ンが第二の配線５
の範囲外に一部でる事も可能である。さらに又図１、図
２とも本体の第一の配線パタ−ンに島状パタ−ンを延在
した例であるが、本体の配線パタ−ン内に同様の形状の
領域をエッチング除去する方法で段差を形成してもその
効果は変わらない。
【００１０】
【発明の効果】本発明によれば、交差する二つの配線に
於て、上層の配線が切れる事なく、製品の歩留りを全く
低下させない。又、パターン設計段階に於いては、その
方向に制限が無くなる為、自由度は大幅に向上する。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a wiring pattern shape. 2. Description of the Related Art FIG. 3 shows an example of a conventional wiring pattern of two layers intersecting each other. Reference numeral 7 denotes a first wiring pattern, and the second wiring 8 intersects with the first wiring pattern. According to this example, the step portion of the first wiring 7 through which the second wiring 8 passes is a portion indicated by 9 and the first wiring 7
Is a step only in one direction. In this case, when forming the second wiring, the step of the first wiring 7 causes the pattern to be cut in the second wiring in a specific direction. In particular, when the second wiring material is formed by sputtering, the direction in which a high-quality film is formed depends on the step direction of the first wiring, and the patterning in a later process is not performed because a high-quality film is not formed. It is well known that sometimes there is a direction in which cuts occur. As described above, in the prior art, when the first and second wiring patterns intersect each other and the step of the first wiring pattern is in a specific direction, In addition, the second wiring is cut off at the step, and the yield of the product is significantly reduced. An object of the present invention is to provide a product with a good yield without the second wiring being cut at the step of the first wiring, no matter what direction the intersection of the first and second wirings faces. Is to be able to make [0004] The semiconductor device of the present invention comprises:
A semiconductor device having a first wiring pattern and a second wiring pattern crossing each other on a substrate, the semiconductor device having an island-shaped pattern provided via an extending portion extending from the first wiring pattern; The extending portion is formed to be narrower than the width of the island pattern, and the directions of the steps formed by the island pattern are present in four directions perpendicular to each other or in directions of 360 degrees. The pattern intersects the first wiring pattern so as to cover the island pattern and the extension. Conventionally, the first wiring pattern has only one step in the region where the second wiring crosses. However, the steps formed by the island pattern are oriented in four directions perpendicular to each other or 360 degrees.
By being present in the direction of the angle, the second wiring material is formed with good film quality in at least one of the steps, and at the time of patterning, at the step portion of the first wiring. In addition, it is possible to prevent the second wiring from being completely cut. Further, even if the second wiring material is formed by means such that the film quality is formed differently depending on the step direction such as sputtering, the wiring is formed in at least one direction at the first wiring step. At the step portion, the pattern is not cut, and the second wiring does not cut as a whole. The present invention will be described below in detail with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing an embodiment of the present invention. 1 is a first wiring, and 2 is a second wiring.
The second wiring 2 passes through the step of the first wiring 1, and an island-shaped pattern extending from the first wiring 1 at that portion.
3 is provided. This island-shaped pattern 3 has a rectangular shape, and therefore, as shown by the arrows in the figure, there are steps in four directions a, b, c, and d. The second wiring 2 is arranged so as to overlap the pattern. Thereby, the direction of the step of the first wiring 1 in the portion through which the second wiring 2 passes can be achieved in four directions.
Accordingly, the second wiring 2 has a good step cover at least in one of the four steps of the island pattern, and the pattern is prevented from being cut. In FIG. 1, the island-shaped pattern 3 according to the present invention is completely covered by the second wiring 2, but can extend outside the range of the second wiring 2. FIG. 2 is a plan view showing another embodiment of the present invention. 4 is a first wiring and 5 is a second wiring. The second wiring 5 passes through the step of the first wiring 4, and a circular island pattern extends on the first wiring 4 at that portion. In the case of the embodiment shown in FIG. 1, the steps provided in the first wiring 1 are in four directions perpendicular to each other, so that the second wiring material is formed in another direction such as a direction of 45 degrees. In some cases, the film quality is good. Therefore, if a circular pattern is provided to extend on the first wiring 4 as shown in FIG. 2, the direction of the step exists in any direction of 360 degrees, and more complete prevention of disconnection is achieved. it can. This circular pattern does not change its effect even if it is not only a perfect circle but also an ellipse.
In the same manner as in the case of FIG.
It is also possible to be partially outside the range. Further, FIGS. 1 and 2 both show an example in which an island-like pattern is extended on the first wiring pattern of the main body. Even if a step is formed, the effect does not change. According to the present invention, in two intersecting wirings, the wiring in the upper layer is not cut off, and the yield of products is not reduced at all. In the pattern design stage, the direction is not limited, so that the degree of freedom is greatly improved.
【図面の簡単な説明】
【図１】本発明の一実施例を示す平面図である。
【図２】本発明の他の実施例を示す平面図である。
【図３】従来の２つの配線の交差部の一例を示す平面図
である。
【符号の説明】
１，４，７ 第一の配線
２，５，８ 第二の配線
３，６ 本発明に依る第一の配線の延在した島状
パターン
９ 従来に於ける第一の配線の段差部BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing one embodiment of the present invention. FIG. 2 is a plan view showing another embodiment of the present invention. FIG. 3 is a plan view showing an example of a conventional intersection of two wirings. DESCRIPTION OF SYMBOLS 1,4,7 First wiring 2,5,8 Second wiring 3,6 Island pattern 9 of first wiring extending according to the present invention 9 First wiring in the prior art Step
Claims (1)
ターンと第２の配線パターンを有する半導体装置におい
て、 前記第１の配線パターンから延在する延在部を介して設
けられた島状パタンーンを有し、前記延在部を前記島状
パターンの幅より狭く形成し、前記島状パターンで形成
される段差の方向を、互いに直角な四方向あるいは３６
０度の方向に存在させてなり、 前記第２の配線パターンは、前記島状パターン及び前記
延在部を覆って前記第１の配線パターンに交差すること
を特徴とする半導体装置。(57) A semiconductor device having a first wiring pattern and a second wiring pattern crossing each other on a substrate, wherein the first wiring pattern extends from the first wiring pattern. The extended portion is formed to be narrower than the width of the island-shaped pattern, and the directions of the steps formed by the island-shaped pattern are four directions perpendicular to each other or 36 directions.
The semiconductor device according to claim 1, wherein the second wiring pattern intersects the first wiring pattern so as to cover the island pattern and the extending portion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20934291A JP3387104B2 (en) | 1991-08-21 | 1991-08-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20934291A JP3387104B2 (en) | 1991-08-21 | 1991-08-21 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0547755A JPH0547755A (en) | 1993-02-26 |
| JP3387104B2 true JP3387104B2 (en) | 2003-03-17 |
Family
ID=16571364
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20934291A Expired - Fee Related JP3387104B2 (en) | 1991-08-21 | 1991-08-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3387104B2 (en) |
-
1991
- 1991-08-21 JP JP20934291A patent/JP3387104B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0547755A (en) | 1993-02-26 |
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