JP3389124B2 - Semiconductor storage device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a write operation auxiliary circuit arranged in a dummy cell region.

[0002]

2. Description of the Related Art In the current diffusion technology used for manufacturing a semiconductor memory device, the mask pattern shape of the memory cell region is such that the outer peripheral region of the memory cell region is less dense than the inner region of the memory cell region. Becomes This is because the exposure conditions and etching conditions are different from those in the memory cell internal region due to the difference in the mask pattern density between the memory cell region and the peripheral circuit region. Specifically, the shape of the gate and the field of the memory cells in the outer peripheral region of the memory cell array is changed, and the influence thereof reduces the performance of the cell transistor and deteriorates the characteristics.

Therefore, as shown in FIGS. 6 (A) and 6 (B), a cell having no memory function (hereinafter referred to as “memory function”) is provided between the memory cell region 50 and the peripheral circuit region 51 or between the adjacent memory cell regions 50. , A dummy cell region 52 having dummy cells) is arranged to prevent a difference in density between the inside and the outside of the memory cell region 50 from occurring. A semiconductor memory device including a dummy cell is disclosed in, for example, Japanese Patent Laid-Open No. 10-269790.

FIG. 7 is a circuit diagram schematically showing a memory cell area and a dummy cell area. As shown in FIG. 7, the memory cell 53 in the memory cell region 50 is formed by the digit line 5
The dummy cells 54 in the dummy cell region 52 are arranged at the intersections of the word lines 57 and 56 and the word lines 57 orthogonal thereto, and the dummy cells 54 at the intersections of the digit lines 55 and 56 and the dummy line 58 orthogonal thereto. In FIG. 7, reference numeral 59 is a write buffer.

FIGS. 8A and 8B are circuit diagrams showing a circuit configuration in a memory cell and a circuit configuration in a dummy cell, respectively. As shown in FIG. 8A, the memory cell 53
Is a flip-flop circuit 60 and a transfer transistor 6
1 and 62. Transfer transistors 61 and 62
Is connected between the nodes 63 and 64 holding two complementary storage data of the flip-flop circuit and the digit lines 55 and 56, and the word line 57 is connected to the gate thereof. The flip-flop circuit 60 cross-couples two inverter circuits including high resistance load elements 65 and 66 and driving transistors 67 and 68 (one input is supplied to the other output). The high resistance load elements 65 and 66 have one ends connected to the power supply voltage wiring Vcc and the other ends connected to the drains of the driving transistors 67 and 68. The sources of the driving transistors 67 and 68 are grounded (or connected to the reference voltage wiring Vss (not shown)). Transfer transistor 6
1, 62 and the driving transistors 67 and 68 are composed of n-channel MOSFETs.

As shown in FIG. 8B, the dummy cell 54
In, the gates of the transfer transistors 61 and 62 are grounded via the dummy line 58.

[0007]

In the prior art, it is necessary to insert a large number of dummy cells in order to completely suppress the deterioration of the characteristics described above, which leads to an increase in chip size. Therefore, it is necessary to reduce the dummy cell area and effectively use the dummy cell area.

In addition, with the recent increase in capacity, the number of memory cells connected to one digit line is also increasing, and the length of the digit line is inevitably extended. This leads to an increase in the load on the digit line, and as a result, it takes more time to discharge and precharge the digit line, which hinders the speedup. In particular, it takes time to discharge the digit line during the write operation and to precharge the digit line after the write operation, which easily affects the speedup of the product.

At the same time, the influence of the far-end difference from the buffer is more likely to appear due to the extension of the digit line, and variations easily occur even in cells on the same digit. The main cause is that the discharge time and the precharge time of the digit line are different between the cell far from the buffer and the cell close to the buffer. As a countermeasure against this, it is conceivable to arrange a write buffer and a circuit that performs the same operation also inside the digit line to reduce the difference between the near and far ends. However, for the same reason as the necessity of the dummy cell area described above, when such a peripheral circuit is arranged in the middle of the digit line, the contact point between the memory cell area and the peripheral circuit area expands, and the necessary dummy cell area also increases accordingly. This leads to an increase in chip size. Therefore, in the conventional circuit, it has been avoided to arrange the peripheral circuit in the middle of the digit line as much as possible.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device capable of improving the characteristics without increasing the chip size.

[0011]

A first semiconductor memory device of the present invention has a cell-shaped write operation auxiliary circuit arranged between a memory cell region and a peripheral circuit region, and the write operation is performed. The auxiliary circuit responds to the start and end operations of writing,
It is characterized in that the digit line is discharged and precharged.

A second semiconductor memory device of the present invention has a cell-shaped write operation auxiliary circuit arranged between a memory cell region and a peripheral circuit region and between adjacent memory cell regions. The write operation auxiliary circuit is characterized in that the digit line is discharged and precharged in response to the write start and end operations.

The write operation auxiliary circuit performs the discharge operation of the digit line at the start of writing and the precharge operation of the digit line at the end of writing, and the discharge operation of the digit line and the digit line. A second circuit for switching the precharge operation may be included.

The first circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a load resistor, a power supply voltage section, and a first transistor.
Input line and a second input line, the first transistor is connected to one of the adjacent digit lines, is connected to the first input line, and is connected to the load resistor and the third input line. A second transistor connected to the fourth transistor via a first contact with the transistor, the second transistor connected to the other adjacent digit line, and the first input line; It is connected to the third transistor via a second contact between the load resistor and the fourth transistor, one end of the load resistor is connected to the power supply voltage section, and the third and fourth transistors are connected. The transistor is connected to the second circuit via a third contact and the second input line, and the second input signal is input to the second circuit at the start of writing, whereby the second circuit is connected. The potential of the contact 3 is set to the ground level, and the first By inputting the first input signal to the force lines, the first and second transistors to ON state, ON one of said third and fourth transistors
State, the other is turned off, the digit line is discharged, and at the end of writing, the second input signal is input to the second circuit to set the potential of the third contact to a predetermined power supply voltage level. And by inputting a first input signal to the first input line, the first and second transistors are turned on, one of the third and fourth transistors is turned on, and the other is turned off. In this state, the digit line is precharged.

The second circuit is an inverter circuit composed of a fifth transistor connected to the power supply voltage section side and a sixth transistor connected to the ground side, and has a second input signal at the start of writing. Is input, the fifth
Is turned off, the sixth transistor is turned on, and the second input signal is input at the end of writing, whereby the fifth transistor is turned on.
The sixth transistor is turned off and the sixth transistor is turned off.

[0016]

[0017]

[0018]

According to the present invention, by arranging the write operation assisting circuit in the conventional dummy cell region, the write operation assisting circuit plays the role of the conventional dummy cell region and the discharge operation and the precharge operation of the digit line. It will also serve as an assistant.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The same members as those in the conventional technique are designated by the same reference numerals.

1A and 1B are explanatory views schematically showing the structure of the semiconductor memory device of the present invention. As shown in FIG. 1, the semiconductor memory device of the present invention is a conventional example (FIG. 6).
The write operation auxiliary circuit region 1 is arranged in the dummy cell region 52 (on the digit line). The write operation auxiliary circuit area 1 includes a peripheral circuit area 51 and a memory cell area 50.
Between the peripheral circuit region 51 and the memory cell region 50 and between the adjacent memory cell regions 50 (see FIG. 1B). See) and.

FIG. 2 is a circuit diagram schematically showing the memory cell area and the write operation auxiliary circuit area. As shown in FIG. 2, the memory cell region 50 includes a plurality of memory cells 53, and the write operation auxiliary circuit region 1 includes a plurality of write operation auxiliary circuits 2. Each write operation auxiliary circuit 2 is arranged at the intersection of the digit lines 55 and 56 and the first input line 3 orthogonal thereto. In addition, the write operation auxiliary circuit 2 performs the discharge operation of the digit line at the start of writing and the precharge operation of the digit line at the end of writing, and the cell-shaped first circuit 4 and the discharge operation of the digit line. A second circuit 5 for switching the precharge operation of the digit line.

FIG. 3 is a circuit diagram showing a circuit configuration in the write operation auxiliary circuit. As shown in FIG. 3, the first circuit 4 is
The first transistor 6, the second transistor 7, the third transistor 8, the fourth transistor 9, the high load resistance elements 10 and 11, the power supply voltage wiring Vcc, and the first transistor 6.
Input line 3 and a second input line 12.

The first transistor 6 is connected to the adjacent one digit line 55, the gate thereof is connected to the first input line 3, and the first transistor 6 between the high load resistance element 10 and the third transistor 8 is connected. It is connected to the gate of the fourth transistor 9 via the first contact 13.

The second transistor 7 is connected to the other adjacent digit line 56, its gate is connected to the first input line 3, and the second transistor 7 between the high load resistance element 11 and the fourth transistor 9 is connected. It is connected to the gate of the third transistor 8 via the second contact 14.

One ends of the high load resistance elements 10 and 11 are connected to the power supply voltage wiring Vcc.

The drain of the third transistor 8 is the first
It is connected to the other end of the high load resistance element 10 via the contact 13. The drain of the fourth transistor 9 is connected to the other end of the high load resistance element 11 via the second contact 14.

The sources of the third transistor 8 and the fourth transistor 9 are the third contact 15 and the second input line 12 respectively.
Is connected to the second circuit 5 via.

First to fourth transistors 6, 7, 8, 9
Is composed of an n-channel MOSFET. The first circuit 4 is controlled by a first input signal a transmitted via the first input line 3 and controlled by a decoder or the like.
The first input signal a is generated, for example, by selection by the row decoder circuit and the column decoder circuit at the time of address selection.

The second circuit 5 is a CMOS inverter circuit provided on the second input line 12, and switches between the digit line discharge operation and the digit line precharge operation. The second circuit 5 is connected to the power supply voltage wiring Vcc side, is connected to the fifth transistor 16 formed of a p-channel MOSFET, and is connected to the ground side, and is an n-channel MOS.
And a sixth transistor 17 formed of a FET.

The “H” level input signal b is applied to the second circuit 5
Is input to the fifth transistor 16, the sixth transistor 17 is turned on, and the potential of the third contact 15 becomes GND level.

The “L” level input signal b is applied to the second circuit 5
The fifth transistor 16 is turned on,
The sixth transistor 17 is turned off, and the potential of the third contact 15 changes from the GND level to the Vcc level.
In this way, the second circuit 5 changes the level of the potential of the third contact 15 by the second input signal b. Since the second input signal b needs to be switched between reading and writing, it is generated (takes a logic) using a normal write operation selection signal (WE signal).

The second circuit 5 is preferably arranged as a peripheral circuit outside the memory cell region 50 in consideration of an increase in the size of the memory cell region 50, ease of layout, etc. . In addition, one second circuit 5 is not necessarily required for one first circuit 4. For example, when the same selection form as the word line 57 is adopted, the second circuit 5 is provided in the array section. It is not necessary to dispose the circuit 5, and for most of the first circuit 4, only the output wiring from the second circuit 5 is provided and a new dummy cell region is not required.

Next, the operation of the semiconductor memory device of the present invention will be described. FIG. 4 is a timing chart of signals of respective parts for explaining the operation of the semiconductor memory device of the present invention. In FIG. 4, A
DD is an address selection signal, which is a signal for selecting a specific memory cell. WE is a write operation signal, OE is a data output activation signal, DIN is a data input signal, DO
UT is a data output signal, input a is a first input signal, and input b is a second input signal.

First, the discharge operation of the digit line at the start of writing will be described.

At the start of writing, the operation of the write buffer starts discharging the potential of digit line 55 or digit line 56 from the Vcc level to the GND level. The input signal b is set to take the logic of the write operation signal (WE signal) and to be inputted with the "H" level signal during the write operation.

The “H” level input signal b is applied to the second circuit 5
Input to the fifth transistor 16
The FF and the sixth transistor 17 are turned on, and the potential of the third contact 15 is fixed to the GND level with the start of the writing operation.

The digit line 55 is operated by the operation of the write buffer.
When the potential difference is applied to the digit line 56, the first input signal a is input to the write operation auxiliary circuit 2. However, the first
As for the input timing of the input signal a, it is necessary to give a delay time T1 and input after a sufficient potential difference occurs in the digit line 55 and the digit line 56, as shown in FIG. In FIG. 4, T2 is a delay time at the time of reading.

Here, the operation of discharging the digit line 56 will be described. Upon receiving the signal from the first input signal a, the first transistor 6 and the second transistor 7 are turned on. This allows the digit line 5
The potentials of 5 and the digit line 56 become the gate input potentials of the fourth transistor 9 and the third transistor 8, respectively. Due to the potential difference due to the write buffer operation, the gate input potential of the fourth transistor 9 becomes the “H” level and the transistor is turned on. As a result, the potential of the digit line 56 is changed to the second potential.
The discharge operation is started to the GND level through the transistor 7, the fourth transistor 9, and the sixth transistor 17.

Further, the gate input potential of the third transistor 8 becomes "L" level and it is in the OFF state. As a result, the potential of the digit line 55 maintains the Vcc level. Therefore, the write operation auxiliary circuit 2 in the semiconductor memory device of the present invention assists the write operation (digit line discharge operation).

Next, the precharge operation of the digit line after the completion of the write operation will be described. The second input signal b is controlled by using the write operation signal (WE signal), and when the write operation state ends, the input signal b is changed from the “H” level input to the “L” level input. Switch to. In response to this input, the fifth transistor 16 is turned on, the sixth transistor 17 is turned off, and the third contact 15
The potential of is switched from the GND level to the Vcc level.

Then, as in the write operation, the Vcc level signal from the decoder is input as the first input signal a. This signal turns on the first transistor 6 and the second transistor 7. The third transistor 8 is turned off by the potential of the digit line 56, and the fourth transistor 9 is turned on by the potential of the digit line 55 having a high potential. As a result, the third contact 15 becomes Vc
Since it is at the c level, the precharge operation to the digit line 56 whose potential is at the GND level is started.

According to the semiconductor memory device of the present invention, since the write operation auxiliary circuit 2 has a cell shape, the write operation auxiliary circuit 2 can be arranged at an arbitrary position of the digit line with a minimum size, and when a normal circuit is arranged. If so, the necessary dummy cell region is not necessary. As a result, the chip size can be reduced.

By disposing the write operation assisting circuit 2 in the conventional dummy cell region, the write operation assisting circuit 2 is provided.
In addition to the role of the conventional dummy cell region, it simultaneously serves as a role of assisting the discharge operation and precharge operation of the digit line. As a result, the characteristics can be improved without increasing the chip size.

Further, since the conventional write buffer is usually arranged on one side of the digit line, the characteristic is deteriorated due to the difference between the far and near ends from the buffer, but it is arranged around the memory cell region 50. In the semiconductor memory device of the present invention which utilizes the existing dummy cell region, since it can be arranged on both sides of the digit line, it is possible to improve the characteristics depending on the difference between the near and far ends from the buffer.

Further, in the conventional circuit, in order to precharge and discharge the digit line at high speed, the write buffer has been constructed by using a large transistor having a considerably high capacity. On the other hand, in the present invention,
By installing the write operation auxiliary circuit 2, it is possible to shorten the precharge and discharge time of the digit line.
The large-scale transistor-size write buffer conventionally used is not necessary, and the chip size can be reduced.

Next, a semiconductor memory device according to another embodiment of the present invention will be described. FIG. 5 is a circuit diagram showing a write operation auxiliary circuit of a semiconductor memory device according to another embodiment of the present invention.

As shown in FIG. 5, the write operation auxiliary circuit 2 of this semiconductor memory device includes a first transistor 6 and a second transistor 6.
The transistor 7, the third transistor 8, the fourth transistor 9, and the first input line 3. The first transistor 6 is connected to the adjacent one digit line 55, and its gate is connected to the first input line 3,
Is connected to the third transistor 8 and the fourth transistor 9 via the contact 13.

The second transistor 7 is connected to the other adjacent digit line 56, the gate thereof is connected to the first input line 3, and the third transistor 8 and the fourth transistor 8 are connected via the second contact 14. Connected to the transistor 9.

The third transistor 8 and the fourth transistor 9 are grounded via the third contact 15.

According to the semiconductor memory device of this aspect, by inputting the first input signal a to the first input line 3 at the start of writing, the first transistor 6 and the second transistor 7 are turned on. Then, one of the third transistor 8 and the fourth transistor 9 is turned on and the other is turned off to discharge one of the digit lines 55 and 56. In the above-described embodiment, the second circuit 5 that performs switching for performing the discharge operation and the precharge operation of the digit line is provided, but in this embodiment,
The second circuit 5, the power supply voltage line Vcc, and the high load resistance elements 10 and 11 are not required, and fixing the third contact 15 to the GND level assists only the discharge operation of the digit line. According to the semiconductor memory device of this aspect, the second circuit 5 that performs switching for performing the discharge operation and the precharge operation of the digit line is performed.
Since it is not necessary, the chip size can be reduced, and the entire circuit becomes closer to the cell shape, which facilitates the layout. Regarding the improvement of the characteristics, there is no improvement in the characteristics of the precharge capacity, but the discharge capacity has the same capacity, and due to the shortening of the time required for discharging the digit line, the subsequent precharge of the digit line is possible. I have time to spare. Therefore, it is expected to improve the characteristics according to the above-described embodiment.

The present invention is not limited to the above-mentioned embodiments, and various modifications can be made within the scope of technical matters described in the claims. For example, the third
It is also possible to fix the contact 15 of the power supply voltage Vcc to assist the precharge operation. Further, the semiconductor memory device of the present invention may be used for a precharge operation at the time of reading.

[0053]

According to the semiconductor memory device of the present invention, since the write operation auxiliary circuit has a cell shape, the write operation auxiliary circuit can be arranged at an arbitrary position of the digit line with a minimum size, and when a normal circuit is arranged. In that case, the required dummy cell region is not necessary. As a result, the chip size can be reduced.

By disposing the write operation auxiliary circuit in the conventional dummy cell region, the write operation auxiliary circuit plays the role of the conventional dummy cell region and also the role of assisting the discharge operation and the precharge operation of the digit line. It will also serve as the same. As a result, the characteristics can be improved without increasing the chip size.

In addition, since the conventional write buffer is usually arranged on one side of the digit line, the characteristic is deteriorated due to the difference between the far and near ends from the buffer, but it is arranged around the memory cell area. In the semiconductor memory device of the present invention which uses the dummy cell region, since it can be arranged on both sides of the digit line, it is possible to improve the characteristics depending on the difference between the near and far ends from the buffer.

Further, in the conventional circuit, in order to precharge and discharge the digit line at high speed, the write buffer has been constructed by using a large transistor having a considerably high capacity. On the other hand, in the present invention,
By installing the write operation auxiliary circuit, the precharge and discharge time of the digit line can be shortened, so that the large-scale write buffer of the transistor size used conventionally is not necessary, and the chip size can be reduced. .

[Brief description of drawings]

1A and 1B are explanatory views schematically showing a configuration of a semiconductor memory device of the present invention.

FIG. 2 is a circuit diagram schematically showing a memory cell region and a write operation auxiliary circuit region.

FIG. 3 is a circuit diagram showing a circuit configuration in a write operation auxiliary circuit.

FIG. 4 is a timing chart of signals of respective parts for explaining the operation of the semiconductor memory device of the present invention.

FIG. 5 is a circuit diagram showing a write operation auxiliary circuit of a semiconductor memory device according to another embodiment of the present invention.

6A and 6B are explanatory views schematically showing a configuration of a conventional semiconductor memory device.

FIG. 7 is a circuit diagram schematically showing a memory cell region and a dummy cell region.

8A and 8B are circuit diagrams showing a circuit configuration in a memory cell and a circuit configuration in a dummy cell, respectively.

[Explanation of symbols]

1: Write operation auxiliary circuit area 2: Write operation auxiliary circuit 3: First input line 4: First circuit 5: Second circuit 6: First transistor 7: Second transistor 8: Third transistor 9: Fourth transistor 10: High load resistance element 11: High load resistance element 12: second input line 13: First contact 14: Second contact 15: Third contact 16: Fifth transistor 17: sixth transistor 50: Memory cell area 51: Peripheral circuit area 53: Memory cell 55: Digit line 56: Digit line Vcc: Power supply voltage wiring

─────────────────────────────────────────────────── --- Continuation of the front page (56) Reference JP-A-7-262784 (JP, A) JP-A-3-29194 (JP, A) JP-A-5-274886 (JP, A) JP-A-10- 125805 (JP, A) JP 7-147091 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 11/40-11/4197

Claims (6)

(57) [Claims] 1. A write operation auxiliary circuit including a cell-shaped circuit connected to a digit line between a memory cell area and a peripheral circuit area, wherein the write operation auxiliary circuit is provided for starting writing and A semiconductor memory device characterized by performing switching between a digit line discharge operation and a precharge operation in response to a termination operation. 2. A write operation auxiliary circuit including a cell-shaped circuit connected to a digit line between a memory cell region and a peripheral circuit region and a digit line between adjacent memory cell regions, respectively. A semiconductor memory device characterized in that a write operation auxiliary circuit switches between a digit line discharge operation and a precharge operation in response to a write start and write end operation. 3. A cell-shaped first circuit that performs a digit line discharge operation at the start of writing and a digit line precharge operation at the end of writing, and a digit line discharge circuit. 3. A semiconductor memory device according to claim 1, further comprising a second circuit for switching between an operation and a digit line precharge operation. 4. The first circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a load resistor, a power supply voltage section, and a first transistor.
Input line and a second input line, the first transistor is connected to one adjacent digit line, is connected to the first input line, and is connected to the load resistor and the third input line. A second contact connected to the fourth transistor via a first contact with the transistor, the second transistor connected to the other adjacent digit line, and connected to the first input line; It is connected to the third transistor via a second contact between the load resistor and the fourth transistor, one end of the load resistor is connected to the power supply voltage section, and the third and fourth transistors are connected. The transistor is connected to the second circuit through a third contact and the second input line, and the second input signal is input to the second circuit at the start of writing, whereby the second circuit is connected. The potential of the third contact is set to the ground level, By inputting the first input signal to the input line of, the first and second transistors are turned on, one of the third and fourth transistors is turned on, and the other is turned off, so that the digit The line is discharged, and at the end of writing, the second input signal is input to the second circuit to bring the potential of the third contact to a predetermined power supply voltage level and the first input line to the first input line. By inputting the input signal of 1, the first and second transistors are turned on, one of the third and fourth transistors is turned on, and the other is turned off to precharge the digit line. The semiconductor memory device according to claim 3, wherein 5. The second circuit is an inverter circuit composed of a fifth transistor connected to the power supply voltage section side and a sixth transistor connected to the ground side. By inputting the input signal,
The fifth transistor is turned off, and the sixth transistor is turned off.
Transistor turns on and the second input signal is input at the end of writing,
The semiconductor memory device according to claim 3, wherein the fifth transistor is turned on and the sixth transistor is turned off. 6. A write operation auxiliary circuit including a cell-shaped circuit connected to a digit line between a memory cell area and a peripheral circuit area, wherein the write operation auxiliary circuit starts or starts writing. A semiconductor memory device characterized by performing switching between a digit line discharge operation and a precharge operation in response to a termination operation.