JP6236846B2 - Semiconductor memory device and reading method thereof - Google Patents

Description

  The present invention relates to a semiconductor memory device and a reading method thereof.

  With the demand for larger capacity and lower power consumption of semiconductor memory devices, miniaturization of elements is progressing. However, with the recent progress of scaling, the variation in transistor characteristics increases and the operation margin of the SRAM decreases, making it difficult to read stably and at high speed.

  For example, in single-ended reading of SRAM, reading is performed by extracting the charge of the bit line by the transistor of the selected memory cell. However, when the characteristics of the transistor become large, it is necessary to widen the margin for reading, and high-speed reading is difficult. become.

Japanese Patent Laid-Open No. 06-013581 JP 2010-129144 A International Publication No. 2008/114317 Pamphlet

  An object of the present invention is to provide a structure of a semiconductor memory device and a method for reading the semiconductor memory device, which can perform single-ended reading of an SRAM at high speed and stably.

  According to one aspect of the embodiment, the first bit line, the second bit line paired with the first bit line, and the first bit line and the second bit line are connected. A memory cell, a first N-type transistor having a drain electrode connected to the first bit line and a gate electrode connected to the second bit line, and a drain connected to a source electrode of the first N-type transistor A second N-type transistor having an electrode connected and a gate electrode connected to a high-potential-side power supply node; and a source electrode of the second N-type transistor; There is provided a semiconductor memory device having a control circuit for applying a low-potential-side power supply voltage to the source electrode of two N-type transistors.

  According to another aspect of the embodiment, the first bit line, the second bit line paired with the first bit line, the first bit line, and the second bit line A connected memory cell; a first N-type transistor having a drain electrode connected to the first bit line; and a gate electrode connected to the second bit line; and a source of the first N-type transistor A read method for a semiconductor memory device, comprising: a second N-type transistor having a drain electrode connected to an electrode and a gate electrode connected to a high-potential side power supply node, wherein the memory cell includes a first bit line side A semiconductor that applies a low-potential-side power supply voltage to the source electrode of the second N-type transistor in accordance with a column selection signal for reading when information stored in the storage node is read out to the first bit line Method of reading 憶 device is provided.

  According to the disclosed semiconductor memory device and the reading method thereof, the reading operation of the semiconductor memory device can be performed at high speed and stably.

FIG. 1 is a circuit diagram showing a structure of a semiconductor memory device according to an embodiment. FIG. 2 is a circuit diagram showing a structure of a memory cell of the semiconductor memory device according to the embodiment. FIG. 3 is a circuit diagram showing a structure of a dummy memory cell of the semiconductor memory device according to the embodiment. FIG. 4 is a circuit diagram illustrating a method for driving a semiconductor memory device according to an embodiment. FIG. 5 is a timing chart (part 1) illustrating the reading method of the semiconductor memory device according to the embodiment. FIG. 6 is a timing chart (part 2) illustrating the reading method of the semiconductor memory device according to the embodiment. FIG. 7 is a timing chart showing the effect of the reading method of the semiconductor memory device according to the embodiment. FIG. 8 is a circuit diagram illustrating a circuit model used in a simulation for verifying the read operation of the semiconductor memory device according to the embodiment. FIG. 9 is a timing chart (part 1) showing the simulation result of the read operation of the semiconductor memory device. FIG. 10 is a timing chart (part 2) showing the simulation result of the read operation of the semiconductor memory device. FIG. 11 is a graph showing a simulation result of the read operation of the semiconductor memory device.

  A semiconductor memory device and a reading method thereof according to an embodiment will be described with reference to FIGS.

  FIG. 1 is a circuit diagram showing the structure of the semiconductor memory device according to the present embodiment. FIG. 2 is a circuit diagram showing the structure of the memory cell of the semiconductor memory device according to the present embodiment. FIG. 3 is a circuit diagram showing the structure of the dummy memory cell of the semiconductor memory device according to the present embodiment. FIG. 4 is a circuit diagram illustrating the method for driving the semiconductor memory device according to the present embodiment. 5 and 6 are timing charts showing the read method of the semiconductor memory device according to the present embodiment. FIG. 7 is a timing chart showing the effect of the reading method of the semiconductor memory device according to the present embodiment. FIG. 8 is a circuit diagram showing a circuit model used for the simulation for verifying the read operation of the semiconductor memory device according to the present embodiment. 9 and 10 are timing charts showing simulation results of the read operation of the semiconductor memory device. FIG. 11 is a graph showing a simulation result of the read operation of the semiconductor memory device.

  First, the structure of the semiconductor memory device according to the present embodiment will be explained with reference to FIGS.

  As shown in FIG. 1, the semiconductor memory device according to the present embodiment has memory cell array blocks 10A and 10B arranged adjacent to each other in the column direction (vertical direction in the drawing). In the memory cell array blocks 10A and 10B, a plurality of memory cells MC arranged in a matrix in the column direction and the row direction (lateral direction in the drawing) are provided. Dummy memory cells DC are provided on the outer periphery of the memory cells MC arranged in a matrix.

Each of the memory cell array blocks 10A and 10B is provided with a plurality of word lines WL extending in the row direction and a plurality of bit lines BL extending in the column direction. In the memory cell array block 10A, for example, m word lines WL _{A0 to} WL _Am arranged adjacent to each other in the column direction and, for example, n sets of bit line pairs BL _A0 , / BL arranged adjacent to each other in the row direction. _{A0 to} BL _An and / BL _An are provided. The memory cell array block 10B includes, for example, m word lines WL _{B0 to} WL _Bm arranged adjacent to each other in the column direction, and, for example, n sets of bit line pairs BL _B0 , arranged adjacent to each other in the row direction. / BL _{B0 to} BL _Bn , / BL _Bn are provided.

  The memory cell MC is provided at each intersection of the word line WL and the bit line pair BL, / BL. Further, the dummy memory cells DC are respectively provided in the regions between the bit line pairs BL and / BL adjacent to the memory cells MC arranged in the column direction.

A row selection circuit 12 is connected to one end of the word lines WL _{A0 to} WL _Am and WL _{B0 to} WL _Bm . Each pair of bit lines _{BL A0, / BL A0 ~BL An} , / BL An and each bit line pair _{BL B0, / BL B0 ~BL Bn} , between the / _{BL Bn,} write / read circuit ₁₄ 0-14 _n are connected to each other. A write / read control circuit 16 is connected to the write / read circuits 14 _{0 to} 14 _n .

  The memory cell MC is, for example, a full CMOS SRAM cell as shown in FIG. Memory cell MC includes a P-type transistor PQ1 connected between high-potential-side power supply node VH and a node mc that is a storage node, and an N-type transistor connected between node mc and low-potential-side power supply node VL. NQ1. Further, a P-type transistor PQ2 connected between the high potential side power supply node VH and the node mcx which is a storage node, and an N type transistor NQ2 connected between the node mcx and the low potential side power supply node VL are provided. Have. The gate electrode of the P-type transistor PQ1 and the gate electrode of the N-type transistor NQ1 are connected to the node mcx. The gate electrode of the P-type transistor PQ2 and the gate electrode of the N-type transistor NQ2 are connected to the node mc. Node mc is connected to bit line BL via N-type transistor NQ3. Node mcx is connected to bit line / BL via N-type transistor NQ4. The gate electrodes of N-type transistors NQ3 and NQ4 are connected to word line WL.

  N-type transistor NQ1 and P-type transistor PQ1, N-type transistor NQ2 and P-type transistor PQ2 each constitute a CMOS inverter. The inputs and outputs of these CMOS inverters are cross-connected to form a flip-flop, and complementary data are held at nodes mc and mcx.

  The dummy memory cell DC is arranged around the memory cell array in order to improve the shape uniformity of the memory cell MC, and basically includes six transistors similar to the memory cell MC shown in FIG. The However, in the semiconductor memory device according to the present embodiment, a part of the connection is changed in order to use the dummy memory cell DC as an auxiliary element at the time of reading.

That is, as shown in FIG. 3, the gate electrodes of the P-type transistor PQ1 _D and the N-type transistor NQ1 _D are not only connected to the node dmcx but also connected to the high potential side power supply node VH. The bit line / BL, the drain electrode of the N-type transistor NQ4 _D not connected, are connected to the dummy word line DWL. Further, the node n1 which is a connection node of the N-type transistors NQ1 _D and NQ2 _D is connected to the write / read circuit 14 instead of the low potential side power supply node VL. A predetermined control signal is input from the write / read control circuit 16 to the source terminals of the N-type transistors NQ1 _D and NQ2 _D during the read operation. Note that the dummy word line DWL is a wiring corresponding to the word line WL of the memory cell MC, and is referred to as such in the present specification for convenience. However, the dummy word line DWL is independent in each dummy memory cell DC and is arranged in the row direction. The memory cells DC are not commonly connected.

  Next, the method for driving the semiconductor memory device according to the present embodiment will be explained with reference to FIGS.

Here, in the semiconductor memory device of FIG. 1, a case where writing and reading are performed on the memory cell MC connected to the word line WL _A0 and the bit line pair BL _A0 and / BL _A0 will be described as an example. The same applies when reading the memory cell MC.

  FIG. 4 is a circuit diagram showing an example of a main part of the memory cell MC to be written / read, the dummy memory cell DC connected thereto, and the write / read circuit 14A.

A P-type transistor PQ3 is connected between the bit line _BLA0 and the high potential side power supply node VH. A P-type transistor PQ4 is connected between the bit line / BL _A0 and the high potential side power supply node VH. A P-type transistor PQ4 is connected between the bit line BL _A0 and the bit line / BL _A0 . The gate electrodes of the P-type transistors PQ3, PQ4, and PQ5 are connected to the output terminal of the NAND gate NAG1.

An N-type transistor NQ5 is connected to the bit line BL _A0 . An N-type transistor NQ6 is connected to the bit line / BL _A0 . The output terminal of the NOT gate NG3 is connected to the gate electrodes of the N-type transistors NQ5 and NQ6.

  The output terminals of the NOT gates NG1 and NG2 are connected to the input terminal of the NAND gate NAG1. The output terminal of the NOT gate NG1 is also connected to the node n1 of the dummy memory cell DC via the delay circuit 18. The output terminal of the NOT gate NG2 is also connected to the input terminal of the NOT gate NG3.

The bit line BL _A0 and the bit line BL _B0 are connected to the input terminal of the NAND gate NAG2. The output terminal of the NAND gate NAG2 is connected to the gate electrode of the N-type transistor NQ7 connected between the global bit line GBL and the low potential side power supply node. A P-type transistor PQ6 is connected between the global bit line GBL and the high potential side power supply node VH.

  Note that the circuit configuration of the write / read circuit 14 described above is not limited to that described in this embodiment.

  First, a method for writing data to the memory cell MC will be described.

When writing to the memory cell MC, the row selection circuit 12 sets the word line WL _A0 connected to the memory cell MC to be written to high level and the other word lines WL to low level. As a result, the select transistors NQ3 and NQ4 of the memory cell MC are turned on, the node mc of the memory cell MC to be written is connected to the bit line BL _A0 , and the node mcx is connected to the bit line / BL _A0 .

Further, from the write / read control circuit 16 to the write / read circuit 14 _A, the column selection signal colw of high level is outputted. As a result, a high level is applied to the gate electrodes of the N-type transistors NQ5 and NQ6 via the NOT gates NG2 and NG3, and the NOT gates NG2 and NG3 are turned on.

  In this state, by outputting complementary write data wd and wdx to the source terminals of the N-type transistors NQ5 and NQ6, desired complementary data can be written to the nodes mc and mcx of the memory cell MC.

  Next, a method for reading data from the memory cell MC will be described.

In the standby state (time T0), the word line WL _A0 is at the low level, and the select transistors NQ3 and NQ4 of the memory cell MC are in the off state.

Further, the read column selection signal colr and the write column selection signal colw are at the low level, and the output signal of the output signal of the NAND gate NAG1 is at the low level. As a result, the P-type transistors PQ3, PQ4, and PQ5 are in the on state, and the bit lines BL _A0 and / BL _A0 are at the high level. Similarly, the bit line BL _B0 is also at a high level, and the output signal of the NAND gate NAG2 is at a low level.

  Further, the output signal of the NOT gate NG3 is at a low level, and the N-type transistors NQ5 and NQ6 are in the off state.

  Further, a high level signal, which is the output of the NOT gate NG1, is applied to the node n1 of the dummy memory cell DC via the delay circuit 18. As a result, the nodes dmc and dmcx of the dummy memory cell DC are at a high level.

At the start of the read operation (time T1), a high level voltage is applied to the selected word line WL _A0 . As a result, the select transistors NQ3 and NQ4 of the memory cell MC are turned on.

  At the same time, the column selection signal colr for reading is raised from the low level to the high level. The column selection signal colw for writing remains at a low level. As a result, the output signal of the NAND gate NAG1 rises from the low level to the high level, the P-type transistors PQ3, PQ4, PQ5 are turned off, and the bit lines BL, / BL are disconnected from the high potential side power supply node.

When the node mc of the memory cell MC is at the low level and the node mcx is at the high level, the bit line BL _A0 is connected to the low potential side power supply node VL via the N-type transistors NQ3 and NQ1. As a result, the charge of the bit line BL _A0 is gradually extracted in the direction of the low potential side power supply node VL, and finally the bit line BL _A0 becomes low level.

When the bit line BL _A0 becomes low level, the output signal of the NAND gate NAG2 becomes high level, the N-type transistor NQ7 is turned on, and the global bit line GBL is connected to the low potential side power supply node VL via the N-type transistor NQ7. Connected. As a result, the global bit line GBL becomes low level.

On the other hand, when the node mc of the memory cell MC is at the high level and the node mcx is at the low level, charge transfer from the bit line BL _A0 does not occur, and the bit line BL _A0 is maintained at the high level. When the bit line BL _A0 is at the high level, the output signal of the NAND gate NAG2 remains at the low level, and the global bit line GBL is maintained at the high level.

  Therefore, information stored in the memory cell MC can be read by detecting the voltage level of the global bit line GBL.

  The read method described above is the same as the typical single-ended read method. However, in the read method of the semiconductor memory device according to the present embodiment, the dummy memory cell DC is further used to increase the read speed and reduce the variation. Reduction is possible.

  That is, in the semiconductor memory device according to the present embodiment, the output signal of the NOT gate NG1 is input to the node n1 of the dummy memory cell DC via the delay circuit 18 (control signal dcol). As a result, the potential (control signal dcol) of the node n1 of the dummy memory cell DC is changed from a high level after a predetermined time (time T2) defined by the delay circuit 18 from the rising edge of the column selection signal colr for reading. Fall to low level.

When the node mc of the memory cell MC is at the low level and the node mcx is at the high level (see FIG. 5), the bit line / BL _A0 is maintained at the high level, and the high level is applied to the dummy word line DWL _A0 . When the dummy word line DWL _A0 is at the high level, the bit line BL _A0 is connected to the node n1 at the low level via the N-type transistors NQ3 _D and NQ1 _D. As a result, the charge on the bit line BL _A0 is gradually extracted in the direction of the node n1 via the N-type transistors NQ3 _D and NQ1 _D.

That is, after the time T2, the charge of the bit line BL _A0 is extracted through the N-type transistors NQ3 and NQ1 of the memory cell MC and also extracted through the N-type transistors NQ3 _D and NQ1 _D of the dummy memory cell. . Thereby, the speed of extracting charges from the bit line BL _A0 can be increased.

On the other hand, if the node node mc of the memory cell MC is high level mcx is low (see FIG. 6), the control signal dcol is by falls to the low level, N-type transistors NQ1 _D is turned on, the bit lines BL _A current path is formed between _A0 and node n1. However, by giving the control signal dcol a delay time (first time) with respect to the column selection signal colr, the N-type transistor NQ1 _D has the bit line / BL _{A0 corresponding} to the time (time T1 to T2). The battery is turned on after discharging only for a while. When N-type transistor NQ1 _D is turned on (time T2), the voltage level of bit line / BL _A0 , that is, the voltage level of dummy word line DWL _A0 is also lowered to some extent, and the on-current of N-type transistor NQ3 _D Is also getting smaller. As a result, the extraction of charges from the bit line BL _A0 via the N-type transistors NQ3 _D and NQ1 _D is suppressed, and the bit line BL _A0 can be maintained at a substantially high level (between times T2 and T3). . That is, there is no adverse effect due to read assist using the dummy memory cell DC.

The delay time set in the delay circuit 18 configures the cell so that the extraction of charge from the bit line BL _A0 is effectively suppressed when the node mc of the memory cell MC is at the high level and the node mcx is at the low level. It is desirable to set appropriately according to the characteristics of the transistor to be performed. The delay time set in the delay circuit 18 is not particularly limited, but examples include the time required for the voltage of the bit line / BL _A0 to drop from VDD to 1 / 2VDD.

Thereafter, the word line WL _A0 and the column selection signal for reading colr are returned to the low level, and the read operation is completed (time T3). After a predetermined time defined by the delay circuit 18 from the falling edge of the column selection signal colr, the control signal dcol returns from the low level to the high level and enters a standby state (time T4).

When the charge of the bit line BL _A0 is _extracted only by the memory cell MC without using the dummy memory cell DC during the read operation as in a typical single-ended read method, the voltage change of the bit line BL _A0 is For example, as shown in FIG. In this case, the rate of extracting charges from the bit line BL _A is slow, and the time until the potential of the bit line BL _A0 reaches a low level is long. Further, the time until the potential of the bit line BL _A0 reaches the low level is greatly affected by the variation in transistor characteristics, and the variation also increases. The dotted line shown in the figure assumes a variation range of transistor characteristics.

In contrast, in the reading method of a semiconductor memory device according to the present embodiment by the memory cells MC and dummy memory cell DC remove charge of the bit line BL _A0, voltage change of the bit line BL _A0, for example shown in FIG. 7 (b) It becomes like this. In this case, the rate at which charges are extracted from the bit line BL _A is increased, and the time until the potential of the bit line BL _A0 reaches a low level can be shortened.

In addition, since the influence of variation is averaged by using the memory cell MC and the dummy memory cell DC, variation in time until the potential of the bit line _BLA0 reaches a low level can be significantly reduced. As a result, it is possible to shorten the aperture pulse width in the read guarantee range to the high speed side, and the cycle time can be shortened.

  The dummy memory cells DC are arranged around the memory cell array in order to improve the shape uniformity of the memory cells MC, and are not normally used. Therefore, even if the read circuit is configured using the dummy memory cell DC, the peripheral circuit area does not increase. Thereby, an increase in circuit area can be suppressed as compared with the case where a new assist circuit is added to improve the readout characteristics.

  Next, the results of simulation of the effect of the reading method of the semiconductor memory device according to the present embodiment will be explained with reference to FIGS.

  FIG. 8 shows a circuit model used for the simulation. The circuit in FIG. 8 is slightly different from the circuit shown in FIG. 4 in the configuration of the readout circuit, but the basic operation is the same. In the simulation, for comparison, the calculation was also performed when the dummy memory cell DC was not used.

During the read operation, the output of the NAND gate NAG3 becomes low level, the P-type transistor PQ8 is turned on, and the N-type transistor NQ8 is turned off. When the read potential of the bit line BL _A0 is at a low level, the P-type transistor PQ7 is turned on and the global bit line GBL is at a low level. On the other hand, when the read potential of the bit line BL _A0 is at a high level, the P-type transistor PQ7 is turned off and the global bit line GBL is maintained at a high level.

  The control signal OEN is at a high level in the standby state. In a state where the global bit line GBL is precharged to a high level, the node n2 is at a low level. During the read operation, the control signal OEN becomes low level. When the control signal OEN becomes low level, the node n2 remains at low level and the N-type transistor NQ9 is turned off.

When the potential of the bit line BL _A0 read to the global bit line GBL is at a high level, the P-type transistor remains in an off state, the level of the node n2 does not change, and the output A becomes a high level. That is, the high level state of the bit line BL _A0 can be read to the output A.

On the other hand, when the potential of the bit line BL _A0 read to the global bit line GBL is low level, the P-type transistor is on, the node n2 is high level, and the output A is low level. That is, the low level state of the bit line BL _A0 can be read to the output A.

  FIG. 9 is a time chart showing simulation results when the node mc is at a low level and the node mcx is at a high level (reading of low data). FIG. 10 is a time chart showing simulation results when the node mc is at the high level and the node mcx is at the low level (high data reading).

  In the case of reading raw data, the read method according to the present embodiment (described as “emb.” In the drawing) is compared with the read method according to the comparative example (described as “ref.” In the drawing). The speed at which the potential falls from the high level to the low level is high (see FIG. 9). As a result, it was found that the time required for the output A to change from the high level to the low level can be shortened in the reading method of the present embodiment as compared with the reading method of the comparative example. That is, it was verified that the reading speed can be increased by using the reading method according to the present embodiment. In the simulation result shown in FIG. 9, by using the reading method of the present embodiment, the reading speed can be increased by about 67.8 ps as compared with the reading method of the comparative example (the time between the x marks in the figure). Comparison).

  Further, in the case of reading high data, the potential of the bit line BL by using the reading method of this embodiment (described as “emb.” In the figure) can be slightly suppressed, and the reading method of the comparative example (FIG. Among them, a waveform equivalent to “ref.” Is obtained (see FIG. 10). As a result, it was found that the high-level output A can be read correctly. That is, in the reading method of the present embodiment, it was verified that no malfunction occurred when reading high data.

  FIG. 11 is a graph showing the distribution of readout time when the Monte Carlo simulation of readout time is performed 10,000 times. The horizontal axis indicates the read time (referred to as a delay value) normalized with the read time when the cumulative probability is 50% in the read method of the comparative example as 1, and the vertical axis indicates the cumulative probability. The read time is the time required until the output A is output.

  As shown in FIG. 11, at a cumulative probability of 50%, the delay value in the readout method of the comparative example is 1, whereas the delay value in the readout method of the present embodiment is 0.76. In addition, the variation range of the delay value in the readout method of the comparative example is about 0.6, whereas the variation range of the delay value in the readout method of the present embodiment is about 0.22. As a result, it can be seen that the readout method of the present embodiment can reduce the delay value to about 3/4 and can suppress the variation range of the delay value to about 1/3 compared with the readout method of the comparative example. It was. That is, it has been verified that the reading method of the present embodiment can realize a high reading speed and a reduction in reading time variation.

  The ability to reduce variations in read time has the effect of reducing margins in read timing design. This makes it possible to guarantee operation with a small margin under each PTV condition. The PTV condition is an operating condition that defines the best condition and the worst condition for three items of P: process, T: temperature, and V: voltage that affect the operation speed of the circuit.

  As described above, according to the present embodiment, in the single-ended reading of the SRAM, the charge of the bit line is extracted using the transistor of the selected memory cell and the transistor of the dummy memory cell, so that the reading operation is performed at high speed and stably. be able to.

[Modified Embodiment]
Although the embodiments of the semiconductor memory device and the reading method thereof have been described above, the present invention is not limited to the above-described embodiments, and various modifications, additions, substitutions, and the like are possible without departing from the spirit of the invention. .

For example, although the dummy memory cell DC is used as the read assist circuit in the above embodiment, the dummy memory cell DC is not necessarily used. From the viewpoint of realizing a read operation similar to that in the above embodiment, at least two transistors corresponding to the N-type transistors NQ _3D and NQ _1D may be connected to the memory cell MC. That is, the first N-type transistor and the second N-type transistor are connected in series, the gate electrode of the first N-type transistor is connected to the bit line / BL, the drain electrode is connected to the bit line BL, and the second The gate electrode of the N-type transistor is connected to the high potential side power supply node VH. A circuit for generating a control signal dcol having a reverse phase delayed by a predetermined time from the column selection signal colr for reading may be connected to the source electrode of the second N-type transistor.

DC ... dummy memory cell MC ... memory cell 10 ... memory cell array block 12 ... row selection circuit 14 ... write / read circuit 16 ... write / read control circuit 18 ... delay circuit

Claims (11)

A first bit line;
A second bit line paired with the first bit line;
Memory cells connected to the first bit line and the second bit line;
A first N-type transistor having a drain electrode connected to the first bit line and a gate electrode connected to the second bit line;
A second N-type transistor having a drain electrode connected to a source electrode of the first N-type transistor and a gate electrode connected to a high-potential side power supply node;
A control circuit that is connected to the source electrode of the second N-type transistor and applies a low-potential-side power supply voltage to the source electrode of the second N-type transistor in accordance with a column selection signal for reading. A semiconductor memory device. The semiconductor memory device according to claim 1.
The semiconductor memory device, wherein the control circuit applies the low-potential-side power supply voltage to the source electrode of the second N-type transistor with a delay of a first time from the column selection signal. The semiconductor memory device according to claim 1 or 2,
A dummy memory cell connected to the first bit line;
The semiconductor memory device, wherein the first N-type transistor and the second N-type transistor are transistors constituting the dummy memory cell. The semiconductor memory device according to claim 3.
The dummy memory cell is
A source electrode and a gate electrode are connected to the high potential side power supply node, and a drain electrode is connected to a first connection node between the first N-type transistor and the second N-type transistor. A P-type transistor;
A second P-type transistor having a source electrode connected to the high potential side power supply node and a gate electrode connected to the first connection node;
A drain electrode is connected to the drain electrode of the second P-type transistor, a gate electrode is connected to the first connection node, and a source electrode is connected to the source electrode of the second N-type transistor. An N-type transistor;
A fourth N-type transistor having a gate electrode connected to the second bit line and a source electrode connected to a second connection node between the second P-type transistor and the third N-type transistor; And a semiconductor memory device. The semiconductor memory device according to claim 4.
The semiconductor memory device, wherein a drain electrode of the fourth N-type transistor is separated from the second bit line. The semiconductor memory device according to claim 1,
A semiconductor memory device comprising: a plurality of other memory cells connected to the first bit line and the second bit line. A first bit line; a second bit line paired with the first bit line; a memory cell connected to the first bit line and the second bit line; and the first bit line. A first N-type transistor having a drain electrode connected to the line and a gate electrode connected to the second bit line; a drain electrode connected to the source electrode of the first N-type transistor; A method of reading a semiconductor memory device having a second N-type transistor having a gate electrode connected to a node,
When the information stored in the storage node on the first bit line side of the memory cell is read to the first bit line, the source of the second N-type transistor according to the column selection signal for reading A method for reading a semiconductor memory device, comprising applying a low-potential-side power supply voltage to an electrode. 8. The method of reading a semiconductor memory device according to claim 7,
The method of reading a semiconductor memory device and applying the low potential side power supply voltage to the source electrode of the first time delay and the second N-type transistor before Symbol column selection signal. The method of reading a semiconductor memory device according to claim 8.
In the first time, when the low-level information stored in the storage node is read out to the first bit line, the potential of the first bit line is changed from the high-potential power supply voltage to the low potential. A reading method of a semiconductor memory device, characterized in that it is equal to or longer than a time required for stepping down to a middle level between the side power supply voltage and the high potential side power supply voltage. In the reading method of the semiconductor memory device according to any one of claims 7 to 9,
When the low level information stored in the storage node is read out to the first bit line, the charge of the first bit line is transferred via the first N-type transistor and the second N-type transistor. And reading out the semiconductor memory device. The method for reading a semiconductor memory device according to claim 7, wherein:
The semiconductor memory device further includes a dummy memory cell connected to the first bit line, and the first N-type transistor and the second N-type transistor are transistors constituting the dummy memory cell. A reading method for a semiconductor memory device, comprising:

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