JP3389467B2 - Driving method of solid-state imaging device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a frame transfer CCD solid-state image pickup device capable of obtaining moving images and still images.

[0002]

2. Description of the Related Art An electronic still camera using a solid-state image pickup device has come to be used as a means for fetching image information into a computer device such as a personal computer or a word processor. This electronic still camera is configured to take a subject image as a moving image, that is, a series of still images, and to take out desired one-screen image information from the captured image, as in a conventional television camera or other imaging device. .
Usually, in the processing of image information of such an electronic still camera, in order to speed up the processing, a continuous image is reproduced with an image signal of a small amount of information that is appropriately thinned out, and a single screen to be finally taken out is reproduced. Complete signal processing is applied only to image information.

FIG. 10 is a block diagram showing the structure of a conventional electronic still camera. The CCD solid-state imaging device 1 has a plurality of light receiving pixels arranged in rows and columns and a shift register associated with each light receiving pixel. The plurality of light receiving pixels generate information charges in response to the light of the subject image irradiated on the light receiving surface by a well-known lens mechanism, and accumulate the information charges independently. The shift register transfers and outputs the information charges accumulated in each light receiving pixel in a predetermined order. Further, the solid-state image pickup device 1 is provided with a capacitance for accumulating information charges in pixel units at the output end of the shift register, and the charge amount of the information charges transferred and output is converted into a voltage value and taken out to obtain an image. Output as signal Y0 (t).

The drive circuit 2 supplies a multi-phase vertical transfer clock φv and a horizontal transfer clock φh to each shift register of the solid-state image pickup device 1 to supply information charges accumulated in a plurality of light receiving pixels in a predetermined order. Transfer output. That is, after the information charge of each light receiving pixel is transferred to the shift register according to the vertical scanning timing, 1 is transferred according to the horizontal scanning timing.
By transferring and outputting the data row by row, continuous image signals Y0 (t) can be obtained row by row. The timing control circuit 3 generates a horizontal synchronization signal HT and a vertical synchronization signal VT based on a reference clock having a constant cycle, and supplies the horizontal synchronization signal HT and the vertical synchronization signal VT to the drive circuit 2. The horizontal synchronizing signal HT and the vertical synchronizing signal VT are for determining the timings of horizontal scanning and vertical scanning of the solid-state image sensor 1, and are generated according to a predetermined format. At the same time, a timing signal PC for normalizing the image signal Y0 (t) according to the horizontal synchronizing signal HT and the vertical synchronizing signal VT is generated and supplied to the signal processing circuit 4 described later. In addition, the timing control circuit 3 stops the continuous image pickup operation of the drive circuit 2 in response to the image confirmation instruction DI, and causes the signal processing circuit 4 to transmit the image data D of a specific one screen corresponding to the image signal Y0 (t). Output (n).

The signal processing circuit 4 takes in the image signal Y0 (t) output from the solid-state image sensor 1 and outputs the timing signal P
An image signal Y1 (t) conforming to a predetermined format is obtained by performing various processes such as sample hold and level correction according to C.
Is supplied to the display device 5. This signal processing circuit 4 is
A display device including a D / D converter and a D / A converter, which performs signal processing of the image signal Y0 (t) as digital data, and returns to an analog image signal Y1 (t) after predetermined signal processing is completed. 5 is configured to feed. Further, the signal processing circuit 4 supplies digital image data D (n) corresponding to one screen of the image signal Y0 (t) when the timing control circuit 3 receives the image confirmation instruction DI to the outside as a still image output. To do. The display 5 is composed of, for example, an LCD panel, and continuously displays images taken by the solid-state imaging device 1 according to the image signal Y1 (t) supplied from the signal processing circuit 4. After receiving the image confirmation instruction DI, the still image corresponding to the image data D (n) output as the still image output is displayed.

FIG. 11 is a schematic diagram showing the structure of the CCD solid-state image pickup device 1, showing the case of the frame transfer system. In this figure, for simplification of the drawing, the array of light receiving pixels is shown in 12 rows × 16 columns. And FIG.
2 is a timing chart showing the relationship between each transfer clock driving the solid-state image sensor 1 and each synchronization signal. The frame transfer type CCD solid-state imaging device 1 is composed of an imaging unit 1i, a storage unit 1s, a horizontal transfer unit 1h, and an output unit 1d.
The imaging unit 1i is composed of a plurality of CCD shift registers that are continuous in the vertical direction and are parallel to each other, and each bit of these shift registers constitutes a light receiving pixel. The frame transfer clocks φf1 to φf3 synchronized with the vertical synchronizing signal VT are applied to the image pickup unit 1i, and the information charges accumulated in each light receiving pixel during the image pickup period are rapidly transferred to the storage unit 1s during the blanking period of vertical scanning. Transferred.

The storage section 1s is composed of a plurality of CCD shift registers that are continuous with the shift register of the image pickup section 1i and have the same number of bits. Each bit of these shift registers constitutes a storage pixel, and each of the image pickup section 1i The information charges transferred and output from the light receiving pixels are temporarily stored. This storage unit 1s
Is applied with the vertical transfer clocks φv1 to φv3 synchronized with the vertical synchronization signal VT and the horizontal synchronization signal HT.
The information charges are taken in by one screen unit from the above, and the taken information charges are transferred to the horizontal transfer unit 1h in one row unit in the blanking period of the horizontal scanning.

The horizontal transfer section 1h is composed of a single CCD shift register in which the output of each shift register of the storage section 1s is connected to each bit, and each of the information charges transferred and output from each shift register of the storage section 1s is transferred. Receive a bit. Horizontal transfer clocks φh1 and φh2 synchronized with the horizontal synchronizing signal HT are applied to the horizontal transfer unit 1h, and information charges transferred and output in units of one horizontal line from each shift register of the storage unit 1s are sequentially output to the output unit 1d side. Transferred to.

The output section 1d includes a capacitor for receiving information charges on the output side of the horizontal transfer section 1h, receives the information charges transferred and output from the horizontal transfer section 1h, and outputs a voltage value according to the charge amount. The output unit 1d has a horizontal transfer clock φh1,
A reset clock φr according to φh2 is applied, and the information charges sequentially transferred and output from the horizontal transfer unit 1h are discharged on a pixel-by-pixel basis, so that a voltage value corresponding to the information charge amount for each pixel is extracted. The change in the voltage value output here becomes the image signal Y0 (t).

In such a frame transfer type solid-state image pickup device 1, since the storage unit 1s for temporarily storing the information charges obtained by the image pickup is separated from the light receiving pixel of the image pickup unit 1i, There is little leakage of unnecessary charges from the.
Therefore, it is suitable for an electronic still camera that reads out information charges from a solid-state image sensor at arbitrary timing to obtain a still image.

[0011]

In the case of the electronic still camera described above, the solid-state image pickup device 1 is continuously operated to take out a moving image, and a desired still image can be taken out while watching the moving image. Since the moving image at this time is a mere confirmation screen, it does not need to have high image quality, and normally, the information amount of the image signal Y0 (t) is reduced in advance to reduce the amount of information.
Simplifies signal processing in. That is, the signal processing circuit 4
The image signal Y0 (t) is thinned out in a constant column unit or row unit at the input stage, to reduce the amount of information, simplify various signal processing, and speed up the processing.

However, the configuration for thinning out the image signal Y0 (t) in the signal processing circuit 4 speeds up the circuit operation of the input portion to increase power consumption and tends to increase the circuit scale itself. Therefore, the cost is increased. Therefore, it is an object of the present invention to thin out the number of pixels to obtain an image signal in which the amount of information is reduced in advance in the process of transferring information charges in a solid-state image sensor.

[0013]

The present invention has been made to solve the above-mentioned problems, and is characterized in that a semiconductor of opposite conductivity type is formed on one main surface of a semiconductor substrate of one conductivity type. A region is formed, a plurality of channel regions extending in the column direction are formed in the semiconductor region, and a plurality of transfer electrodes extending in the row direction are formed on the semiconductor region. In a method for driving a solid-state imaging device, in which light-receiving pixels and storage pixels are defined in the channel region for each number, a semiconductor substrate is provided between the channel region and the substrate region in a first period in which charges are accumulated. A first potential that forms a potential barrier having a predetermined height is applied, and the height of the potential barrier between the channel region and the substrate region is limited to a low level during a second period that is continuous with the first period. Second It applies a position with respect to the first light receiving pixels arranged at regular intervals in the column direction, the first
And during the second period, a third potential for maintaining a potential barrier between the channel region and the substrate region is applied to at least one of the transfer electrodes, and the third potential is applied between the array of the first light receiving pixels. With respect to the second light receiving pixel to be arranged, the third potential is applied to at least one of the transfer electrodes during the first period, and the channel region and the substrate region during the second period. And a fourth image pickup operation of applying a fourth potential to all of the transfer electrodes, which eliminates a potential barrier between the first and second light receiving pixels, during the first period. Is transferred to the storage pixel in a third period following the second period.

According to the present invention, predetermined information charges are respectively accumulated in the first and second light receiving pixels during the first period, and the information accumulated in the first light receiving pixel during the subsequent second period. Only the information charges accumulated in the second light receiving pixels while the charges are held are discharged from the channel region to the substrate region. As a result, information charges are thinned out in accordance with the arrangement interval of the first light receiving pixels, and an image signal with a reduced amount of information can be obtained.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 3 is a sectional view showing the structure of a solid-state image pickup device having a vertical overflow drain structure to which the driving method of the present invention is applied. Note that this solid-state image sensor uses the same frame transfer method as in FIG. 11, and FIG. 3 shows the image pickup section thereof. On the main surface of the N-type semiconductor substrate 11,
A P-type diffusion region 12 is formed, and a plurality of channel regions extending in one direction (horizontal direction in the drawing) are formed in the diffusion region 12 in parallel with each other. Each channel area is
This is a region that serves as a transfer path for information charges, and an N-type buried layer 13 is formed near the surface to form a buried channel structure. The semiconductor substrate 11 also functions as an overflow drain that absorbs information charges leaking from the channel region. On the channel region in which the buried layer 13 is formed, a plurality of transfer electrodes 15 extending in a direction intersecting with the channel region are arranged in parallel with each other through the insulating film 14. The transfer electrode 15 may have a two-layer structure in which the transfer electrode of the first layer is covered with the transfer electrode of the second layer. When three-phase driving is adopted, the transfer electrodes 15 set the first and second light receiving pixels P1 and P2 in the channel region in units of three lines. And the first
In the channel region 16 where the light receiving pixel P1 is set, an N-type implantation region 16 having a lower impurity concentration than the buried layer 13 is formed so as to correspond to the central transfer electrode 15. The injection region 16 is for making it difficult for the information charges to escape from the buried layer 13 to the semiconductor substrate 11 side, but is unnecessary if the information charges can be reliably retained only by the action of the transfer electrode 15. Becomes

FIG. 6 is a schematic view showing the structure of a frame transfer type CCD solid-state image pickup device according to the present invention. In this figure, in order to simplify the drawing, the array of the first and second light receiving pixels P1 and P2 is shown in 12 rows × 16 columns. The frame transfer type CCD solid-state imaging device 20 includes an imaging unit 20i, a storage unit 20s, a horizontal transfer unit 20h, and an output unit 20d. The imaging unit 20i is composed of a plurality of CCD shift registers that are continuous in the vertical direction and are parallel to each other, and each bit of these shift registers constitutes the first and second light receiving pixels P1 and P2, respectively. A first light receiving pixel P1 for accumulating information charges in the first and second imaging operations and a second for accumulating information charges only in the second operation mode.
And the light receiving pixels P2 are continuous in the row direction to form a first row L1 and a second row L2. The first row L1 is
The second row L2 is arranged row by row with a fixed interval.
Are arranged between the first rows in an appropriate number. In the present embodiment, two second rows L2 are arranged between the first rows L1. Then, in the first row, the transfer clock φf
1, φf2 ′ and φf3 are applied, and the transfer clocks φf1 to φf3 are applied to the second row L2. Each light receiving pixel P1, P2
When the information charge accumulated in the storage section 20s is transferred, the transfer clock φf2 and the transfer clock φf2 ′ are matched and the information charge is transferred to the storage section 20s (frame transfer). In the first image pickup operation, the transfer of the information charges is performed by the vertical synchronization signal VT as in the image pickup section 1i of the solid-state image pickup device 1 shown in FIG.
It is performed at high speed at the timing synchronized with. On the other hand, in the second imaging operation, high-speed transfer is not performed, and
Similar to the storage unit 1s of the solid-state image sensor 1 shown in FIG. 1, the scanning is performed row by row in a cycle according to horizontal scanning.

The storage section 20s is composed of a plurality of CCD shift registers which are continuous with the shift register of the image pickup section 20i, and each bit of these shift registers constitutes a storage pixel S. The storage unit 20s is optically shielded from light and temporarily stores the information charges transferred and output from the first light receiving pixels P1 of the imaging unit 20i. Storage unit 20
The number of vertical accumulation pixels S of s is equal to
The number of rows L1 of the same, that is, the number of the first light receiving pixels P1 of the imaging unit 20i. In the present embodiment, the storage unit 20s has 1/3 rows (4 rows × 16 columns) of the imaging unit 20i.
Is formed. Vertical transfer clocks φv1 to φv3 synchronized with the vertical synchronizing signal VT or the horizontal synchronizing signal HT are applied to each row of the storage unit 20s. In the first image pickup operation, the information charges are fetched from the first light receiving pixel P1 of the image pickup unit 20i at a frequency of 1/3 of the transfer clocks φf1 to φf3 and φf2 ′, and the fetched information charges are read in one row every horizontal scanning period. Transfer to the horizontal transfer unit 20h one by one. In the second imaging operation, the vertical transfer clocks φv1 to φv3 are transferred to the transfer clocks φf1 to φf3, φ
The information charges from the first light receiving pixels P1 are sequentially transferred to the horizontal transfer unit 20h by matching with f2 ′ and operating as an extension of each shift register of the imaging unit 20i.

The horizontal transfer unit 20h has a single CC in which the output of each shift register of the storage unit 20s is combined with each bit.
Each bit is formed of a D shift register and receives the information charges transferred and output from each shift register of the storage section 20s. The output unit 20d includes a capacitor that receives information charges on the output side of the horizontal transfer unit 20h, receives the information charges transferred and output from the horizontal transfer unit 20h, and outputs a voltage value according to the charge amount. The horizontal transfer unit 20h and the output unit 20d are the same as the horizontal transfer unit 1h and the output unit 1d of the solid-state imaging device 1 shown in FIG. That is, the information charges in the horizontal transfer unit 20h are transferred to the output unit 20d in response to the horizontal transfer clocks φh1 and φh2 synchronized with the horizontal synchronization signal HT, and the information charges accumulated in the capacitance of the output unit 20d are reset clock φr. Are configured to sequentially discharge in response to. Then, the output unit 20
The change in the potential of the capacitance of d is output as the image signal Y0 (t).

When the solid-state image pickup device 20 is compatible with color image pickup, a color filter is attached to the light receiving portion 20i so that the first and second light receiving pixels P1 and P2 are respectively associated with specific color components. For example, as shown in FIG. 7, cyan (Cy) and yellow (Ye) are alternately arranged in odd rows, and white (W) and green (G) are alternately arranged in even rows. When such a color filter is attached to the image pickup unit 20i, 6 pixels in the vertical direction can be set as one unit, and different color components can be extracted from 2 pixels of the unit. As a result, even in the first imaging operation for performing low-resolution imaging, it is possible to independently extract all color components, as in the second imaging operation for reading information charges from all light-receiving pixels.

1 and 2 are timing charts for explaining a method of driving the solid-state image pickup device according to the present invention. The first image pickup operation for extracting only the information charges of the first light-receiving pixel P1 and all the light-receiving pixels P1. , P2, the second imaging operation for taking out the information charges of P2, respectively. In the present embodiment, three-phase transfer clocks φf1 to φf3 and three-phase vertical transfer clocks φ
v1 to φv3 and two-phase horizontal transfer clocks φh1 and φh2 are used. In such a case, in the imaging unit 20i, as shown in FIG. 3, three transfer electrodes 15 are arranged per pixel for each of the light receiving pixels P1 and P2. Then, the transfer clocks φf1 and φf3 are applied to both ends of the light receiving pixels P1 and P2, respectively, and the transfer clock φf2 is applied to the center of the first light receiving pixel P1 to the respective transfer electrodes 15, and the second light receiving pixels are applied. P
At the center of 2, the clock φf2 'is applied. For the semiconductor substrate 11, transfer clocks φf1 to φf3, φf2 ′ are provided.
Substrate clock φsub synchronized with is applied.

As shown in FIG. 1, in the first image pickup operation, the information charges are accumulated in the first period T1, and the accumulation amount of the information charges is limited in the subsequent second period T2. Then, the information charges are transferred in the third period T3 subsequent to the second period T2. The information charges are transferred in the third period T3 by frame transfer in which the information charges for one screen in which the number of pixels is thinned are read out at high speed from the imaging unit 20i to the storage unit 20s, and the horizontal transfer unit 20h from the storage unit 20s. The information transfer is performed in two steps, that is, line transfer for reading out the information charges for each row.

The transfer clocks φf1 to φf3 and φf2 'are the first
Has a high-frequency discharge pulse immediately before the period T1 and a high-frequency read pulse at the beginning of the third period T3 (frame transfer period). The transfer clock φf2 is fixed at a high level in the first period T1 and the second period T2, and the transfer clocks φf1 and φf3 are from the first period T1 to the third period T3 except for the frame transfer period. Fixed at low level. The transfer clock φf2 ′ is fixed at a high level together with the transfer clock φf2 during the first period T1, and is fixed at a low level together with the transfer clocks φf1 and φf3 during the second period T2. The substrate clock φsub is the transfer clock φf.
It is raised and fixed to a high level in a period corresponding to the discharge pulse of 1 to φf3 and φf2 ′ and the second period T2, and fixed to a low level in the other first period T1 and third period T3. .

Immediately before the first period T1, the substrate clock φsu
b is raised to high level and transfer clocks φf1 to φf
3, when the discharge pulse of φf2 ′ is applied, the semiconductor substrate 11
At the same time that the potential on the side becomes deeper, the potential on the transfer electrode 15 side becomes periodically shallower. At this time, since a potential profile that deepens toward the deep portion of the semiconductor substrate 11 is formed under each of the light receiving pixels P1 and P2, all the information charges accumulated in each of the light receiving pixels P1 and P2 before that are all formed on the semiconductor substrate. It is discharged to the 11 side.

When the transfer clocks φf1 and φf3 are fixed to the low level in the first period T1 and the second period T2, as shown in FIG. 4, the light receiving pixels P1 and P2 are separated into both ends. A potential barrier is formed. In the first period T1, when the substrate clock φsub is fixed to the low level and the transfer clocks φf2 and φf2 ′ are fixed to the high level, at the center of each of the light receiving pixels P1 and P2, the curve a in FIG. A potential profile as shown in is formed. That is, a potential profile is formed which becomes deeper as it goes away from the transfer electrode 15, shows a minimum value in the buried layer 13 and a maximum value in the diffusion region 12, and becomes deeper again as it goes from the diffusion region 12 to the deep part of the semiconductor substrate 11. To be done. As a result, in each of the light receiving pixels P1 and P2, it becomes possible to accumulate the information charges corresponding to the difference between the minimum value in the buried layer 13 and the maximum value in the diffusion region 12.

In the second period T2, the transfer clock φ
When the clock φsub is raised to the high level while keeping the f2 at the high level, the potential profile in the depth direction at the center of the first light receiving pixel P1 changes as shown by the curve b in FIG. That is, the potential on the semiconductor substrate 11 side becomes deeper, and the maximum value in the diffusion region 12 lowers accordingly. As a result, the difference between the local minimum value in the buried layer 13 and the local maximum value in the diffusion region 12 becomes small, and the storage capacity of the information charge becomes small, and the storage capacity at this time is exceeded, and the information charge is stored in the first period T1. The information charges are discharged to the semiconductor substrate 11 side. When the clock φsub is raised to the high level and the transfer clock φf2 ′ is lowered to the low level at the same time in the second period T2, the potential profile in the depth direction at the center of the second light receiving pixel P2 is as shown in the figure. 5 changes as shown by the curve c. That is, the potential on the semiconductor substrate 11 side becomes deep and at the same time the potential on the transfer electrode 15 side becomes shallow,
The minimum value in the buried layer 13 and the maximum value in the diffusion region 12 are reversed. As a result, the potential barrier in the diffusion region 12 disappears, and all the information charges accumulated in the first period T1 are discharged to the semiconductor substrate 11 side. Therefore, at the end of the second period T2 of the first imaging operation, as shown in FIG. 4, the information charges are accumulated only in the first light receiving pixel P1.

In the image pickup section 20i, the storage capacity of the information charges in the channel region is fixed to the first by fixing the potential of the transfer electrode 15 due to the delay of the potential fluctuation in the channel region with respect to the potential fluctuation of the transfer electrode 15. It becomes smaller than the period T1 in the third period T3 in which the high frequency is applied. For this reason, when the amount of information charges close to the saturation amount is accumulated in the first period T1, a part of the information charges may remain in the channel region without being transferred in the third period T3. To prevent such transfer residue of information charges,
In the second period T2, the storage capacity of the information charges in the channel region is limited. This second period T
In 2, the discharge of the information charges of the second light receiving pixel P2 and the limitation of the storage capacity are simultaneously performed.

In the third period T3, the substrate clock φ
Transfer clock φf1 with sub kept at low level
When a read pulse of ~ φf3, φf2 'is applied, the first
The information charges accumulated in the light receiving pixel P1 are transferred from the imaging unit 20i to the storage unit 20s and output along the extending direction of the channel region. At this time, since the information charges are accumulated only in the first light receiving pixels P1, the image pickup unit 20i in which the two second light receiving pixels are arranged between the vertical arrangements of the first light receiving pixels P1 is 3 Each time pixel transfer is performed, one pixel of information charge is output.

The vertical transfer clocks .phi.v1 to .phi.v3 have a read pulse having a frequency of 1/3 of that of the transfer clocks .phi.f1 to .phi.f3 at the beginning of the charge transfer period, and a line feed pulse having a constant period following the read pulse. . The horizontal transfer clocks φh1 and φh2 are the vertical transfer clocks φv1 to φh.
It has a high frequency output pulse corresponding to the v3 line feed pulse. The operation based on the vertical transfer clocks φv1 to φv3 and the horizontal transfer clocks φh1 and φh2 is the same as in FIG.
It is the same as the CCD solid-state image sensor 1 shown in FIG. Therefore, the information charges intermittently output from the imaging unit 20i are sequentially taken into the storage unit 20s and temporarily stored in the storage pixel S, and then from the storage unit 20s to the horizontal transfer unit 20h at a constant cycle. After the data is transferred in units of one row, it is transferred from the horizontal transfer unit 20h in units of one pixel and output to the output unit 20d.

In the case of the first image pickup operation, the same operation is repeated at a constant cycle. Therefore, the transfer output of the information charges of the current screen and the accumulation of the information charges of the next screen should be overlapped. Is done. That is, the first period T1
2, the vertical transfer clocks φv1 to φv3 and the horizontal transfer clocks φh1 and φh2 each have a line feed pulse and an output pulse, and while the information charge is accumulated in the imaging unit 20i, the previous one in the accumulation unit 20s. The information charges of the screen are transferred.

According to the first image pickup operation, the information charges accumulated in the first light receiving pixel P1 are repeatedly read out at a predetermined cycle, and an image signal representing a moving image can be obtained at a low resolution. As shown in FIG. 2, in the second imaging operation,
Information charges are accumulated in the first period T1, and the accumulation amount of information charges is limited in the subsequent second period T2. Then, the information charges are transferred in the third period T3 subsequent to the second period T2. The transfer of the information charges in the third period T3 is performed only by the line transfer for reading the information charges from the imaging unit 20i through the storage unit 20s for each row.

The transfer clocks φf1 to φf3 and φf2 'are the first
Immediately before the period T1 of, the high-frequency discharge pulse is provided, and the line feed pulse of a constant cycle is provided during the third period T3. The transfer clocks φf2 and φf2 ′ coincide with each other and are fixed at a low level during the first period T1 and the second period T2. The transfer clocks φf1 and φf3 are used in the first period T1 and the second period.
During the period T2 of, the level is fixed to the low level. In addition, the substrate clock φsub is raised and fixed at a high level during the period corresponding to the discharge pulse of the transfer clocks φf1 to φf3 and φf2 ′ and the second period T2, and the other first period T1.
And is fixed to the low level during the third period T3.

Immediately before the first period T1, the substrate clock φsu
b is raised to high level and transfer clocks φf1 to φf
3, when the discharge pulse of φf2 ′ is applied, the semiconductor substrate 11
At the same time that the potential on the side becomes deeper, the potential on the transfer electrode 15 side becomes periodically shallower. The operation at this time corresponds to the first imaging operation. When the transfer clocks φf1 and φf3 are fixed to the low level in the first period T1 and the second period T2, as shown in FIG. 4, potential barriers for separating pixels are formed at both ends of each of the light receiving pixels P1 and P2. It is formed.

In the first period T1, the substrate clock φ
transfer clock φf2, φf2 'with sub fixed at low level
Is fixed to a high level, a potential profile as shown by a curve a in FIG. 5 is formed in the depth direction at the center of each of the light receiving pixels P1 and P2, as in the first imaging operation. As a result, in each of the light receiving pixels P1 and P2, it becomes possible to accumulate the information charges corresponding to the difference between the minimum value in the buried layer 13 and the maximum value in the diffusion region 12.

In the second period T2, the transfer clock φ
Clock φsub with f2 and φf2 'maintained at high level
Is raised to a high level, the potential profile in the depth direction at the center of each of the light receiving pixels P1 and P2 changes as shown by the curve b in FIG. 5, as in the first imaging operation. As a result, the difference between the local minimum value in the buried layer 13 and the local maximum value in the diffusion region 12 becomes small, and the storage capacity of the information charge becomes small, and the storage capacity at this time is exceeded, and the information charge is stored in the first period T1. The information charges are discharged to the semiconductor substrate 11 side. In the second imaging operation, at the end of the second period T2, as shown in FIG.
Information charges are accumulated in 1 and P2, respectively.
The limitation on the storage capacity of the information charges in the second period T2 is the same as that in the first imaging operation.

In the third period T3, the substrate clock φ
Transfer clock φf1 with sub kept at low level
When the line sending pulses of ~ φ3 and φf2 'are applied, the information charges accumulated in the respective light receiving pixels P1 and P2 are transferred row by row to the accumulating section along the extending direction of the channel region.
The vertical transfer clocks .phi.v1 to .phi.v3 have line feed pulses that match the transfer clocks .phi.f1 to .phi.f3 during the third period T3. In the third period T3, the vertical transfer clock φv1 ~
The transfer operation based on φv3 coincides with the transfer operation based on the transfer clocks φf1 to φf3, and information charges are transferred and output from the image pickup unit 20i through the storage unit 20s to the horizontal transfer unit on a row-by-row basis. The horizontal transfer clocks φh1 and φh2 have high-frequency output pulses corresponding to the line feed pulses of the vertical transfer clocks φv1 to φv3 during the third period T3. The horizontal transfer clocks φh1 and φh2 are the same as those in the first image pickup operation,
The horizontal transfer unit 20 from the imaging unit 20i through the storage unit 20s
The information charges transferred to and output from the horizontal transfer unit 20h are output from the horizontal transfer unit 20h in units of one pixel.

In the case of the second image pickup operation, since a still image for one screen is obtained, it is not necessary to repeatedly store the information charges in the image pickup section 20i, and the information charge accumulated in the image pickup section 20i is read out. Is given enough time. However, when the second imaging operation is performed, the imaging unit 2
Since all the information charges accumulated in each of the light receiving pixels P1 and P2 of 0i cannot be taken into the accumulation pixels of the accumulation unit 20s as they are, most of the information charges are held at the position where the photoelectric conversion operation is possible even during the charge transfer period. To be done. Therefore, a shutter mechanism is provided so as to cover the solid-state image sensor 20, and the shutter mechanism is closed as soon as the charge accumulation period ends, and the image pickup unit 2 is closed.
Generation of smear charges is prevented by blocking 0i.

According to the second image pickup operation, the information charges accumulated in the first and second light receiving pixels P1 and P2 of the image pickup section 20i are sequentially read out in a state where the image pickup section 20i is shielded, and the information charges are high. It is possible to obtain an image signal representing a still image with a resolution. FIG. 8 is a block diagram showing the configuration of an electronic still camera that adopts the driving method of the present invention to obtain a first image signal representing a moving image and a second image signal representing a still image. FIG. 9 is a timing chart for explaining the operation.

The CCD solid-state image pickup device 20 shown in FIG. 6 has a storage unit 20s in which the number of rows is reduced to 1/3 with respect to the image pickup unit 20i, and various clocks supplied from the drive circuit 21. Driven by, and outputs an image signal Y0 (t). The shutter mechanism 30 is arranged on the optical path on which the subject image is projected onto the image pickup section 20i of the solid-state image pickup device 20 through a well-known lens mechanism, and shields the image pickup section 20i as necessary. The shutter mechanism 30 only needs to be capable of controlling the transmission of light, and can be configured using a liquid crystal panel, a light shielding plate, or the like. The shutter drive circuit 21 generates a drive clock φd based on a shutter control signal ST supplied from a timing control circuit 22 described later, and drives the shutter mechanism 30 to open and close. For example, the shutter mechanism 30 is opened while the shutter control signal ST is rising, and the shutter mechanism 30 is closed while the shutter control signal ST is falling.

The drive circuit 21 transfers the transfer clocks φf1 to φf3, φf to each shift register of the solid-state image pickup device 20.
2 ', vertical transfer clocks .phi.v1 to .phi.v3 and horizontal transfer clocks .phi.h1, .phi.h2 are supplied to transfer and output the information charges accumulated in the plurality of light receiving pixels P1, P2 in a predetermined order. That is,
Each light-receiving pixel P of the imaging unit 20i passes through a fixed charge accumulation period.
1 and P2, the information charges accumulated in P2 are transferred and output for each pixel in a predetermined order, and the image signal Y0 (t) is continuous for each line.
I am trying to get it. The information charge transfer operation in the solid-state imaging device 20 follows the first imaging operation shown in FIG. 6 or the second imaging operation shown in FIG. 7.

The timing control circuit 22 makes the solid-state image pickup device 20 continuously operate in the first image pickup operation to obtain the first image signal Y0 (t) for displaying a moving image, and the solid-state image pickup operation in the second image pickup operation. The image sensor is operated only once so that the second image signal y0 (t) for displaying a still image can be obtained. At the same time, for the shutter drive circuit 31 that drives the shutter mechanism 30 that shields the image pickup unit 20i of the solid-state image pickup device 20,
The shutter mechanism 30 is opened in the first image pickup operation, and the shutter mechanism 30 is opened for a certain period of time in the second image pickup operation and then closed to give an instruction to shield the image pickup unit 20i of the solid-state image pickup device 20 from light.

In the first image pickup operation, the horizontal synchronizing signal HT and the vertical scanning signal VT are generated on the basis of the reference clock having a constant period and are supplied to the drive circuit 21.
To operate periodically. Thereby, the solid-state imaging device 20
Repeats image pickup only with the first light-receiving pixel P1 of the image pickup section 20i, and outputs the first image signal Y0 (t) from which the number of rows is thinned to 1/3 from the image pickup section 20i. At this time, the shutter control signal ST is still raised, and the shutter drive circuit 31 maintains the shutter mechanism 30 in the open state. During the first imaging operation, the timing signal PC for standardizing the image signal Y0 (t) is simultaneously generated and supplied to the signal processing circuit 23.

When the image confirmation instruction DI is input while the first image pickup operation is continuing, the first image pickup operation is terminated at that point and the second image pickup operation is started. In the second image pickup operation, first, the shutter control signal ST falls and the shutter mechanism 30 is temporarily closed to shield the image pickup section 20i of the solid-state image pickup device 20 from light. In this state, the frame transfer operation is performed to discharge the information charges accumulated in each light receiving pixel of the image pickup unit 20i. This discharging operation may be performed by repeating the same operation as the first imaging operation once after closing the shutter mechanism 30. After the discharge operation of unnecessary electric charges is completed, the shutter control signal ST is raised for a predetermined period, and the shutter mechanism 3
By opening 0, information charges are accumulated in all the light receiving pixels of the image pickup section 20i of the solid-state image pickup device 20. This shutter mechanism 3
The open time of 0 is set according to the brightness of the subject so that the average amount of information charges accumulated in the image pickup unit 20i of the solid-state image pickup device 20 falls within a predetermined range. Here, the optimum shutter opening time may be set based on the average level of the first image signal Y0 (t) obtained in the first image pickup operation, or may be set by directly measuring the brightness of the subject. Conceivable. In the second image pickup operation, the solid-state image pickup element 20 does not involve the frame transfer operation, but the shutter mechanism 30 needs to shield the image pickup section 20i from light.
In the image pickup unit 20i shielded by the shutter mechanism 30, the information charges accumulated in the light receiving pixels having a larger number of rows than in the accumulating unit 20s are read out row by row. As a result, the solid-state image sensor 20 outputs the second image signal y0 (t) that displays the pixels corresponding to the light receiving pixels P1 and P2 of the image capturing unit 20i.

The signal processing circuit 23 takes in the first image signal Y0 (t) output from the solid-state image pickup device 20, performs various kinds of processing such as sample hold and level correction according to the timing signal PC, and has a predetermined format. The image signal Y1 (t) is supplied to the display 24. The signal processing circuit 23 includes an A / D converter and a D / A converter, and
The image signal Y0 (t) is subjected to signal processing as digital data, and after predetermined signal processing is completed, the image signal Y1 (t) having an analog value is restored and supplied to the display unit 24. The signal processing circuit 23 repeats the above-described signal processing as the first imaging operation until the timing control circuit 22 receives the image confirmation instruction DI. After receiving the image confirmation instruction DI, the digital image data D (n) corresponding to the second image signal y0 (t) representing the information charges from all the light receiving pixels of the image pickup unit 20i of the solid-state image pickup device 20 is stopped. It is supplied to the outside as an image output. At this time, the display unit 24 is also supplied with the image signal Y1 (t) corresponding to the still image output and with the number of pixels thinned out. The display 24 is composed of an LCD panel or the like, and continuously displays images taken by the solid-state imaging device 20 according to the image signal Y1 (t) supplied from the signal processing circuit 23.

As described above, by changing the substantial number of light-receiving pixels of the solid-state image pickup device 20 between the first image pickup operation and the second image pickup operation, an image signal for displaying a low-resolution moving image. In the first image pickup operation for obtaining the above, the signal processing of the signal processing circuit 23 can be simplified.

[0045]

According to the present invention, the number of light receiving pixels to be read can be operatively thinned, and an image signal in which the amount of information is omitted can be obtained in advance. Therefore, the signal processing circuit can be simplified and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a timing diagram illustrating a first imaging operation of a method for driving a solid-state imaging device according to the present invention.

FIG. 2 is a timing diagram illustrating a second imaging operation of the method for driving a solid-state image sensor according to the present invention.

FIG. 3 is a cross-sectional view showing a structure of an imaging section of a solid-state imaging device having a vertical overflow drain structure.

FIG. 4 is a potential diagram in the image pickup section of the solid-state image pickup device of FIG.

5 is a potential profile diagram in the depth direction in the image pickup section of the solid-state image pickup device of FIG.

FIG. 6 is a plan view showing the outline of a frame transfer type solid-state imaging device to which the driving method of the solid-state imaging device of the present invention is applied.

FIG. 7 is a plan view showing a configuration example of a mosaic type color filter.

FIG. 8 is a block diagram showing a configuration of an image pickup apparatus adopting the method for driving a solid-state image pickup element according to the present invention.

9 is a timing diagram illustrating an operation of the image pickup apparatus in FIG.

FIG. 10 is a block diagram showing a configuration of a conventional imaging device.

FIG. 11 is a plan view showing the outline of a conventional frame transfer type solid-state imaging device.

FIG. 12 is a timing diagram illustrating an operation of a frame transfer type solid-state imaging device.

[Explanation of symbols]

1, 20 CCD solid-state image sensor 1i, 20i Imaging unit 1s, 20s storage unit 1h, 20h Horizontal transfer section 1d, 20d output section 2,21 CCD drive circuit 3,22 Timing control circuit 4, 23 Signal processing circuit 5,24 indicator 11 Semiconductor substrate 12 diffusion area 13 Embedded layer 14 Insulating film 15 Transfer electrode 16 injection area 30 shutter mechanism 31 Shutter drive circuit

Claims (5)

(57) [Claims] 1. A semiconductor region of opposite conductivity type is formed on one main surface of a semiconductor substrate of one conductivity type, a plurality of channel regions extending in the column direction are formed in the semiconductor region, and the semiconductor region is also formed. A plurality of transfer electrodes extending in the row direction are formed above , and a light receiving pixel is defined in the imaging unit and a storage pixel in the storage unit in the channel region for every fixed number of the transfer electrodes. In the method for driving a solid-state image sensor, the first barrier for forming a potential barrier having a predetermined height between the channel region and the substrate region in the first period for accumulating charges in the semiconductor substrate. Apply the potential of
A second potential that limits the height of the potential barrier between the channel region and the substrate region to a low level is applied in a second period that is continuous with the first period, and a constant interval is provided in a row direction in a column direction. A third potential for maintaining a potential barrier between the channel region and the substrate region during at least the first and second periods with respect to the first light-receiving pixel arranged at. A second light-receiving pixel, which is applied between the first light-receiving pixel array and the first light-receiving pixel array.
A fourth potential is applied to at least one of the transfer electrodes during the first period, and a potential barrier between the channel region and the substrate region is eliminated during the second period. A first imaging operation of applying the potential of 1 to all the transfer electrodes, and the information charge accumulated in the first light-receiving pixel in the first period is connected to the second period in a third period. The same number of rows as the number of rows of the first light receiving pixel
A method for driving a solid-state image pickup device, which comprises transferring to the above-mentioned storage pixels arranged in columns . 2. The first and second light receiving pixels,
During the first and second periods, the method further includes a second image pickup operation of applying the third potential to at least one of the transfer electrodes, and the first image pickup operation is repeatedly executed to continuously perform in screen units. The second image signal for displaying a single still screen is obtained by executing the second image pickup operation at a desired timing while obtaining the first image signal for
7. A method for driving a solid-state image sensor according to item 4. 3. In the first imaging operation, the first
And irradiating the light-receiving pixel with light from the subject during a second period, irradiating the light-receiving pixel during the first period in the second imaging operation, and irradiating the light-receiving pixel during the second period. The method for driving the solid-state image pickup device according to claim 2, wherein the method is to block light. 4. The method according to claim 3, wherein, in the first period of the second imaging operation, the time for irradiating the light-receiving pixels with light is expanded or contracted according to the intensity of light from the subject. Driving method of the solid-state image pickup device. 5. The second potential is applied to the semiconductor substrate and the fourth potential is applied to the transfer electrode at the start of the first period of the second imaging operation. 4. The method for driving a solid-state image sensor according to claim 3, wherein the potential barrier between the channel region and the substrate region is eliminated to discharge the information charges in the channel region once.