JP3393246B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention uses a semiconductor device having a MOS structure in which an internal circuit has a low power supply voltage specification in order to reduce power consumption, while a high power supply voltage circuit is mixed as an input / output circuit. And its manufacturing method. In particular, the present invention relates to a circuit dividing method for easily improving device performance without lowering reliability and yield of a gate oxide film due to different power supply voltages.

[0002]

2. Description of the Related Art Conventionally, the power supply voltage of a MOS LSI has been mainly 5V. However, with the recent trend toward device miniaturization and low power consumption, the power supply voltage is 2.
L using a MOS transistor operating at 5 to 3.3V
SI has appeared. Because the power consumption of MOS transistors is generally proportional to the square of the power supply voltage, it is extremely effective to reduce the power supply voltage in order to reduce the power consumption and prevent the increase in heat generation per unit area due to miniaturization. That's why. However, since the driving ability is lowered simply by lowering the power supply voltage, the driving ability of the low voltage MOS transistor is being improved by shortening the gate and thinning the gate oxide film.

However, in reality, there is a current situation where it is difficult to reduce the power supply voltage of all the LSIs on the printed circuit board. Therefore, it is rare to configure the entire LSI with only MOS transistors having a low power supply voltage. Is often mixed with a 5V power supply type MOS transistor that constitutes an input / output circuit. In the case of such mixed specifications, if the 5V power supply common to the input / output circuit is directly connected to the low power supply voltage MOS transistor, the reliability of the low power supply MOS transistor is serious because the gate oxide film is thin. May have an impact.

Therefore, assuming mixed specifications,
At present, as a measure for preventing the reliability of the gate oxide film from decreasing, a method of increasing the gate oxide film thickness of the entire LSI in a form adapted to an input / output circuit of 5V power supply specification is adopted.

[0005]

However, according to the conventional method of increasing the gate oxide film thickness of the entire LSI according to the input / output circuit and the like, a low power supply voltage specification which constitutes an internal circuit such as a memory cell array is essential. However, the driving capability of the MOS transistor is deteriorated, and the performance of the LSI cannot be improved. However, increasing the gate oxide film thickness only in the input / output circuit not only complicates the process, but also requires processing with the gate oxide film exposed, which results in device yield and
A decrease in reliability cannot be avoided.

The present invention has been made in view of the above circumstances, and a metal insulating film semiconductor device of a low power supply voltage specification in which a circuit having a higher power supply voltage is mixed is also provided. without causing a decrease in yield due to propose a work dividing method of a circuit which simply improve device performance new manufacturing side of the semiconductor device using the same
The purpose is to provide the law .

[0007]

[0008]

[0009]

[0010]

[0011]

[Problems to be Solved by the Invention] Problems of the above-mentioned prior art
In order to solve the above problems and achieve the above-mentioned object, a method of manufacturing a semiconductor device according to the present invention uses a power supply of different sizes.
Includes high-voltage drive circuit and low-voltage drive circuit driven by pressure
A method for manufacturing a semiconductor device, comprising the high voltage drive circuit
To the gate electrode of the field effect type semiconductor element on the side
The process of introducing conductivity type impurities to improve conductivity, and
Part of the impurities of the first conductivity type introduced into
The impurities of the second conductivity type, which is the opposite of the first conductivity type,
Introducing into the gate electrode on the voltage drive circuit side.
Mu.

[0012]

Preferably, the high voltage drive circuit side and the low voltage
When introducing impurities into each gate electrode on the voltage drive circuit side,
At the same time, by introducing the impurities into the semiconductor substrate,
Form a source region and a drain region. to this
As a result, the source region and the drain region can be formed in a self-aligned manner, and the manufacturing process can be simplified.

Preferably, the electric field effect on the low voltage drive circuit side
In order to improve the conductivity of the gate electrode of the semiconductor device
The conductivity type of the impurities to be introduced is the second conductivity type,
The impurity of the second conductivity type is added to the gate on the high voltage drive circuit side.
In the process of introducing into the electrode, at the same time, low voltage driving
Impurity of the second conductivity type is further introduced into the gate electrode on the roadside.
To do . With this configuration, when the impurity opposite to the first introduced impurity is introduced into the high voltage drive circuit side to reduce the conductivity of the gate electrode, the impurity concentration on the low voltage drive circuit side can be increased. This makes it possible to further increase the difference in impurity concentration between the two.

The above manufacturing method is suitable for manufacturing a complementary semiconductor device such as a so-called CMOS. That is, suitable
In addition, the semiconductor device includes the high-voltage drive circuit and the low-voltage drive circuit.
Each voltage drive circuit has n-type or p-type channel
Composed of two types of field effect semiconductor elements
Complementary type semiconductor device comprising the high voltage driving circuit and the low voltage
The driving circuit and the n-type channel field effect semiconductor
Simultaneously introducing n-type impurities into each gate electrode of the conductor element
Of the p-channel field effect semiconductor device
A step of simultaneously introducing a p-type impurity into each gate electrode,
Electric field effect of one conductivity type channel on the high voltage drive circuit side
The gate electrode of the fruit-shaped semiconductor element and the low-voltage drive circuit side
Gate of field-effect semiconductor device of the other conductivity type channel
At the same time, the other conductivity type impurity is introduced into the electrode.
And a step.

[0016]

[0017]

[0018]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Semiconductor devices according to the present invention include MOS memory devices such as DRAM, SRAM and mask ROM, and various MOS logics. Of these, the present embodiment will be described in detail below with reference to the drawings, taking a DRAM as an example.

Although not particularly shown, this DRAM comprises an internal circuit including a memory cell array and a peripheral circuit including an input / output circuit. The internal circuit has, for example, a 3V power supply specification to reduce the power consumption, while the peripheral circuit has another L that is systematized with this DRAM.
Due to the entanglement with SI, the 5V power supply specification is kept and the dual power supply configuration is adopted.

FIG. 1 is a schematic sectional structural view of a MOSFET which constitutes an input / output circuit of a DRAM and to which a bias is applied. In the figure, reference numeral 2 is a MOSF forming an input / output circuit.
It shows ET. In this MOSFET 2, first, on a surface of a semiconductor substrate 4 such as a silicon wafer, an active region 6 is formed which is divided by an element isolation region (LOCOS or the like) not shown. There is no limitation on the conductivity type of the channel of the MOSFET 2, and an n-channel MOSFET (NMOS) is used in this embodiment. Therefore, the active region 6 has a p-type conductivity and is formed by ion-implanting a p-type impurity such as boron (B) at a relatively low concentration. On the other hand, p-channel MOSFET (PMO
In the case of S), this can be formed by reversing all conductivity types including the active region 6.

A gate electrode 10 is formed on the surface of the active region 6 via a gate oxide film 8. Gate electrode 10
The material and the film thickness are not particularly limited, but in the present embodiment, a polysilicon film having a thickness of about 150 nm was formed by the CVD method. Further, the material and the film thickness of the gate oxide film 8 are not particularly limited, and in this embodiment, a very thin silicon oxide film of about 9 nm is formed by the thermal oxidation method. The gate oxide film 8 is made thin in this way because the gate oxide film on the internal circuit side (not shown) is, for example, an MO for charge transfer of the memory cell.
This is because it is necessary to form a thin film to improve the driving capability of the SFET, and in accordance with this, the gate oxide film 8 on the input / output circuit side is also thinned and simultaneously formed to simplify the manufacturing process.

Sidewalls 12 made of, for example, a phosphorus-containing film (PSG) are formed on both side walls of the gate electrode 10, respectively. The sidewalls 12 are formed by coating the PSG film over the entire surface and then etching back by anisotropic etching such as RIE.

On the surface of the active region 6 of the semiconductor substrate 2, from the both end sides of the gate oxide film 8 to the outside of each side wall 12, the active region having a profile peculiar to the FET structure called LDD (Lightly Doped Drain), respectively. (Source region 14 and drain region 16) is the gate electrode 1
0 is formed in a self-aligned manner. The active regions 14 and 16 are formed by performing, for example, ion implantation in two steps before and after the formation of the sidewall 12 by changing the dose amount and energy, and then performing annealing.
As a result, the n ⁺ regions 14b and 16b in which the n-type impurity is dosed at a high concentration are formed deeply in the back of the substrate, and the n ⁻ regions 14a and 16a which are dosed in a relatively low concentration are shallow at the substrate surface side, The gate electrode 10 is formed to extend slightly in the lateral direction toward the center.

When the active regions 14 and 16 are formed, the gate electrode 10 is also doped with a relatively low concentration of impurities of the same ionic species. This impurity introduction is performed to enhance the conductivity of the polysilicon film forming the gate electrode 10, and in this embodiment, it is performed by an ion implantation method using an n-type impurity. The reason why the concentration of introduced impurities in the gate electrode 10 is made relatively low is that the introduced impurities are attracted to the Vss side when a negative voltage Vss is applied to the gate electrode 10 as shown in FIG. This is for depleting the interface side with the oxide film 8 and relaxing the electric field applied to the gate oxide film 8 due to the voltage drop in the depletion layer 10a. The degree of depletion only needs to ensure the reliability of the gate oxide film when the predetermined voltage Vss is applied. From this viewpoint, the concentration of introduced impurities in the gate electrode 10 is determined.

Regarding the method of making the impurity concentration of the gate electrode 10 relatively thin, the gate electrode 1 on the peripheral circuit side is described.
In addition to setting the ion implantation amount to be low only for 0, once the high-concentration impurity is introduced without distinction from the internal circuit, the impurity of the opposite conductivity type is introduced only into the gate electrode 10 on the peripheral circuit side. There is a method of reducing. There is also a method in which the gate electrode on the peripheral circuit side has a polycide structure (a laminated structure of a polysilicon film and a silicide film of a refractory metal), and a specific impurity is absorbed by the refractory metal to reduce the concentration. For example, boron (B) as a p-type impurity
In the combination of and the tungsten silicide film, B can be absorbed by tungsten (W) to reduce the concentration.

The MOSFET 2 thus constructed is
Although not shown in particular, the electrodes are taken out by the metal wiring layer via the interlayer insulating layer and connected to the internal circuit. At this time, as described above, since the peripheral circuit and the internal circuit have different introduced impurity concentrations of the gate electrode 10, it is necessary that this metal wiring layer is made of a material that does not move at least impurities. In the present embodiment, aluminum (Al) is used, which prevents impurities from diffusing into the gate electrode 10 from the internal circuit side and increasing the impurity concentration due to, for example, the thermal history of the subsequent steps.

In addition to this MOSFET2, MI
M capacitors and the like are laminated in a predetermined pattern, and an overcoat layer is formed thereon. In the above description of the DRAM, there are no limitations other than those mentioned in particular, and various modifications can be made within the scope of the present invention.

Next, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings by taking an SRAM as an example. 2 to 6 used here are schematic cross-sectional structural views showing respective manufacturing steps for explaining the manufacturing method of the SRAM, in which the right half of each drawing is compared with the internal circuit and the left half is compared with the input / output circuit. There is. In addition, the SRAM described in the embodiment of this manufacturing method is configured by a complementary MOS (CMOS) in both its internal circuit and input / output circuit.
Each has an NMOS on the left side and a PMOS on the right side.

First, as shown in FIG. 2, a semiconductor substrate 20 such as a silicon wafer is prepared, and wells 22 and 23 having different conductivity are formed on the surface of the semiconductor substrate 20 as active regions of a so-called twin tub structure. , Each formed by, for example, an ion implantation method. Specifically, NM
A p-well 22 made of p-type impurities is formed on the OS side using, for example, a silicon oxide film as a mask, and an n-well 23 made of n-type impurities is similarly formed on the PMOS side at a predetermined distance from the p-well 22.

Next, as shown in the figure, a LOCOS 24 for an element isolation region is formed. In order to form the LOCOS 24, although not shown in the drawing, first, a thermal oxide film for pad and an anti-oxidation film composed of a silicon nitride film are laminated in this order, and the anti-oxidation film is subjected to predetermined patterning. After that, ion implantation for channel stopper and thermal oxidation for LOCOS are performed.

After exposing the surfaces of the active regions 22 and 23, the surface of the semiconductor substrate 20 including the exposed surfaces is oxidized by a thermal oxidation method to form a gate oxide film 26, as shown in FIG. To film. The thermal oxidation conditions are, for example, 850 to
It is wet oxidation at about 1000 ° C. The thermal oxidation for the gate oxide film 26 is performed at the same time for the internal circuit and the input / output circuit, and the film thickness thereof is not particularly limited, but it is preferably thin in order to improve the driving capability of the device.
nm.

Next, an undoped polysilicon film (Non Doped Poly Si) which becomes the gate electrode 28 of FIG.
A film is formed by the D method or the like. This polysilicon film thickness is, for example, about 100 to 300 nm, and in the present embodiment, it is 150.
nm. Then, after patterning this polysilicon film by a photolithography method, etching is performed together with the underlying gate oxide film 26 by, for example, RIE to obtain a gate electrode 28 having a predetermined pattern.

Subsequently, as shown in FIG. 3, an NMOS is formed as a shallow LDD surface region on both ends of the gate electrode 28.
N ⁻ regions 30a and 31a are formed on the side, and p ⁻ regions 32a and 33a are formed on the PMOS side. This is done by using, for example, boron (B) or phosphorus (P) with the gate electrode 28 as a mask.
Is performed by ion implantation. After that, a sidewall film material such as a PSG film is formed on the gate electrode 28 by a CVD method or the like, and the sidewall film material is etched back by anisotropic etching such as RIE. As shown, the sidewall 34 is formed on the side portion of the gate electrode 28.

Next, after the resist 36 is formed on the entire surface, as shown in FIG. 4, only the NMOS regions of the internal circuit and the input / output circuit are opened by using the photolithography method. Then, for example, arsenic (As) is implanted at a relatively high concentration to form n ⁺ regions 30b and 31 as deep LDD regions.
b is formed to complete the source region 30 and drain region 31 for the NMOS. This ion implantation simultaneously introduces impurities into the gate electrode 28 of the NMOS,
It is made n-type conductive. Here, the As implantation conditions are not particularly limited, but in the present embodiment, the energy is 30 ke.
V, dose amount: 5 × 10 ¹⁵ cm ^-2 .

On the other hand, for the PMOS region, p
By implanting a type impurity (for example, B) by ion implantation, impurities are introduced into the deep LDD region and the gate electrode 28. As shown in FIGS. 5 and 6, this ion implantation into the PMOS region is performed in two steps, and each ion implantation is performed using the patterned resist 36 as a mask as in the case of the NMOS described above. Be seen.

As can be seen by comparing FIGS. 5 and 6, the portions where the ion implantation is selectively performed at the first and second times are different. That is, in the first ion implantation, as shown in FIG. 5, relatively low concentration B ions (B ⁺ ) are selectively implanted in the PMOS regions of the internal circuit and the input / output circuit. In this embodiment, the first B ion implantation conditions are energy: 10 keV, dose: 1 × 10 ^15.
It was cm ^-2 . On the other hand, in the second implantation of B ions, as shown in FIG. 6, relatively high concentration B ions (B ⁺⁺ ) are selectively present in the PMOS region of the internal circuit and the NMOS region of the input / output circuit. Be driven into. In this embodiment, the second B ion implantation condition is energy: 10 ke.
V, dose amount: 4 × 10 ¹⁵ cm ⁻² .

By such selective twice ion implantation, the concentration of introduced impurities in the gate electrode 28 is made lower on the input / output circuit side than on the internal circuit side, and CMOS transistors are separately formed. That is, in the PMOS, the input / output circuit side has a relatively low concentration of only the first B ion implantation, whereas the internal circuit side is subjected to the B ion implantation twice and the impurity concentration is set high. Regarding the NMOS, the internal circuit side is regulated by relatively high concentration As ion implantation, whereas the input / output circuit side, by the second B ion implantation of high concentration As ion once introduced, By partially canceling it, the concentration is reduced. These ion implantation conditions are determined from the viewpoints of depletion of the gate electrode 28 described above and the reliability of the gate oxide film 26 thus secured.

After that, although not particularly shown, after activation annealing, each electrode of the FET is led out or connected by a metal wiring layer having a predetermined pattern through an interlayer insulating layer, and finally an overcoat film is formed. And the CM
The OS type SRAM can be completed. The metal wiring layer in this case is also made of a material (for example, A, which does not move impurities between the internal circuit and the input / output circuit), as described above.
l).

In the above description of the SRAM, there are no limitations other than those mentioned in particular, and various modifications can be made within the scope of the present invention. For example, the structure of the gate electrode 28 is not limited to LDD, and the film structure thereof may be polycide. In the above description, the ion species used to form the source regions 30 and 32, the drain regions 31 and 33, and the gate electrode 28 are As and B, but instead of these, phosphorus (P) and boron fluoride (B) are used.
F ₂ ) may be used. Also, the ion implantation conditions are FET
Naturally, it depends on the size and the gate structure, and can be realized by using the energy and dose amount other than the above embodiment.
Further, in the above description, the ion implantation of the p-type impurity is performed twice, but conversely, the method of performing the ion implantation of the n-type impurity twice can also perform the similar circuit division.

[0040]

According to the method of manufacturing a semiconductor device of the present invention, a low power supply voltage circuit whose performance is improved by lowering the drive power supply voltage and thinning the gate oxide film of the device, and, for example, the conventional 5V. When a semiconductor device is formed by mixing a high power supply voltage circuit driven by a power supply, the conductivity of the gate electrode can be reduced only on the high power supply voltage circuit side. As a result, the electric field strength applied to the gate oxide film on the high power supply voltage circuit side is relaxed, and this does not cause reliability deterioration or yield reduction. This means that a thin gate oxide film can be used even on the side of the high power supply voltage circuit, and it is not necessary to change the film thickness of the gate oxide film according to the magnitude of the power supply voltage as in the conventional method. Can be simplified.
Further, since it is not necessary to perform processing while the gate oxide film is exposed as in the conventional case, it is possible to contribute to the improvement of the yield also in this sense.

Further, while the internal circuit achieves high performance and high integration by reducing the power supply voltage and achieving low power consumption, the existing power supply voltage can be used in the peripheral circuit, which facilitates connection with an external system. A semiconductor device can be provided.

[Brief description of drawings]

FIG. 1 is an exemplary semiconductor device according to the present invention, in which a bias is applied to a MOSFET which constitutes an input / output circuit of a DRAM.
It is a schematic sectional structural drawing of FIG.

FIG. 2 is an SR according to a method for manufacturing a semiconductor device according to the present invention.
FIG. 6 is a schematic cross-sectional structural view of one manufacturing process of AM, showing a stage after the formation of the gate oxide film.

FIG. 3 is a schematic cross-sectional structure diagram of one manufacturing process of the SRAM, showing a stage after formation of the sidewalls.

FIG. 4 is a schematic cross-sectional structure diagram of one manufacturing process of the SRAM, showing an introduction stage of an n-type impurity.

FIG. 5 is a schematic cross-sectional structure diagram of one manufacturing process of the SRAM, showing a first introduction stage of p-type impurities.

FIG. 6 is a schematic cross-sectional structure diagram of one manufacturing process of the SRAM, showing a second introduction step of p-type impurities.

[Explanation of symbols]

2 ... MOSFET 4, 20 ... Semiconductor substrate 6 ... Active region 8, 26 ... Gate oxide film 10, 28 ... Gate electrode 12, 34 ... Side wall 22 ... P well 23 ... N well 24 ... LOCOS 30, 32 ... Source region 31 , 33 ... Drain regions 30a, 31a ... N ^- regions 30b, 31b ... N ⁺ regions 32a, 33a ... P ^- regions 32b, 33b ... P ⁺ regions 36 ... Resist

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/8234-21/8238 H01L 27/085-27/092

Claims (4)

(57) [Claims] 1. Driven by power supply voltages of different magnitudes
A method of manufacturing a semiconductor device including a high-voltage driving circuit and a low-voltage driving circuit , wherein a first conductivity type impurity is introduced into a gate electrode of the field-effect semiconductor element on the high-voltage driving circuit side. And a step of increasing conductivity, and an impurity of a second conductivity type opposite to the first conductivity type is removed so as to cancel out a part of the impurities of the first conductivity type that have already been introduced. A method of manufacturing a semiconductor device, the method including: introducing into an electrode. 2. When introducing impurities into the respective gate electrodes on the high voltage drive circuit side and the low voltage drive circuit side, at the same time,
The method of manufacturing a semiconductor device according to claim 1, wherein the source region and the drain region are formed by introducing the impurity into the semiconductor substrate as well. 3. The conductivity type of impurities introduced to the gate electrode of the field effect semiconductor element on the low voltage drive circuit side to enhance conductivity is the second conductivity type, and the second conductivity type. type impurity in the step of introducing into the gate electrode of the high voltage drive circuit side, at the same time, according to claim 1 or 2, further introduced a second conductivity type impurity into the gate electrode of the low voltage drive circuit side Manufacturing method of semiconductor device. Wherein said semiconductor device, each of composed of two types of field effect semiconductor device having an n-type or p-type channel of the high-voltage drive circuit and the low voltage drive circuit
A high-voltage drive circuit and a low-voltage drive circuit, wherein a step of simultaneously introducing an n-type impurity into each gate electrode of the field-effect semiconductor element of the n-type channel, introducing a p-type impurity simultaneously to the gate electrodes of the field effect type semiconductor device of the p-type channel, low the gate electrode of a field effect semiconductor device of the one conductivity type channel of said high voltage drive circuit side At the same time, the other conductivity type impurity is introduced into the gate electrode of the field effect semiconductor element of the other conductivity type channel on the voltage drive circuit side.
The method for manufacturing a semiconductor device according to claim 3, further comprising :