JP3407702B2 - Line width control circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line width control circuit in an electrophotographic printer or the like, and more particularly to a line width control circuit for obtaining a high definition image without increasing the frequency of a transfer clock of an original image.

[0002]

2. Description of the Related Art Conventionally, in order to obtain a high-definition image in a line width control circuit of an electrophotographic printer, the number of divisions of a pixel of interest (a positive integer N A high-frequency transfer clock corresponding to Assuming that N = 16, it is necessary for the line width control unit 3 in FIG. 2 to perform parallel-serial conversion (parallel data load & data shift) with a clock 16 times the clock C0 with respect to the input line width control information S1. there were.

[0003]

However, the speed of electrophotographic printers has recently increased, and some electrophotographic printers have a transfer rate of more than 50 Mhz per pixel. In this case, a clock of 800 Mhz or more is required to perform 16-division line width control by the conventional method. This exceeds the data transfer rate of the current ordinary device, and in the conventional method, there is a dilemma of giving up the speedup or reducing the number of divisions to suppress the high definition. The challenge is to achieve high definition without reducing the number of divisions (N) and without requiring N times as many clocks.

[0004]

In order to solve the above-mentioned problems, the invention of claim 1 is obtained by scanning an original image.
A reference pixel generation unit that outputs a peripheral pixel matrix centered on the target pixel of the binarized image, and a line width that inputs the peripheral pixel matrix and divides the target pixel into N (a positive integer) to narrow the line width. A lookup table for outputting control information; a line width control section for inputting the line width control information and subdividing one pixel to output a line width controlled image signal to an engine for a photographic printer; A controller that supplies a clock and a horizontal synchronization signal to the pixel generation unit and the line width control unit is provided, and the line width control unit is excited by N clocks with a phase difference supplied from the controller. The exclusive OR (EX-OR) of the outputs of the N flip-flop circuits (F / F circuits) is taken, and the output of the N-bit F / F circuit and the N-bit divided data are individually calculated. E Take -OR, feeds back to the F / F circuits.

According to a second aspect of the present invention, the line width control section calculates an initial value of the change point data, which is the first data obtained by dividing the current pixel by N, from the line width control information, and outputs the initial condition. A generation circuit, a bit selection circuit for parallel output of change point data excluding the initial value of the change point data among N divided data of the current pixel from the line width control information, the initial value of the change point data and the An OR circuit for calculating the change point data and outputting the line-width-controlled image signal to the engine.

Further, in the invention of claim 3, the logical sum circuit comprises a data shifter for shifting data and N of the F
/ F circuit, N first EX-OR circuits, and a second EX-O taking an EX-OR of N outputs from the F / F circuit.
R circuit.

Further, in the invention of claim 4, the installation data of the lookup table is not the direct subdivided image of the target pixel but the change point data.

Further, according to the invention of claim 5, the flow control is performed without fixing the start of the pixel by the data shifter, so that the timing control is performed only by resetting the F / F circuit once per line. To do.

Further, in the invention of claim 6, the look-up table is composed of a ROM.

Further, in the invention of claim 7, the data shifter shifts the N change point data by a predetermined bit, and outputs the shift data as shift data.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION A line width control circuit according to the present invention controls an N division line width of a pixel of interest X by using output data of a look-up table in which a pixel of interest is subdivided and expressed using peripheral pixels as reference pixels. It is something to do.

Specifically, the target pixel X of the original image shown in FIG. 7 (a) is processed to generate a smooth recorded image shown in FIG. 7 (b). In order to generate the recorded image, the lookup table 2 shown in FIG. 1 has the a-line × bbit (3 × 3 in the example of FIG. 7) from the reference pixel generation unit 1.
The peripheral pixel matrix S0 of the binarized image of is received and the line width control information S1 of the target pixel X (X in FIG. 7) is output. The line width control unit 3 outputs an image in which the pixel of interest X is subdivided into N bits based on the line width control information S1 to the engine 4 for the photographic printer. Normally, when dividing a pixel into N bits,
It is necessary to shift the data with a transfer clock having a frequency N times higher than that of the original pixel, but this is not necessary in the present invention. (Structure of Embodiment) An example of dividing a pixel into 16 parts will be described below in detail with reference to the drawings. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram of the line width control unit 3, and FIG. 4 is an operation timing chart of the line width control unit 3.

In FIG. 1, the controller 5 transfers the horizontal synchronizing signal H2 input from the engine 4 to the transfer clock C.
It is synchronized with LK and output as a horizontal synchronization signal H1.

The operation of the controller 5 will be described below.

Here, when the horizontal synchronizing signal H2 is synchronized with the transfer clock (that is, the original oscillation clock CLK0) of continuous pixels, the horizontal synchronizing signal H1 has a maximum jitter (fluctuation) of one pixel in the horizontal direction. Occurs. In order to suppress this jitter, synchronization is normally performed with a clock having a higher frequency than the original oscillation clock CLK0. Here, 16 pixels
Since it is divided, the frequency multiplication rate is set to 16. That is, the original clock CLK0 is multiplied by 16 to utilize the 16-multiplied clock CLK16,
Clocks C0 to C15 whose phases are shifted by 1/16 are generated by the multiplied clock CLK16. Clock C0
The relationship of ~ C15 is expressed in FIG.

The transfer clock CLK is synchronized with the input horizontal synchronizing signal H2 for each line by using the clocks C0 to C15. Specifically, the horizontal synchronizing signal H
After the reference point of 1 (rising or falling),
For example, among the clocks C0 to C15, one of the first incoming clocks C0 to C15 is selected and output as the reference clock. As a result, the horizontal synchronizing signal H1 is output with a jitter of 1/16 pixel accuracy with respect to the horizontal synchronizing signal H2.

Data selection signals SEL0 to SEL3 are also provided.
Are clocks C0 to C based on the value of the data selection signal SEL.
This is a signal for selecting 15 and is output to the line width control unit 3.

The reference pixel generator 1 transfers a binary image of white (0) and black (1) obtained by scanning an original image to a transfer clock C.
In accordance with LK and the horizontal synchronizing signal H1, a peripheral pixel matrix S0 of a line × bbit centered on the target pixel X
Output as. (In the example of FIG. 7, it is 3 × 3 9-bit data.) The lookup table 2 inputs the peripheral pixel matrix S0 and outputs the line width control information S1 of the target pixel X, It is usually composed of a ROM.

The line width control information S1 is information for dividing the pixel of interest X into N to narrow the line width, and has the data format shown in FIG. 8 (a). 8B to 8E are explanatory diagrams of FIG. 8A. Hereinafter, description will be made assuming that N = 16.

In FIG. 8A, 4 bits of bits b7 to b4 are black edges "B", which are change point addresses where black starts in one pixel. 4 bits of bits b3 to b0 are a white edge “W”, which is a change point address where white starts in one pixel.

In FIG. 8B, B = “4”, W =
It is "Ah". When B <W, the pixel of interest X starts white, the addresses “4” to “9” are black, and “Ah” is displayed.
Therefore, “Fh” becomes white.

In FIG. 8C, B = “Bh”, W =
It is "3". When B> W, the target pixel X starts from black, the addresses “3” to “Ah” are white, and “Bh”.
"Fh" becomes black.

FIGS. 8 (d) and 8 (e) show the case where the pixel of interest X is all black or all white, in which case "B" = "W".
Becomes The bit b7 (= b
Perform with the value of 4).

The line width control section 3 receives the line width control information S1 and outputs to the engine 4 an image obtained by subdividing one pixel as shown in FIGS. 8 (b) to 8 (e). As shown in FIG. 2, it comprises an initial condition generation circuit 31, a bit selection circuit 32, and an OR circuit 33. The configuration of the line width control unit 3 will be described in more detail.

The initial condition generating circuit 31 calculates the initial pixel data D0 which is the initial value (first data of 16 divisions) of the current pixel from the line width control information S1 which is the input from the lookup table 2 and outputs it. To do. 8 (a)-
The condition that the initial pixel data D0 becomes black from (e) is as follows.

{B> W ≠ 0} or {(B = W) & b7 = 1} or {B = 0 ≠ W} ... Also, the change point data D15 ′ (of the previous pixel is the final value of the previous pixel The signs and the like are represented by adding '.) The condition that the color is black is {B' = W '} or {(B' = W ') & b7 = 1} ..., and B'and W'are This is a pixel change point address.

The initial pixel data D0 is the change point data from the final value of the previous pixel to the initial value of the current pixel, and D0 = EX-OR.

The bit selection circuit 32 receives the line width control information S1 and, based on FIG. 8, outputs the change point data D1 to D15 of the 16-divided data of the current pixel in parallel (here,
(Except initial pixel data D0 which is an initial value). Specifically, the bit selection circuit 32 is composed of two decoders (not shown) and activates only two signal lines designated by B and W (that is, sets them to 1). However, when B = W, all are not activated (that is, set to 0). In the example of FIG. 8B, only the shift data DT4 and DT10 are 1,
Other shift data is 0.

As shown in FIG. 3, the OR circuit 33 shifts and outputs the initial pixel data D0 and the change point data D1 to D15 as shift data DT0 to DT15 by the data selection signals SEL0 to SEL3.
31 and 16 F / F circuits 333 which receive clocks C0 to C15 having a phase difference as clock inputs, and F / F circuits 3
33 F / F outputs F0 to F15 exclusive OR (EX-
EX-OR circuit 334 (second EX-OR)
Circuit) and the F / F outputs F0 to F15 of the F / F circuit 333.
And 16 pieces of EX-OR circuits 332 (first EX-OR circuits) whose shift data DT0 to DT15 are individually input signals and whose outputs are input to the F / F circuit 333. (Operation of Embodiment) Next, the operation of the embodiment of the present invention will be described.

When the reference pixel generator 1 outputs the peripheral pixel matrix S0 shown in FIG. 7A, the look-up table 2 constituted by the ROM outputs S1 = 80h as the line width control information S1. This is B = 8, W = 0
8F is expected as the image signal S2 in which the line width of the target pixel X is controlled for the engine 4.

In the line width control section 3 of FIG. 2, the initial condition generating circuit 31 receives S1 = 80h as the line width control information S1 and outputs D0 = 0 as the initial pixel data D0. (Here, assuming that the final value of the previous pixel is white,
Since S1 = 80h does not satisfy the logic of the previous item, the initial pixel data D0 becomes 0. The bit selection circuit 32 uses S1 = as the line width control information S1.
80h is received, 1 is output only for the change point data D8,
Others are set to 0 (D0 is not output).

The operation of the OR circuit 33 is as follows.

The data shifter 331 has a data selection signal S.
Initial pixel data D0 and change point data D1 to D15 according to the values of EL0 to SEL3 (= SEL: data selection signal)
Are shifted and output as shift data DT0 to DT15. For example, the data selection signal SEL is SEL = 6h
At this time, the clock C6 is selected as the reference clock. That is, one pixel starts at the clock C6, becomes the clocks C7, C8 to C15, C0, and C1 to C4, and is terminated at the clock C5.

At this time, the data shifter 331 shifts the initial pixel data D0 and the change point data D1 to D15 by 6 bits. That is, the initial pixel data D0, the change point data D1 to D15, and the shift data DT0 to DT15 correspond as follows, respectively.

D0 → DT6, D1 → DT7, D2 → DT
8 ... D9 → DT15, D10 → DT0, D11 → D
T1 ... D15 → DT5.

The F / F circuit 333-0 receives the shift data D
The EX-OR circuit 332-0 takes the exclusive OR of T0 and the F / F output F0, and uses this as the data input, and the clock C
0 is used as the clock input. F / F circuits 333-1 to 33
Reference numeral 3-15 is an EX-OR circuit 332-for the exclusive OR of the shift data DT1 to DT15 and the F / F outputs F1 to F15.
1 to 332-15, which are used as data inputs, and clocks C1 to C1 delayed by 1/16 phase from the clock C0.
C15 is used as a clock input.

Further, the data selection signal SEL is SEL = 6
Therefore, the initial pixel data D is stored in the F / F circuit 333-6.
0 is shifted in, and the F / F circuit 333-6 (corresponding to the clock C6) becomes the reference (initial bit) of the processing pixel (current pixel).

FIG. 6 is a timing chart of the OR circuit 33. Controller 5 at the beginning of the line
F / F circuit 333-0-3 by the reset signal from
33-15 is cleared and F / F outputs F0 to F15 are 0.
Has become. Here, since the change point data of the first pixel is 1 only in the change point data D8, the shift data DT14 becomes DT14 = 1 by the data shifter 331 (other DTs are 0). Since the clock that first arrives is the clock C6 and the shift data DT is DT = 0, the F / F output F6 of the F / F circuit 333-6 is F6 =
It is 0.

Since the F / F output 6 is also 0 at that time, the output of the EX-OR circuit 334, that is, the line width-controlled image signal S2 of the OR circuit 33 becomes 0 (EX-
The OR circuit outputs 1 when the number of input 1 is odd). Since the shift data DT7 is also 0, the F / F output F7 becomes F7 = 0 according to the next clock C7, and the line width-controlled image signal S2 does not change (that is, 0 output). Similarly, F / F circuits 333-8 to 333
-13 are sequentially driven by the clocks C8 to C13, the F / F outputs F8 to F13 all output 0, and the line width controlled image signal S2 does not change.

Next, when the clock C14 arrives, the shift data DT14 is DT14 = 1. Therefore, the F / F output F14 is F14 = 1, and the line width controlled image signal S2 is 1. Shift data DT15, DT0
Since DT5 is 0, the line width controlled image signal S2 continues to output 1 without change after the clock C14.

By the above operation, the line width controlled image signal S2 of the logical sum circuit 33 outputs the pattern of FIG. 6, which is the same as the expected pattern of FIG. 8 (f). .

Next, when it is desired to output the same data as the second pixel, the same data (the line width control information S1 is S1 =
80h) is output. This means that B = 8 and W = 0, and the output data of the target pixel X to the engine 4 is expected to be as shown in FIG.

Now, as the output result of the first pixel, the output of the F / F circuit 333 is 1 only for the F / F output F14, and 0 for the others. On the other hand, as the change point data of the second pixel, the change point data D8 is D8 = 1 as in the first pixel, and the initial pixel data D0 is D0 = 1. (Because the final data of the previous pixel is black = 1, the initial condition generating circuit 31 outputs'change = 1 ') As a result of the data shifter 331, the shift data DT6, DT
Only 14 is 1.

In the second pixel as well, the clock that first arrives is the clock C6, and the shift data DT6 is the exclusive OR of DT6 = 1 and F6 = 0 of the F / F output F6 to obtain F
The / F circuit 333-6 outputs 1. Already F / F output F
Since 14 has F14 = 1, the final line width controlled image signal S2 has S2 = 0, and white is output. (1
2 is an even number, the EX-OR circuit 334 outputs 0. ) Hereinafter, until clock C13, F / F circuits 333-7 to 333-3
33-14 outputs 0, and the line width controlled image signal S2
Keeps outputting 0. When the clock C14 arrives, the exclusive OR of the shift data DT14 = 1 and the F / F output F14 = 1 is obtained, and F14 = 0. At this point, F / F
Since the number of outputs is 1 (only F / F output F6), the line width controlled image signal S2 is S2 = 1.

From clock C15 to clock C5, F
The value of / F output remains 0, and as a result, the image signal S2 whose line width is controlled does not change.

By the above operation, the engine 4 receives the pattern of FIG. 8 (f) as the image signal S2 whose line width is controlled for both the first pixel and the second pixel, and as shown in FIG. 7 (b).
It is possible to obtain a smooth recorded image in which black is inserted at the right end of the pixel of interest X.

[0047]

As described above, according to the present invention, the divided data is sequentially transferred by the clocks whose phases are shifted without performing parallel / serial conversion, and the result is transferred to the combinational circuit (EX-OR circuit). By outputting after that, without increasing the frequency of the transfer clock of the original image,
This has the effect of obtaining a recorded image with high-definition dot accuracy.

Further, by controlling the flow without fixing the start of the pixel by the data shifter, it is only necessary to reset the F / F circuit once for each line, and the timing control can be facilitated. . On the other hand, when the start of the pixel is fixed without data shift, that is, when the clock C0 is used as the pixel start, the reset signal is input for each pixel, which makes timing control difficult, and as a result, It becomes an obstacle to speeding up.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram of a line width control unit 3.

FIG. 3 is a block diagram of an OR circuit 33.

FIG. 4 is an operation timing chart of the line width control unit 3.

FIG. 5 is a relationship diagram of clocks C0 to C15.

FIG. 6 is a timing chart of an OR circuit 33.

FIG. 7 is an image of a pixel of interest.

FIG. 8A is a data format of the line width control information S1,
(B) to (e) are patterns of the line-width-controlled image signal S2 to the engine, and (f) is a pattern of the line-width-controlled image signal S2.

[Explanation of symbols]

1 Reference pixel generator 2 lookup table 3 Line width control section 4 engine 5 controller 31 initial condition generation circuit 32-bit selection circuit 33 OR circuit 331 data shifter 332 EX-OR circuit 333 F / F circuit 334 EX-OR circuit

─────────────────────────────────────────────────── ─── Continued Front Page (58) Fields surveyed (Int.Cl. ⁷ , DB name) B41J 2/44 B41J 2/485 H04N 1/23-1/31

Claims (7)

(57) [Claims] 1. A reference pixel generation unit for outputting a peripheral pixel matrix centering on a target pixel of a binarized image obtained by scanning an original image; and inputting the peripheral pixel matrix to set the target pixel to N ( (A positive integer) A look-up table that outputs line width control information for dividing the line width to narrow the line width, and a photo printer for inputting the line width control information and subdividing one pixel into line width controlled image signals. And a controller for supplying a clock and a horizontal synchronizing signal to the reference pixel generation unit and the line width control unit. The line width control unit supplies the clock and the horizontal synchronization signal to the reference pixel generation unit and the line width control unit. N excited by N clocks with phase difference
The exclusive OR (EX-OR) of the outputs of the flip-flop circuits (F / F circuits) is taken, and the EX of the output of the N-bit F / F circuit and the divided data of N bits are individually EX. A line width control circuit, which takes an OR and is fed back to the F / F circuit. 2. An initial condition generation circuit for calculating and outputting an initial value of change point data, which is the first data obtained by dividing the current pixel by N, from the line width control information, and the line width control section. A bit selection circuit for parallel-outputting the change point data excluding the initial value of the change point data among the N divided data of the current pixel from the control information, and the initial value of the change point data and the change point data are calculated. 2. The line width control circuit according to claim 1, further comprising a logical sum circuit for outputting the line width controlled image signal to the engine. 3. The OR circuit comprises a data shifter for shifting data, N F / F circuits, and N first E circuits.
EX of N outputs from the X-OR circuit and the F / F circuit
3. The line width control circuit according to claim 2, further comprising a second EX-OR circuit that takes an OR. 4. The change point data is used as the installation data of the look-up table, not as the direct subdivided image of the pixel of interest.
The described line width control circuit. 5. The timing control is performed by resetting the F / F circuit only once per line by controlling the flow of the pixel without fixing the start of the pixel by the data shifter. Item 3. The line width control circuit according to item 3. 6. The line width control circuit according to claim 1, wherein the look-up table is composed of a ROM. 7. The line width control circuit according to claim 3, wherein the data shifter shifts the N change point data by a predetermined bit and outputs the shift data as shift data.