JP3580248B2 - Image forming circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a line width control technique of an electrophotographic printer, in particular, it relates to an image forming circuit for controlling the line width of the printed image.
[0002]
[Prior art]
Conventionally, in an electrophotographic printer, a line width control circuit that performs line width control based on division line width information of a target pixel from a look-up table that subdivides the target pixel, using peripheral pixels of the target pixel as reference pixels, As the number of divisions increases, a higher definition image can be obtained. However, it is necessary to read line width information from a look-up table with a transfer clock having a frequency corresponding to the number of divisions of a target pixel. That is, in order to obtain a high-definition image, a high-frequency transfer clock corresponding to the number of divisions of the target pixel is required for the line width control information from the lookup table (Japanese Patent Laid-Open No. 2000-134434). reference). For example, when the target pixel is divided into 16, it is necessary to perform parallel-serial conversion (parallel data load & data shift) on the input line width control information with a clock 16 times the transfer clock.
[0003]
Recently, the speed of electrophotographic printers has been increasing, and some printers have a transfer rate of more than 50 MHz per pixel. In this case, a clock of 800 MHz or more is required to perform the 16-division line width control by the conventional method. However, such a high-frequency transfer clock exceeds the data transfer rate of the current ordinary device, and therefore, in a conventional line width control circuit using a look-up table, the speed-up is not performed or the division is not performed. Either reduced the number or suppressed the high definition.
[0004]
As an image forming circuit that improves dot accuracy without increasing the transfer clock frequency, the inventor of the present application disclosed in Japanese Patent Application No. 10-302269 (Japanese Patent Application Laid-Open No. 2000-134434) a white image obtained by scanning an original image. The binary image of 0) and black (1) is defined as an a-line x b-bit peripheral pixel matrix centered on the pixel of interest (see X in FIG. 7A) according to the transfer clock and the horizontal synchronization signal. A reference pixel generation unit to be output and a line width control information of a pixel of interest by inputting a peripheral pixel matrix (information for dividing the pixel of interest into N to reduce the line width, and indicates a change point address starting with black in one pixel A lookup table that outputs a black edge and a white edge that indicates a transition point address starting with white in one pixel), and receives a line width control information as an input, and outputs a 1 to the engine. In an image forming circuit including a line width control unit that outputs a subdivided image, a reference pixel generation unit, and a controller that controls an operation of the line width control unit, a target pixel read from a lookup table is subdivided. Generated image data using the same number of time-division clocks as the number of divisions N enables the frequency of the transfer clock of the original image to be low regardless of the number of divisions. There has been proposed a circuit and a method capable of obtaining a recorded image with high definition of dot accuracy without increasing the frequency according to the number of divisions.
[0005]
[Problems to be solved by the invention]
As a result of intensive studies, the inventor of the present application has come up with an image forming apparatus and an image forming method capable of expressing a more varied image than when only the edge mode is used.
[0006]
That is, the problem to be solved by the present invention is to improve the dot accuracy without increasing the transfer clock frequency, and to provide an image forming apparatus and an image forming apparatus capable of expressing an image with more changes than when only the edge mode is used. An object of the present invention is to provide an electrophotographic printer including an image forming apparatus.
[0007]
[Means for Solving the Problems]
According to the present invention to solve the above-described problems, the line width control unit performs N-division line width control of a target pixel by using output data of a look-up table in which a target pixel is subdivided and input, using peripheral pixels as reference pixels. It is. The present invention outputs a reference pixel generation unit that outputs a peripheral pixel matrix centering on a target pixel, and outputs line width control information that subdivides and expresses the target pixel with a predetermined division number using the peripheral pixel matrix as a reference pixel. A lookup table, a line width control unit that generates data obtained by subdividing the pixel of interest based on the line width control information using the same number of time-division clocks as the number of divisions, the reference pixel generation unit, A controller that controls the operation of a line width control unit.In the image forming apparatus, as the line width control information of the look-up table, in addition to edge information indicating a change point address in the pixel of interest, It has pattern information consisting of subdivided image data.
[0008]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention will be described below. The present invention performs N-division line width control of a target pixel by using peripheral pixels as reference pixels and inputting output data of a lookup table in which the target pixel is subdivided. More specifically, the pixel of interest X (70) of the original image shown in FIG. 7A is processed to generate a smooth recorded image as shown in FIG. 7B.
[0009]
In order to generate the recorded image, the lookup table 2 shown in FIG. 1 converts the matrix S0 of the binary image of a line × b bits (3 × 3 in the example of FIG. 7) from the reference pixel generation unit 1. It receives and outputs the line width control information S1 of the pixel of interest (70 in FIG. 7).
[0010]
The line width control unit 3 outputs to the electrophotographic printer engine 4 an image S2 obtained by subdividing the pixel of interest into N bits based on the line width control information S1.
[0011]
According to the present invention, in the lookup table 2, pattern information (pattern mode) of a target pixel is prepared as line width control information S1 in addition to change point address information (edge mode) in the target pixel. It is possible to cope with more image changes than in the case of only the mode.
[0012]
【Example】
In order to describe the above-described embodiment of the present invention in more detail, an embodiment of the present invention will be described with reference to the drawings. In the following embodiments, description will be made on the basis of an example in which a pixel is divided into 16, but the present invention is not limited to such a configuration. FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of the line width control unit 3 according to one embodiment of the present invention. FIG. 3 is a block diagram showing a configuration of an OR circuit of the line width control unit 3 according to one embodiment of the present invention. FIG. 4 is a timing chart for explaining the operation of the line width control unit 3 in one embodiment of the present invention.
[0013]
Referring to FIG. 1, a reference pixel generation unit 1, a look-up table 2, a line width control unit 3, an electronic printer engine (abbreviated simply as "engine") 4, and a controller 5 are provided. .
[0014]
The controller 5 synchronizes the horizontal synchronization signal H2 input from the engine 4 with the transfer clock CLK, as shown in FIG. 4, and outputs the same to the reference pixel generation unit 1 as H1. The operation of the controller 5 according to one embodiment of the present invention will be described. When the controller 5 synchronizes the horizontal synchronizing signal H2 with a continuous pixel transfer clock (original clock CLK0), a horizontal fluctuation (jitter) of one pixel at maximum occurs in H1.
[0015]
Usually, in order to suppress jitter, synchronization is performed by a clock (multiplied clock) having a higher frequency than the original clock CLK0. Here, since the pixel is divided into 16, the frequency multiplication factor is set to 16 times.
[0016]
In other words, the controller 5 uses the clock CLK16 obtained by multiplying the original clock CLK0 by 16 using a multiplication circuit (not shown), and shifts the phase of CLK0 by 1/16 by CLK16 to the time division clocks C0 to C15 (“multiple clocks”). Phase clock). The time-division clocks C0 to C15 are as shown in FIG. 5 and have the same period, C0 is the original clock CLK0, and the transition edge of the clocks C0 to C15 is the period (1 A phase difference is provided for each period obtained by dividing the clock cycle (16).
[0017]
The transfer clock CLK is synchronized with the input horizontal synchronization signal H2 for each line using clocks C0 to C15. Specifically, after the reference point (rising or falling) of H1 For example, the first clock (in C0 to C15) is selected and output as a reference clock.
[0018]
As a result, H1 is output with a 1/16 pixel accuracy jitter with respect to H2.
[0019]
The 4-bit control signals SEL0 to SEL3 output from the controller 5 to the line width control unit 3 are selection signals for selecting C0 to C15.
[0020]
The reference pixel generation unit 1 converts a binary image of white (0) and black (1) obtained by scanning the original image into a data centered on the target pixel X according to the transfer clock C0 and the horizontal synchronization signal H1. It is output as a line × b-bit matrix S0. In the example shown in FIG. 7, the data is 3 × 3 9-bit data.
[0021]
The look-up table 2 receives the peripheral pixel matrix S0 and outputs the line width control information S1 of the target pixel X, and is usually configured by a ROM (read only memory).
[0022]
In one embodiment of the present invention, the line width control information S1 is control information for dividing the target pixel X into N parts to reduce the line width, and has two types of information, an edge mode and a pattern mode.
[0023]
First, the edge mode will be described. The edge mode has the data format shown in FIG. The data width is 8 bits. 8B to 8E are explanatory diagrams of FIG. 8A. Hereinafter, description will be made on the assumption that N = 16.
[0024]
In FIG. 8A, four bits b7 to b4 (upper bits) are black edges “B” indicating a transition point address where black starts in one pixel, and four bits b3 to b0 (lower bits) are A white edge “W” indicating a transition point address where white starts in one pixel.
[0025]
In FIG. 8B, the black edge B = “4” and the white edge W = “Ah” (where h is hexadecimal). When B <W, the target pixel X starts with white, addresses “4” to “9” are black, and addresses “Ah” to “Fh” are white.
[0026]
In FIG. 8C, the black edge B = “Bh” and the white edge W = “3”. When B> W, the target pixel X starts with black, addresses “3” to “Ah” are white, and addresses “Bh” to “Fh” are black.
[0027]
FIG. 8D shows the case where the target pixel X is all black, and FIG. 8E shows the case where the target pixel X is all white . The distinction between the white and black levels is made by the value of b7 (= b4).
[0028]
Next, the pattern mode will be described. The pattern mode has the data format shown in FIG. The data width is 8 bits. 9 (b) to 9 (e) are explanatory diagrams of FIG. 9 (a).
[0029]
The pattern mode is the monochrome information itself in the target pixel, and N = 8. That is, b7 is the head (left end of the pixel divided into eight), and hereinafter b6 and b5, and b0 means the right end color of the pixel.
[0030]
The line width control unit 3 receives the line width control information S1 from the look-up table 2 and inputs to the engine 4 an image obtained by subdividing one pixel as shown in FIGS. 8B to 8E. Is output.
[0031]
The configuration of the line width control unit 3 according to one embodiment of the present invention will be described with reference to FIG. As shown in FIG. 2, the line width control unit 3 includes an initial condition generation circuit 31, a bit selection circuit 32, an OR circuit 33, a bit conversion circuit 34, and a selector 35.
[0032]
In the edge mode, the initial condition generation circuit 31 receives the line width control information S1 from the look-up table 2 as an input, calculates an initial value (first data of 16 divisions) D0 of the current pixel, and outputs it.
[0033]
From FIG. 8A to FIG. 8E, the conditions under which D0 becomes black are as follows.
[0034]
｛B> W ≠ 0｝ or ｛(B = W) & b7 = 1｝ or ｛B = 0 ≠ W｝ ▲▲ 1 ▼
[0035]
The condition that the final value D15 ′ of the previous pixel becomes black is as follows.
｛B '= W'｝… (2)
(However, B 'and W' are change point addresses of the previous pixel)
[0036]
D0 is change point information from the last value of the previous pixel to the initial value of the current pixel,
D0 = (1) EX-OR (2)… (3)
It becomes.
[0037]
The bit selection circuit 32 receives the line width control information S1 and outputs in parallel bit data D1 to D15 forming transition point information of the 16-part data of the current pixel according to FIG. 8 (excluding the initial value D0). The bit selection circuit 32 is specifically composed of two decoders (not shown), and activates only two signal lines designated by a black edge “B” and a white edge “W” (to 1). Do). However, when B = W, all are not activated (set to 0). That is, in the example shown in FIG. 8B, of the bit data D1 to D15, only D4 and D10 are 1 and the others are 0.
[0038]
In the pattern mode, the bit conversion circuit 34 receives the line width control information S1, and outputs in parallel the change point information d0 to d7 of the 8-pixel data of the current pixel according to FIG. Specifically, the bit conversion circuit 34 outputs the EX-OR of the adjacent 2-bit data. That is,
The EX-OR (exclusive OR) of b7 and b6 is d1,
The EX-OR of b6 and b5 is d2, ...,
The EX-OR of b1 and b0 is d7,
Is output as
[0039]
The fact that the initial value d0 is change point information from the last value of the previous pixel to the initial value of the current pixel is the same as in the edge mode.
[0040]
In the example shown in FIG. 9C, d1, d2, d6, and d7 are 1, and others are 0 (d0 is determined by the relationship with the previous pixel, but is set to 0 for convenience of explanation).
[0041]
Actually, d0 to d7 are expanded into 16 bits in order to match the edge mode with the number of bits. That is, as shown in FIG. 9D, d0 to d7 are expanded into even bits D0 to D15, and 0 is inserted into the odd bits and output.
[0042]
The selector 35 determines the output data D0 to D15 of the initial condition generation circuit 31 and the bit selection circuit 32 in the edge mode and the outputs D0 to D15 of the bit conversion circuit in the pattern mode based on the selection control signal (EDGE / PTN). Select output.
[0043]
The OR circuit 33, as shown in FIG. 3, includes a data shifter 333 that shifts and outputs 16 pieces of bit data D0 to D15 input in parallel as DT0 to D15 by a 4-bit data selection signal SEL0 to SEL3. 16 D-type flip-flops 331 (F / F0 to F / F15) which receive time-division clocks C0 to C15 having phase differences as clock inputs, and outputs F0 to F15 of 16 flip-flops F / F0 to F / F15 The EX-OR 332 which takes the exclusive OR of the D-type flip-flops F / F0 to F / F15 and the output of the D-type flip-flop F / F and DT0 to DT15 are individually input signals. , And 16 EX-ORs 334 each having the output as the D input of each flip-flop F / F. The EX-OR 332 outputs 1 when the number of input 1s is odd.
[0044]
The operation in the edge mode according to the embodiment of the present invention will be described. When the image matrix shown in FIG. 7A is output from the reference pixel generation unit 1, the lookup table 2 (ROM) outputs S1 = 80h as data. This means that the black edge B = 8 and the white edge W = 0, and the output data of the target pixel to the engine 4 is expected to be as shown in FIG.
[0045]
In the line width control unit 3, the initial condition generation circuit 31 receives S1 = 80h and outputs D0 = 0.
[0046]
Assuming that the last value of the previous pixel is white, "80h" does not satisfy the logic of the above item (3), so the bit selection circuit 32 receives the line width control information S1 = 80h and outputs 1 only in D8. , D1 to D7 and D9 to D15 are set to 0 (however, D0 is not output).
[0047]
The selector 35 outputs the output D0 = 0 of the initial condition generation circuit 31 and the outputs D1 to D15 of the bit selection circuit 32 (1 only for D8, 0 otherwise) to the OR circuit 33.
[0048]
The operation of the OR circuit 33 is as follows.
[0049]
The data shifter 333 shifts the input data D0 to D15 according to the values of SEL0 to SEL3 and outputs the data as DT0 to DT15. For example, when SEL = 6h, C6 is selected from the time-division clocks C0 to C15 as the reference clock. That is, one pixel starts at C6, becomes C7, C8,... C15, C0, and ends at C5.
[0050]
At this time, the data shift motor 333, D0 to D15 and are shifted by 6 bits, and outputs it as DT0～DT15. That is, D0 to D15 and DT0 to DT15 correspond as follows.
[0051]
D0 → DT6, D1 → DT7, D2 → DT8,..., D9 → DT15, D10 → DT0, D11 → DT1,.
[0052]
The flip-flop F / F0 inputs the output of DT0 and the EX-OR 334 which receives its own output F0 to the data input terminal D, inputs the clock C0 to the clock input terminal, and inputs the data at the rising edge of the clock C0. The input data at the end D is sampled and output.
[0053]
The flip-flops F / F1 to F15 input the data DT1 to DT15 and the output of the EX-OR 334 which receives the output of the flip-flops F / F1 to DT15 to the data input terminal D, and delay the clocks C1 to C1 delayed from C0 by 1/16 phase. 15 is input to the clock input terminal, and the input data of the data input terminal D is sampled and output at the rise of C1 to C15.
[0054]
Since the selection signal SEL is “6h”, the flip-flop F / F6 of the logic sum circuit 33 receives a signal obtained by shifting D0 by 6 bits using the data shifter 333, and the F / F6 (corresponding to C6) is processed. It becomes a reference (initial bit) of the pixel (current pixel).
[0055]
FIG. 6 is a timing chart for explaining the operation of the OR circuit 33. At the head of the line, the 16 flip-flops F / F0 to F / F15 are cleared by the reset signal from the controller 5, and the outputs F0 to F15 = 0 of the 16 flip-flops. Each flip-flop 331 is a D-type flip-flop with a reset function.
[0056]
Here, the change point information of the first pixel is 1 only in the data D8, so that DT14 is 1 in the shift output of the data shifter 333 (other DT0 to D13 and D15 are 0).
[0057]
The clock that arrives first is C6 and the data DT6 = 0, so the output F6 = 0 of the flip-flop F / F6. At that time, the outputs of the other flip-flops are also 0, and the output of the EX-OR 332, that is, the output S2 of the OR circuit 33 (the image obtained by subdividing the pixel of interest) is 0.
[0058]
Since the data DT7 is also 0, the output F7 of the flip-flop F / F7 becomes 0 by the next incoming clock C7, and S2 remains at 0.
[0059]
Similarly, flip-flops F / F8 to F / F13 are sequentially driven by clocks C8 to C13, output data DT8 to DT13 (all 0), and S2 does not change.
[0060]
Next, when the clock C14 arrives, since DT14 = 1, the output F14 of the F / F14 becomes 1, and S2 becomes 1. Since DT15 and DT0 to DT5 = 0, S2 does not change after the clock C14 and continues to output 1.
[0061]
By the above operation, the output S2 of the OR circuit 33 outputs a pattern as shown in FIG. 6, which is the same as the expected pattern of FIG. 8 (f).
[0062]
Next, when it is desired to output the same data as the second pixel, the look-up table 2 (ROM) outputs the same data (S1 = 80h).
[0063]
This means that the black edge B = 8 and the white edge W = 0, and the output data of the pixel of interest with respect to the engine 4 is expected to be as shown in FIG.
[0064]
Now, as an output result of the first pixel, the output of the flip-flop 331 of the OR circuit 33 is 1 only for the flip-flop F14 and 0 for the other.
[0065]
On the other hand, as the change point information of the second pixel, D8 = 1 and D0 = 1 as in the first pixel. Since the final data of the previous pixel is black = 1, the initial condition generation circuit 31 outputs “changed” = 1 as the initial value D0.
[0066]
As a shift result in the data shifter 333, only DT6 and DT14 obtained by shifting D0 and D8 by 6 bits become 1.
[0067]
In the second pixel as well, the clock that first arrives is C6, and the exclusive OR of DT6 = 1 and the output F6 = 0 of the flip-flop F / F6 is obtained, and the flip-flop F / F6 outputs 1. . Since the output F14 of the flip-flop F / F14 has already been 1, the number of 1s becomes two, the EX-OR 332 outputs 0, the final output S2 becomes 0, and white is output.
[0068]
Hereinafter, until the clock C13, the flip-flops F / F7 to F / F14 output 0, and S2 keeps outputting 0.
[0069]
When the clock C14 arrives, EX-OR of the output DT14 = 1 of the data shifter 333 and the output F14 = 1 of the flip-flop F / F14 is obtained, and the output F14 of the flip-flop F / F14 becomes 0. At this point, one of the outputs F0 to F15 of the flip-flop 334 outputs 1 (only F6), so that S2 = 1.
[0070]
From the clock C15 to the clock C5, the value of the flip-flop 331 remains 0, and as a result, S2 does not change.
[0071]
With the above operation, the engine 4 receives the pattern of FIG. 8F as S2 for both the first pixel and the second pixel, and inserts black at the right end of the target pixel X as shown in FIG. To obtain a good recorded image.
[0072]
In the edge mode, the change point address is described, so that the image data of the target pixel changes up to two times. Therefore, in the edge mode, a more complicated change of the image data cannot be realized.
[0073]
On the other hand, in the pattern mode, as shown in FIG. 9A, since the image data itself is expressed, an image with many changes can be expressed.
[0074]
Next, the operation of the embodiment (pattern mode) of the present invention will be described with reference to FIG.
[0075]
In the pattern mode, the bit conversion circuit 34 receives the line width control information S1 and outputs in parallel the change point information d0 to d7 of the 8-part data of the current pixel according to FIG. Specifically, this circuit outputs an exclusive OR (EX-OR) of adjacent 2-bit data. That is, (01100011) is output (FIG. 9C). The initial value d0 is change point information from the last value of the previous pixel to the initial value of the current pixel, and is set to 0 here.
[0076]
Further, in order to match the edge mode with the number of bits, d0 to d7 are expanded to 16 bits. That is, as shown in FIG. 9D, d0 to d7 are developed into even bits of D0 to D15 (d0 is D0 and D1, d1 is D2 and D3,...), And 0 is inserted in the odd bits. , D0 to D15. As a result, the following data is output as S2.
[0077]
001010000000001010
[0078]
In the pattern mode, the operation of the OR circuit 33 is the same as that in the edge mode, and a description thereof will be omitted.
[0079]
【The invention's effect】
As described above, in the present invention, the look-up table includes, as the line width control information, the pattern information (pattern mode) of the target pixel in addition to the change point address information (edge mode) in the target pixel. As a result, there is an effect that an image having more changes can be expressed as compared with the case where only the edge mode is used.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.
FIG. 2 is a diagram illustrating a configuration of a line width control unit according to an embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration of an OR circuit of a line width control unit in a line according to an embodiment of the present invention.
FIG. 4 is a timing chart showing the operation of one embodiment of the present invention.
FIG. 5 is a timing chart showing the operation of one embodiment of the present invention.
FIG. 6 is a timing chart showing the operation of one embodiment of the present invention.
FIG. 7 is a diagram for explaining one embodiment of the present invention.
FIG. 8 is a diagram for explaining a data configuration in edge mode according to one embodiment of the present invention.
FIG. 9 is a diagram for explaining a data configuration of a pattern mode in one embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Reference pixel generation part 2 Look-up table 3 Line width control part 4 Electronic printer engine (engine)
5 Controller 31 Initial condition generation circuit 32 Bit selection circuit 34 Bit conversion circuit 35 Selector 33 OR circuit 331 Flip-flop 332 EX-OR (Exclusive OR circuit)
333 Data shifter 334 EX-OR (Exclusive OR circuit)

Claims (6)

A reference pixel generation unit that outputs a peripheral pixel matrix around the pixel of interest;
A look-up table that outputs line width control information obtained by subdividing the pixel of interest with a predetermined number of divisions using the peripheral pixel matrix as a reference pixel,
A line width control unit that generates data obtained by subdividing the pixel of interest based on the line width control information using the same number of time-division clocks as the number of divisions;
A controller for controlling operations of the reference pixel generation unit and the line width control unit,
An image forming circuit comprising:
The look-up table, as the line width control information, in addition to edge information indicating a change point address in the target pixel, includes pattern information consisting of image data obtained by subdividing the target pixel,
The controller sends a control signal for selecting an edge mode and a pattern mode, a time-division clock having a phase difference to each other, and a selection signal indicating a reference clock among the time-division clocks to the line width control unit. Supply,
The line width control unit,
In the edge mode, an initial condition generation circuit that receives line width control information from the lookup table as input, calculates and outputs an initial value of the current pixel ,
A bit selection circuit that receives the line width control information as an input, and removes an initial value of the current pixel, and outputs bit data of change point information of the divided data of the current pixel;
In the pattern mode, a bit conversion circuit that receives the line width control information as input and outputs bit data indicating change information of adjacent data of the divided data of the current pixel;
Based on a control signal for selecting an edge mode and a pattern mode supplied from the controller, in the edge mode, the outputs of the initial condition generation circuit and the bit selection circuit are selectively output, and in the pattern mode, the outputs of the bit conversion circuit are output. A selector for selecting and outputting
A data shifter that outputs in parallel the result of shifting the bit data output in parallel from the selector by the number of bits specified by the selection signal from the controller,
A plurality of flip-flops each of which receives the time-division clock supplied from the controller as a sampling clock,
An exclusive-OR circuit that takes outputs of the plurality of flip-flops as inputs and takes an exclusive-OR of these inputs;
An output of each of the plurality of flip-flops, an output of the data shifter at a bit position corresponding to a position of each of the flip-flops being input, A plurality of exclusive OR circuits that supply as data inputs of
An image forming apparatus comprising: The bit conversion circuit outputs an exclusive OR of adjacent two-bit data of the pixel of interest, an initial value is change point information from a final value of a previous pixel to an initial value of a current pixel, attention is matched to the number of bits changing point edge information indicating the address of the pixel outputs, an image forming apparatus according to claim 1, wherein a. The image forming apparatus according to claim 1, comprising the electrophotographic printer engine for outputting a horizontal synchronizing signal to the controller as well as the print image data obtained by subdividing the pixel of interest from the line width control unit. The controller receives a horizontal synchronization signal from the electrophotographic printer engine, supplies a signal obtained by synchronizing the horizontal synchronization signal with a transfer clock to the reference image generation unit together with the transfer clock, and 4. The image forming apparatus according to claim 3 , wherein a control signal for selecting an edge mode and a pattern mode is supplied to the line width control unit. 5. 2. The controller according to claim 1, wherein a rising or falling edge of the horizontal synchronization signal is set as a reference point, and a clock which first arrives after the reference point is selected as a reference clock among the time-division clocks. Image forming apparatus. Electrophotographic printer including an image forming apparatus according to any one of claims 1 to 5.

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