JP3407789B2 - Data pattern generator - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data pattern generator for generating a test signal for a device under test in a digital communication system.

[0002]

2. Description of the Related Art Conventionally, as a data pattern generator, the one described in Japanese Patent Laid-Open No. 8-37485 has been known.
FIG. 7 is a block diagram showing a schematic configuration of the conventional data pattern generator.

In FIG. 7, 1 is a user-specified data memory for storing a data pattern externally specified by the user, and 2 is a CRC (cyclic redundancy) for the user-specified data pattern stored in the user-specified data memory 1.
check) CR that stores the calculation result calculated by the calculation unit 5
C data memory, 3 is a fixed data memory that stores a PN (pulse value) pattern or a fixed pattern "0 or 1", and 4 is a user-specified data memory 1, a CRC data memory 2, and a fixed data memory 3, respectively. Is a read address storage unit for storing read address data for reading the data pattern, and 6 is a data output circuit.

In the data pattern generator configured as described above, depending on the type of data pattern to be generated,
By changing the read start address / read end address stored in the read address storage unit 4, each data pattern is sequentially read from the user-specified data memory 1, the CRC data memory 2, and the fixed data memory 3 to output the data output circuit. 6 generated the data pattern.

[0005]

However, in the configuration of the conventional data pattern generator, the data storage means for the CRC data or PN pattern classified into the test signal pattern and the read address storage for reading each data pattern are provided. Since all the parts and the like are configured by the memory that is the storage means, the storage capacity of the memory tends to increase, and since the read address storage part controls the reading of each data pattern, the read control is complicated. Had the problem of becoming.

The present invention is intended to solve the problem in the conventional device described above, and the memory means can be configured with a small storage capacity, and the write and read control for the memory means can be simplified, while an arbitrary test signal can be obtained. A first object is to provide a data pattern generator capable of generating a pattern.

Further, by storing the user-specified pattern in the memory means, the user-specified pattern and the test signal pattern can be changed without changing the storage capacity of the memory means and while simplifying the writing and reading control with respect to the memory means. A second object is to provide a data pattern generator capable of generating a data pattern in which

[0008]

In order to achieve the first object, the data pattern generator of the present invention has the following configuration. That is, the analyzing means recognizes the type of the data pattern to be generated and generates the control signal according to the type of the data pattern, and the memory means stores the control signal generated by the analyzing means. The test signal pattern generation means generates a test signal pattern for the device under test based on the control signal stored in the memory means.

In order to achieve the second object, the data pattern generator of the present invention has the following configuration. That is, the setting means recognizes the user-specified pattern externally specified by the user, the analyzing means recognizes the type of the data pattern to be generated, generates a control signal according to the type of the data pattern, and sets the memory means in the setting means. The user-specified pattern recognized by and the control signal generated by the analysis unit are stored. And the test signal pattern generating means is
The configuration is such that a data pattern that is a combination of the user-specified pattern and the test signal pattern is generated for the device under test by using the user-specified pattern and the control signal stored in the memory means.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION The invention according to claim 1 of the present invention includes an analyzing means for recognizing a type of a data pattern to be generated and generating a control signal corresponding to the type of the data pattern. memory means for storing the control signal analyzing means is generated, the control for the memory means
Write control for writing signals and stored in the memory means
Control for reading out the control signal
Means and said are those in which a test signal pattern generator for generating a test signal pattern using the memory means control signals stored in, this configuration, the control signal according to the type of various data patterns Can be written in and read out from the memory means, and the test signal pattern generating means can be surely controlled to generate and generate an arbitrary test signal pattern for the device under test.

According to a second aspect of the present invention, an analyzing means for recognizing a type of a data pattern to be generated and generating a control signal corresponding to each type of the data pattern, and a user-designated pattern designated by a user are provided. Recognize and this
Setting means for writing the user-specified pattern in the memory means, memory means for storing both the user-specified pattern recognized by the setting means and the control signal generated by the analyzing means, and the user-specified pattern stored in the memory means And a test signal pattern generating means for generating a data pattern combining a user-specified pattern and a test signal pattern by using the control signal, and writing for writing the control signal generated by the analyzing means to the memory means. Control means and the analysis means stored in the memory means
User's designation of the generated control signal and the setting means
And a control means for performing a read control for reading out the pattern . With this configuration, the memory means stores the user-specified pattern and the control signal in accordance with the user-specified pattern specified by the user and the types of various data patterns. It is possible to write and read data to and from the test signal pattern generating means, and to generate and generate a data pattern that is a combination of an arbitrary user-specified pattern and a test signal pattern for the device under test.

FIG. 1 shows an embodiment of the present invention.
From now on, description will be made with reference to FIG.

FIG. 1 is a block diagram showing the configuration of a data pattern generator for explaining the first embodiment of the present invention.
FIG. 2 is a block diagram showing an example of the circuit configuration of the test signal pattern generating means shown in FIG. 1. In the data pattern generator 7, 10 recognizes a data pattern type signal 14 inputted from the outside and recognizes the data pattern. Analysis means for generating a control signal corresponding to each type of, 11 is a memory means for storing the control signal 16 generated by the analysis means 10, 12 is a data pattern 15 using the control signal 16 stored by the memory means 11 Test signal pattern generating means for generating, and 13 are control means for executing write control and read control for the memory means 11.

In FIG. 2, 17a to 17n are test signal pattern (a to n) generation circuits for generating test signal patterns 19a to 19n, and 18b to 18n are multiplexers.

Next, the operation of the apparatus of the first embodiment will be described with reference to FIGS. FIG. 3A is an explanatory diagram showing the stored contents of the control signal stored in the memory means 11, and FIG. 3B is a time chart of the data pattern 15 generated from the test signal pattern generation means 12. The PTNa to PTNn shown in the time chart correspond to the control signals a to n, respectively, and correspond to the test signal pattern generation circuit 17a.
Shows the pattern generated at ~ 17n.

First, the user sets and inputs the data pattern type signal 14 relating to the type of data pattern to be generated, to the analyzing means 10. The analysis means 10 analyzes the input data pattern type signal 14 to generate control signals (a to n) 16. Since the analysis means 10 writes the generated control signals a to n in the memory means 11, the analysis means 10 notifies the control means 13 of a write execution instruction, and the memory means 11 has the contents shown in FIG.
Write the control signals a to n. When writing is completed,
The analysis means 10 gives a read execution instruction to the control means 13.

The control signals a to n are sequentially read from the memory means 11 by the control means 13. Read control signal a
2 to n are signals indicating whether or not the test signal pattern (a to n) generation circuits 17a to 17n are enabled as shown in FIG.
When it is "1", the test signal pattern (a to n) generation circuit 17a
.About.17n are enabled and test signal patterns a.about.n or PTNa.about.PTNn are generated.

The multiplexers 18b to 18n are respectively controlled by the control signals b to n in the same manner as described above, and when they are "1",
A test signal pattern from the test signal pattern (b to n) generation circuits 17b to 17n is selected. As a result, the test signal patterns PTNa to PTNn are generated and selected to obtain the data pattern 15.

With such a configuration, the data pattern type required by the user is analyzed to create a control signal, and the control signal can be written into and read from the memory means to make the test signal pattern. Since each test signal pattern generation circuit in the generation means can be controlled reliably, it becomes possible to generate an arbitrary test signal pattern for the device under test.

FIG. 4 is a block diagram showing the configuration of a data pattern generator for explaining the second embodiment of the present invention. A data pattern generator 8 in the second embodiment is shown.
Then, in addition to the data pattern generator 7 shown in FIG.
The setting means 20 for recognizing the user-specified pattern specified by the user is provided. In the following, the members corresponding to those described with reference to FIGS. 1 to 3 are denoted by the same reference numerals and detailed description thereof will be omitted.

The operation of the second embodiment will be described with reference to FIGS. FIG. 5 is a block diagram showing a circuit configuration example in the test signal pattern generating means shown in FIG.
6A is an explanatory view showing the stored contents of the user-specified pattern 22 and the control signals a to n stored in the memory means 11, FIG.
(b) is a time chart of the generated data pattern 19. PTNa to PTNn shown in the time chart respectively correspond to the control signals (a to n) 16 and indicate patterns generated by the test signal pattern generation circuits 17a to 17n. USRa to USRn are user-specified patterns 22 specified by the user.

First, the user analyzes the data pattern type signal 14 relating to the type of data pattern to be generated by the analyzing means 10.
Setting and input to the user specified pattern signal
21 is input to the setting means 20. The analysis means 10 analyzes the input data pattern type signal 14 and controls it.
(a to n) 16 are generated. The analysis means 10 writes the generated control signals a to n and the user-specified patterns USRa to USRn by the user-specified pattern signal 21 in the memory means 11,
A write execution instruction is sent to the control means 13 and the setting means 20, and the user-specified patterns USRa to USRn and the control signals a to n are written in the memory means 11 with the contents shown in FIG. When the writing is completed, the analysis means 10 gives the read execution instruction to the control means 13.

In the memory means 11, the user-specified patterns USRa to USRn and the control signals a to n are read simultaneously by the control means 13 in sequence. The user-specified pattern 22 read out as shown in FIG. 5 is input to the multiplexer 18a. In addition, the read control signals a to n are test signal patterns.
(a to n) is a signal indicating whether or not the generation circuits 17a to 17n are valid. When "1", the test signal pattern (a to n) generation circuits 17a to 17n become valid and the test signal pattern a to n or PTNa to PTNn are generated.

The multiplexers 18a to 18n are respectively controlled by the control signals a to n in the same manner as described above.
The test signal patterns a to n from the test signal pattern (a to n) generation circuits 17a to 17n are selected. As a result, the data pattern 19 is obtained by selecting the user-specified patterns, that is, USRa to USRn and the test signal patterns a to n.

With such a configuration, each test signal pattern in the test signal pattern generating means is inputted by inputting the user-specified pattern required by the user, writing the same in the memory means and reading the same as the control signal. Since the generation circuit can be controlled reliably, it is possible to generate an arbitrary data pattern that is a combination of the user-specified pattern and the test signal pattern.

Incidentally, in the apparatus in both the above embodiments,
Although the burst type data pattern generating device has been described, a continuous type data pattern may be generated, and in this case, the control means 13 continuously and repeatedly performs read control on the memory means 11. realizable.

In the apparatus of the second embodiment, the generated data pattern has been described as the data pattern generating apparatus which generates the combination data of the user-specified pattern and the test signal pattern, but the user-specified data is specified by the user. Only the pattern may be generated. In this case, if all the control signals generated by the analysis means 10 are generated as "0" and written in the memory means 11, all the control signals when read out are "0". Therefore, each test signal pattern in the test signal pattern generating means 12 is not generated, and only the user-specified pattern is generated as the data pattern.

[0028]

As described above, according to the present invention, the control signal is stored in the memory means in association with each type of the data pattern generated by the analyzing means, and the control signal is read out to generate the test signal pattern. Since the means can be surely controlled, it is possible to generate an arbitrary data pattern corresponding to the type of the data pattern with a small memory storage capacity and simple control.

Further, the user designating pattern designated by the user is inputted by the setting means, and the control signal and the user designating pattern are stored in the memory means in association with each type of the data pattern generated by the analyzing means.
Since the test signal pattern generating means can be surely controlled by reading by the control means, an arbitrary data pattern in which the user-specified pattern and the test signal pattern are combined by a simple control with a small memory capacity of the memory. Can occur.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a data pattern generator for explaining a first embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration example in the test signal pattern generating means of FIG.

3A is an explanatory view showing the stored contents of a control signal stored in the memory means of FIG. 1, and FIG. 3B is a time chart of a data pattern generated from the test signal pattern generating means of FIG. .

FIG. 4 is a block diagram showing a configuration of a data pattern generation device for explaining a second embodiment of the present invention.

5 is a block diagram showing an example of a circuit configuration in the test signal pattern generating means of FIG.

6A is an explanatory diagram showing the stored contents of a control signal stored in the memory means of FIG. 4, and FIG. 6B is a time chart of a data pattern generated from the test signal pattern generating means of FIG. .

FIG. 7 is a block diagram showing a schematic configuration of a conventional data pattern generation device.

[Explanation of symbols]

7, 8 ... Data pattern generator, 10 ... Analysis means,
11 ... Memory means, 12 ... Test signal pattern generating means,
13 ... Control means, 14 ... Data pattern type signal, 15, 19
… Data pattern, 16… Control signal (a to n), 17a to 1
7n ... Test signal pattern (a to n) generation circuit, 18a to 18n ...
Multiplexer, 19a to 19n ... Test signal pattern (PTNa
~ PTNn), 20 ... Setting means , 21 ... User specified pattern signal, 22 ... User specified pattern (USRa to USRn).

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H04L 29/14

Claims (2)

(57) [Claims] 1. An analyzing unit for recognizing a type of a data pattern to be generated and generating a control signal corresponding to each type of the data pattern, and a memory unit for storing the control signal generated by the analyzing unit. against this memory means
Write control to write the control signal and the memory hand
Read control for reading the control signal stored in the stage;
And control means for performing, the data pattern generating apparatus characterized by comprising a test signal pattern generator for generating a test signal pattern using the stored control signal to the memory means. 2. A recognizes the type of the data pattern to be generated, and analysis means for generating a control signal in association with each type of the data pattern, recognizes a user-specified pattern specified by the user, and the user-specified After the pattern
Setting means for writing in the memory means, memory means for storing both the user-specified pattern recognized by the setting means and the control signal generated by the analyzing means, and the user-specified pattern and control signal stored in the memory means. Test signal pattern generating means for generating a data pattern that is a combination of a user-specified pattern and a test signal pattern, and the analyzing means generates the memory means.
Write control for writing the selected control signal and the memory hand
The control signal generated by the analysis means stored in the stage and
A data pattern generation device, comprising: a control unit for performing read control for reading out a user-specified pattern recognized by a setting unit .