JP3408173B2 - Multi-channel drive integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-channel driving integrated circuit. 2. Description of the Related Art FIG. 1 is a circuit block diagram showing a main part of a general multi-channel driving integrated circuit. In FIG. 1, P-type MOS transistors (1-1) to (1-n) are driving transistors, a source (input electrode) is connected to a power supply Vdd, and a drain (output electrode) is connected to an output pad (2). -1) to (2-n) are connected to n LEDs (not shown). P-type MO
The S transistors (1-1) to (1-n) cause any one of the n LEDs to emit light according to the voltage applied to the gate (control electrode). Inverters (3-1) to (3)
-N) includes a series body of a P-type MOS transistor and an N-type MOS transistor, and includes inverters (3-1) to (3).
−n), the sources of the P-type MOS transistors are commonly connected to the power supply Vdd ′, and the inverters (3-1) to
The drain connection points of the P-type MOS transistor and the N-type MOS transistor constituting (3-n) are connected to the gates of the P-type MOS transistors (1-1) to (1-n). A P-type MOS transistor (4), an operational amplifier (5) and a current detection resistor (6) constitute a constant current circuit. The gate of the P-type MOS transistor (4) is connected to the output terminal of the operational amplifier (5), the source is connected to the power supply Vdd, and the drain is grounded via the current detection resistor (6). The reference voltage Vref is applied to the-(inverting input) terminal of the operational amplifier (5), and the + (non-inverting input) terminal is connected to the non-ground side of the current detection resistor (6). The output terminal of the operational amplifier (5) serving as the output of the constant current circuit is commonly connected to the sources of the N-type MOS transistors forming the inverters (3-1) to (3-n). The constant current circuit is
It detects the voltage across the current detection resistor (6) that fluctuates according to the ON state of the P-type MOS transistor (4), and holds the output voltage of the operational amplifier (5) at a constant value. Therefore, the inverters (3-1) to (3-n)
The source voltage of the type MOS transistor can be held at a constant value, in other words, the P-type transistor when the N-type MOS transistors forming the inverters (3-1) to (3-n) are turned on.
The gate voltages of the OS transistors (1-1) to (1-n) can be set to a constant value, which allows n LEDs to be driven at a constant current. The shift register (7) is composed of n bits, and print data for turning on or off the n LEDs (for example, a logical value "1" indicates lighting, and a logical value "0" indicates turning off. Are sequentially shifted in synchronization with the shift clock SCLK. Latch circuit (8)
Is a latch clock which is composed of n bits corresponding to the shift register (7) and generates n-bit data held in the shift register (7) when the shift register (7) completes n shift operations. Batch latch is performed in synchronization with LCLK. AND gate (9-1)-
(9-n) denotes P-type MOS transistors (1-1) to
(1-n) corresponds one-to-one, and one input terminal is LED
The strobe signal STB having the logical value "1" is supplied at the timing when the light is emitted, and the other input terminal is connected to the n-bit output terminal of the latch circuit (8). As described above, while the strobe signal STB is set to the logical value "1", the P-type MOS transistors (1-1) to which the print data have the logical value "1" are output.
The LED connected to (1-n) is turned on, and the P-type MOS transistor (1-
The LEDs connected to 1) to (1-n) are turned off. Then, dot printing is performed with the lighting of the selected LED, and as a result, a character display, a graphic display, and the like intended by the user are obtained. FIG. 3 is a diagram showing an arrangement pattern of the elements of FIG. 1 on a semiconductor substrate. In FIG. 3, the print driving integrated circuit chip (10) of FIG.
Are arranged in parallel according to the number of print dots. For example, a print drive integrated circuit chip (10) having 192 output pads (2) is used and 960 at a time.
When performing dot printing, it is necessary to provide five print drive integrated circuit chips (10) on the printed board (11).
The individual print drive integrated circuit chips (10) are cascaded so that the strobe signal STB, the latch clock LCLK, and the shift clock SCLK are commonly applied.
The output pads (2-1) to (2-n) in the print driving integrated circuit chip (10) are usually arranged on one side of the upper side in the longitudinal direction of the chip, and the metal terminals (12-n) on the printed board (11) are arranged. 1) to (12-n) are bonded (wire-bonded) one to one with an aluminum wiring (13) or the like. The one-dot chain line inside the print driving integrated circuit chip (10) is the location (active area) of the component shown in FIG. 1 and is electrically coupled to the output pads (2-1) to (2-n). FIG. 4 is a sectional view of the print driving integrated circuit chip (10). The print driving integrated circuit chip (10) protects the components on the chip from external factors, so that the first area of the output pad (2-1) to (2-n) is protected except for the external lead-out area. After forming the film (14) (silicon oxide film, silicon nitride film, etc.), a second protective film (15) is further formed.
(Polyimide insulating film) is formed and double protected. Recently, with the increase in the density and the function of integrated circuits, adjacent output pads (2) have been developed.
The interval M between the two tends to be narrow. Usually, the interval M is 3
If the thickness is about 0 μm or more, there is no problem. If the thickness is reduced to about 20 μm or less, the first protective film (14) can be easily formed on the print driving integrated circuit chip (10) because of its material. Since the thickness of the first protection film (15) is larger than the thickness of the first protection film (14) and the interval M is smaller than an ideal value, the second protection film (15) on the output pads (2-1) to (2-n) is formed. 1
5) When etching, the second protective film (14)
There was a problem that the protective film (15) was not completely formed due to peeling or the like, and an intended protective film could not be formed. Therefore, there is a limit to the size reduction of the print driving integrated circuit chip (10). SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-channel drive integrated circuit which does not impair the reliability even if the gap between the output pads is set smaller than before. SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has a plurality of driving circuits for outputting signals for driving a passive element array or an active element array. A multi-channel in which a transistor and a plurality of output pads connected to output terminals of the plurality of driving transistors are provided on a single semiconductor substrate, and the plurality of output pads are arranged at specific locations on the single semiconductor substrate In the drive integrated circuit, after providing a first protective film in a region other than the openings of the plurality of pads on the single semiconductor substrate, at least the arrangement region of the plurality of output pads on the single semiconductor substrate is changed. It is characterized in that a second protective film is provided in a region except for the above. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be specifically described with reference to the drawings. FIG. 2 is a diagram showing an arrangement pattern of the multi-channel driving integrated circuit of the present invention. In FIG. 2, the components shown in FIG. 1 are integrated in a solid line area A of the print driving integrated circuit chip (10), and output pads (2-1) to (2-n) are arranged in a solid line area B.
Are arranged in the longitudinal direction. 2. The drains of P-type MOS transistors (1-1) to (1-n) corresponding to the drive transistor according to claim 1 integrated in a solid line area A, and an output pad (2-1) arranged in a solid line area B. To (2-n) are connected by a metal wiring. After the device of FIG. 1 is integrated on the print drive integrated circuit chip (10), it is necessary to form a protective film for protecting the device of FIG. 1 from external factors. First, a first protection film (silicon oxide film, silicon nitride film, etc.) which is obliquely upwardly sloping is formed on solid line regions A and B representing the entire print drive integrated circuit chip (10), and the output pads (2-1) to Only the external lead-out region of (2-n) is etched to form an opening for wire bonding. Thereafter, a second protective film (polyimide insulating film) which is obliquely inclined to the right is formed only in the solid line region A (FIG. 2A). Alternatively, a solid line area A and a solid line area B
(FIG. 2b). Since the solid line region B has only n output pads and metal wiring, the first protective film alone is sufficient for protection. As described above, in the embodiment of the present invention, since the second protective film is not provided between the adjacent output pads, the gap between the output pads can be shortened, and the size of the print driving integrated circuit chip can be reduced. Can be. According to the present invention, since the second protective film is not provided between the adjacent output pads, the gap between the output pads can be shortened, and the size of the print driving integrated circuit chip can be reduced. The advantage that can be obtained is obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit block diagram showing a general multi-channel driving integrated circuit. FIG. 2 is a diagram showing an arrangement pattern of a multi-channel driving integrated circuit of the present invention. FIG. 3 is a diagram showing an arrangement pattern of a conventional multi-channel driving integrated circuit. FIG. 4 is a sectional view of FIG. 3; [Description of Signs] (1-1) to (1-n) P-type MOS transistors (2-1) to (2-n) Output pad (10) Print drive integrated circuit chip (13) Metal wiring (14) 1 protective film (15) 2nd protective film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H01L 21/82 H01L 21/822 B41J 2/44 B41J 2/45 B41J 2/455 H01L 27/04

Claims (1)

(57) [Claim 1] A plurality of drive transistors for outputting a signal for driving a passive element array or an active element array;
A multi-channel drive integrated circuit in which a plurality of output pads connected to output terminals of the plurality of drive transistors are provided on a single semiconductor substrate, and the plurality of output pads are arranged at specific locations on the single semiconductor substrate In the above, after providing a first protective film in a region on the single semiconductor substrate excluding the openings of the plurality of pads, at least in a region excluding an arrangement region of the plurality of output pads on the single semiconductor substrate. Providing a second protective film and adjoining
A multi-channel driving integrated circuit, wherein a second protective film is not formed between output pads .