JP3418285B2 - Switching power supply - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching power supply device, and more particularly to a full-wave rectification type synchronous rectification using a midpoint tap type secondary winding suitable for a low voltage and large capacity power supply device. The present invention relates to a switching power supply device.

[0002]

2. Description of the Related Art As a conventional technology relating to a switching power supply device, for example, Akira Hasegawa, "Switching Regulator Design Know-how", April 10, 1985, CQ Publishing Co., Ltd., p. 28, FIG. -D
The technology shown in "Main circuit and characteristics of C converter" (e) is known.

In this prior art, an inverter having a full-bridge circuit structure is provided on the primary side of the transformer, and a midpoint tap type full-wave rectification circuit is provided on the secondary side of the transformer.
The power supply device having such a configuration is suitable for use as a large-capacity switching power supply because the output is most easily extracted from the relationship between the withstand voltage and the current of the transistor used in the inverter.

In the above-mentioned conventional technique, the output voltage is controlled by the duty of the drive voltage of the inverter. Then, while the inverter is in the ON state and the current is flowing to the primary side of the transformer, the rectifying diode on the secondary side causes the current to flow toward the output via the smoothing inductance L. Further, the rectifier diode continues to flow the return current of the inductance L while the inverter is turned off and the current is stopped from flowing to the primary side of the transformer.
However, since the inverter on the primary side is off,
This return current cannot flow to the primary side, is shunted to the rectifier diode on the opposite side, and this state is maintained until the next reverse driving.

In general, most of the loss of the switching power supply is occupied by the loss due to the drop of the rectifying diode and the switch loss of the inverter. In the past, efforts have been made to reduce losses by using chain diodes in order to reduce diode drops, but in recent years, the power supply voltage required by equipment, that is, the output voltage of the power supply device The efficiency of power supplies that perform rectification by chain diode is not satisfactory because the efficiency is decreased, and further improvement in efficiency is required.

Further, there is a resonance power supply device as a power supply device capable of improving efficiency, and as a conventional technique related to this type of power supply device, for example, "Product-&-Applicat."
ionsHandbook 1993-94 ”Unitrode Integrated Cincuits
The technology described on pages 9-201, etc. of Corpovation is known. This resonance type power supply device has a small switching loss and can be miniaturized by increasing the switching frequency. However, in the example of the above literature, the efficiency is 75%.
%.

In addition to the above, "Electronic Technology: Switching Power Supply Design Handbook" as a conventional technology related to switching power supplies, published by Nikkan Kogyo Shimbun Co., Ltd. 1989 Vo
Various circuits described on pages 14 to 15 of l.31 No. 3 are known.

FIG. 3 is a circuit diagram showing the configuration of an example of a switching power supply device according to the prior art, and FIG. 4 is an operation waveform diagram for explaining the operation thereof. Hereinafter, referring to FIGS. The configuration and operation of the power supply device will be described. In FIG. 3, T ₁ is a transformer and M _{1 to} M ₄ are MO.
S transistors, D _{1 to} D ₄ are body diodes which are parasitic elements of MOS transistors, D ₅ and D ₆ are rectifying diodes, L ₁ is a smoothing inductance, C ₁ is a capacitor for preventing magnetic bias of a transformer, and C ₂ Is a smoothing capacitor, C ₃
Is a snubber capacitor, R ₁ is a snubber resistor, and R _L is a load.

In the circuit shown in FIG. 3, MOS transistors M _{1 to} M ₄ are enhancement type MOS transistors which are turned on at a high level and turned off at a low level, and form a full-bridge inverter. These transistors M ₁ ~M ₄ is controlled by a gate drive signal V ₁ ~V ₄ to the primary winding of the transformer T _1, via a capacitor C ₁ for biased magnetization prevention of the transformer T _1, Power supply voltage +
A current i _T having a required duty is supplied from V _I and −V _I. The current flowing through the secondary winding of the transformer T ₁ is double-wave rectified by the rectifying diodes D ₅ and D ₆ , and the rectified DC current forms an inductance L ₁ and a capacitor C that form an output smoothing filter. Load through ₂ R _L
Is supplied to. Then, the voltage supplied to the load R _L of the power supply, the power supply voltage + V _I, and -V _I, transformer T ₁
Of the current i _T flowing through the primary winding of the transformer T ₁
And the winding ratio of.

The operation waveform shown in FIG. 4 shows the waveform of each position and each signal shown in FIG. 3. V ₁ is the gate drive waveform of M ₁ , and similarly V ₂ is M ₂ and V ₃ is of M _3, V ₄ is the gate drive waveform of M _4. Further, H shown along with the waveforms shown as V _{1 to} V ₄ shows a high level, L shows a low level, and the transistors M _{1 to} M ₄ turn on at a high level and turn off at a low level. Further, in FIG. 4, t ₂ , t ₃ , t ₅ , t
₆ is a period showing the state of operation.

During the period t ₂ , the MOS transistors M ₁ and M ₄
Is on and the primary side of the transformer T ₁ is driven in the current direction shown as i _T in FIG. 3, and the period t ₅ is M
In this period, the OS transistors M ₂ and M ₃ are turned on and driven in the direction opposite to the current direction indicated by i _T. Then, during these periods, the currents i ₄ and i ₃ flow to the secondary side of the transformer T ₁ , are rectified by the diodes D ₆ and D ₅ , and are rectified via the inductance L ₁ and the capacitor C ₂ which form the smoothing filter. The current i _T is supplied to the load R _L. Also, the period t ₃ ,
t ₆ is a period in which the transformer T ₁ is opened from the inverter drive circuit including the transistors M _{1 to} M ₄ .

By the way, since the current i _T of the transformer T ₁ is cut off at the end timing of the above-mentioned periods t ₂ and t ₅ ,
Due to the leakage inductance of the transformer T ₁ during the beginning of the periods t ₃ and t ₆ , a flyback voltage is generated in the primary winding of the transformer T ₁ as shown by the waveform v ₁ -v _{2 in} FIG. This causes a large oscillating voltage. In order to suppress the generation of this oscillating voltage, the capacitor C ₃ and the resistor R ₁
Is provided, and the snubber current i _SN flows through the snubber circuit to absorb vibration energy. The power consumption of this snubber circuit depends on how much vibration is suppressed, but 20 W to 40 W is required.

Further, in the above-mentioned prior art, the MOS
Transistor M ₁ ~M ₄ switching loss P _SW of the inverter by is the power consumed by charging and discharging of the drain capacitance of the MOS transistor M ₁ ~M _4, can be expressed by the following equation (1).

P _SW = N × C _OSS × [{+ V _I − (− V _I )} / 2] × f (1) where N: number of MOS C _OSS : output capacitance V _{I of} MOS: power supply Voltage f: Switching frequency In the above, the number of MOSs = 4, output capacity = 2 × 10 to ⁹
If F, V _I = 135V and f = 100 × 10 ³ , then P _SW
≈15W.

[0015]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
Since no consideration is given to the switching loss of the inverter, and because the diode is used for rectification, it is impossible to eliminate the switching loss of the inverter and the rectification loss due to the diode, making it difficult to improve the efficiency of the power supply device. It has a problem that

Generally, in order to greatly improve the efficiency of the switching power supply device, it is necessary to reduce the loss due to the voltage drop of the rectifier diode, and the loss due to this voltage drop employs a synchronous rectification circuit using MOS transistors. It can be realized by It is quite natural to turn on the MOS transistor for synchronous rectification during this rectifying operation, and it is usual that the loss during this period is reduced.

Further, it is necessary to reduce the loss even during the return operation after the rectifying operation. In general, a switching power supply device controls an output voltage thereof by providing an inverter on the primary side of a transformer for pulse width control. Therefore, in the half cycle period of the rectifying operation, there are a period in which the current flows from the inverter side and a period in which the current is cut off. The period during which the current is cut off is the above-mentioned reflux operation period, and normally the rectifying operation is stopped,
The return current is flowing through another path. For example, if the rectifier circuit is M
When it is composed of an OS transistor, its path is MO
It becomes the body diode of the S transistor. Since the body diode is a silicon diode, its drop voltage is about 0.7 V to 1.2 V, which causes an abnormally large loss during the freewheeling period. In order to avoid this, control is performed so that the period of time flowing through the body diode is extremely short, that is, the pulse width is abnormally widened, or a freewheeling Schottky diode is used in addition to the rectifying MOS transistor. It is possible to use.

Although the efficiency of the switching power supply device can be improved by using the above-mentioned methods, these methods cannot significantly improve the efficiency. In addition, the above-mentioned method of operating with an abnormally wide pulse width makes the variable width of the output voltage narrow, making it difficult to use as a power supply device. There is a problem that miniaturization is hindered and cost is increased.

The object of the present invention is to solve the above-mentioned problems of the prior art, and the loss due to the drop of the rectifying diode, which has conventionally dominated most of the loss, the switching loss of the inverter, and the loss during the flow of the return current. It is an object of the present invention to provide a switching power supply device capable of significantly reducing the power consumption and improving the efficiency.

[0020]

The object according to the present invention SUMMARY OF THE INVENTION includes an inverter provided on the primary side of the transformer, and a center tap full-wave rectifier circuit provided on the secondary side of the <br/> transformer A rectifying circuit for a full-wave rectifying circuit, comprising:
The element is constituted by a switch element, and its on-time is maintained during the rectifying operation and while the return current of the smoothing inductance flows, and the return current is induced to the primary side of the transformer to drive the inverter. This is achieved by allowing the flow to the switch element that constitutes it.

Further, the object of the present invention is, in the above, that the flyback voltage generated by the transformer is set to the inverting drive side at the timing when the reflux current of the inverter provided on the primary side of the transformer is cut off to start the inverting rectification operation. This is achieved by setting it in a period in which the voltage across the switch element is close to 0V.

Further, the object of the present invention is as follows.
This is achieved by configuring the inverter with a full bridge circuit using MOS transistors and using a rectifier circuit as a synchronous rectifier circuit using MOS transistors.

According to the present invention, the synchronous rectification by the MOS transistor is used to reduce the loss due to the voltage drop in the rectifier circuit, and the zero volt switch is used.
The switching loss of the inverter can be reduced, and the return current generated by the inductance of the output filter is made to flow to the primary side inverter, so that the loss due to the return current can also be reduced.

Hereinafter, the improvement of the efficiency of the switching power supply device according to the present invention by reducing the above-mentioned various losses will be further described.

It can be said that the reduction of the loss during the rectifying operation of the switching power supply device is the processing of the return current flowing through the inductance of the output filter. If the return current is made to flow through the body diode of the rectifying MOS transistor, the loss will increase by almost one digit. Therefore, according to the present invention, the MOS transistor for rectification is not turned off but kept in the ON state even after the rectification current flows and the rectification current flows. The loss is suppressed during this period. In addition, in the present invention, in order to further reduce the loss during the return current period, the return current is reduced to a transformer.
I try to run it to the next side.

In general, the inverter provided on the primary side of the transformer performs pulse width control for output voltage control. Then, the inverter turns off after the transformer is pulse-driven, and even if the reflux current continues to flow to the secondary side rectifying MOS transistor, the primary side is turned off. No return current can flow to Therefore, when such an operation is performed, the return current flows through the body diode of the MOS transistor on the secondary side which is off, and the loss here cannot be reduced.

Therefore, according to the present invention, a return current is supplied to the primary side of the transformer. In order to flow the return current to the primary side of the transformer, it is necessary for the inverter to control the pulse width and also to flow the return current. Therefore, the inverter provided on the primary side of the transformer according to the present invention is
Since the MOS transistor has a full bridge configuration, one of the high-voltage side or the low-voltage side MOS transistor is controlled to perform pulse width control for controlling the output voltage, and the MOS transistor on the opposite side flows a return current. It is controlled to continue to be on. As a result, the inverter causes the secondary side return current to pass through the secondary side return current to the primary side MOS transistor that remains on and the off side MOS transistor to turn off.
It can flow through the body diode of the transistor.

In the present invention, as described above, by guiding all the secondary side return current to the primary side, the return current flows through the body diode of the rectifying MOS transistor on the secondary side to increase the loss. You can get rid of things.

Further, the loss of the switching power supply is
By reducing the switching loss of the inverter provided on the primary side of the above-mentioned transformer, that is,
This can be reduced by selecting the timing of cutting off the return current on the primary side of the transformer. The switching power supply is
Since it is due to the inverter operation, it is not possible to continue to flow the return current, and the current is periodically passed through the transformer in reverse to transfer the power to the secondary side of the transformer. It is necessary to cancel the state.

When the MOS transistor that is flowing a return current on the primary side of the transformer is turned off, the current flowing in the transformer is cut off. As a result, the leakage inductance of the transformer causes a flyback effect, and the primary side of the transformer is cut off. The voltage reaches a voltage sufficient to turn on the body diode of the opposing MOS transistor. In this state, when the MOS transistor on the opposite side is turned on, this MOS transistor can be turned on at a source-drain voltage of 0V. As a result, the present invention can operate the inverter provided on the primary side of the transformer without switching loss.

The present invention can achieve high efficiency of the switching power supply device as described above.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a switching power supply device according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing a circuit configuration of a switching power supply device according to an embodiment of the present invention, and FIG. 2 is a timing chart for explaining its operation. In FIG. 1, M ₅ and M ₆ are MOS transistors, and D ₅ and D ₆ are MOS transistors.
It is a body diode which is a parasitic element of a transistor, and other symbols are the same as in the case of FIG.

In the circuit shown in FIG. 1, MOS transistors M _{1 to} M ₄ are enhancement type MOS transistors which are turned on at a high level and turned off at a low level, and form a full-bridge inverter. These transistors M ₁ ~M ₄ is controlled by a gate drive signal V ₁ ~V ₄ on the primary side of the transformer T _1, via a capacitor C ₁ for biased magnetization prevention of the transformer T _1, the power supply voltage + V _I, -
A current having a required duty is supplied from V _I. Also,
MOS transistor T _5, T ₆ is a transistor for rectification, is inverter and synchronous control by the gate drive signal V ₅ ~V _6, rectified DC current, the inductance L _1, C ₂ constituting the output smoothing filter Is supplied to the load R _L via.

The timing chart shown in FIG. 2 shows the waveform of each position and each signal shown in FIG. The difference from the prior art in one embodiment of the present invention that operates according to this timing chart is that the device of one embodiment of the present invention is
Period t _1, and that have a t _4, t _7, also become a MOS transistor M ₁ ~M prior art by a pair of _4-on, transistor M ₁ that has been turned off constituting the inverter,
For M ₄ and M _2, M _3, continues to turn on the M ₁ in the period t ₃ after M ₄ off is that continues to turn on the M ₁ during the period t ₆ after M ₃ off.

In FIG. 2, as in the case of the prior art,
V _{1 to} V ₄ are gate drive waveforms of M _{1 to} M ₄ , and are V _{1 to} V ₄
The H indicates a high level and the L indicates a low level, and the transistors M _{1 to} M ₄ are turned on at a high level and turned off at a low level. Further, in FIG. 2, t _{1 to} t ₇ are
The period t ₂ is a period in which the primary side of the transformer T ₁ is driven in the current direction shown as i _T in FIG. 1, and the period t ₅ is a current shown as i _T. It is a period for driving in the opposite direction. Each period of t ₁ , t ₄ , and t _{7 is} a period in which the transformer T ₁ is opened from the inverter drive circuit including the transistors M _{1 to} M ₄ . The period of t ₃ and t _{6 is} a period in which the return current of the load current i _L is supplied to the primary side of the transformer T ₁ .

Next, referring to FIGS. 1 and 2, the operation of the power supply device according to the first embodiment of the present invention will be described for each period t _{1 to} t ₇ .

At the starting point of the period t _1, the primary side current i _T of the transformer starts to decrease from the negative current flowing until then toward 0. At the same time, ₁ of transformer T 1
A flyback voltage is generated across the secondary winding due to leakage inductance. This voltage is v ₁ in FIG.
As the waveform shown as -v _2, + V _I - a voltage having a value of - (V _I). This flyback voltage is the current i _T
Until but it becomes 0 amps, + V _I - stay on the value of - (V _I).

During this period t ₁ , the MOS transistor M ₁ ,
When M ₄ is controlled to be turned on and the direction of the current i _T is made to rotate in the positive direction opposite to that in the past, MO becomes
The S-transistors M ₁ and M ₄ have a drain-source voltage V
_The drive state, that is, the on state from the off state can be entered in the state of _DS = 0V. Such an operation is performed by ZVS (Z
It is called ero / Volto / Swiching) and can switch MOS transistors with low loss.

As described above, in the period t ₁ , V ₂ is changed from high level to low level to turn off the MOS transistor M ₂ which has been turned on until then, and then V ₁ and V ₄ are changed from low level to high level. It can be seen that the period until the MOS transistors M ₁ and M ₄ are turned on is limited to the period until the current i _T becomes 0 ampere. In the example shown in FIG. 2, the operation is switched from the MOS transistor M ₂ to M ₁ or from the M ₁ to M ₂ at the ideal ZVS operation timing, and the drain-source voltage is 0V. At the same time, when the current i _T also becomes 0 A, the MOS
The transistor M ₁ is turned on.

During the period t ₂ , the MOS transistors M ₁ and M ₄
Is turned on and the current i _T flows in the positive direction, and is a period in which energy is sent from the primary side of the transformer to the secondary side. Even if the MOS transistors M ₁ and M ₄ are turned on within the period t _{1 in} which the current i _T changes toward 0 A, the current i _T does not flow in the desired direction. The current i _T starts flowing in the desired direction after the current i _T crosses 0A. Therefore, the start of the period t ₂ is when the current i _T starts to increase positively from 0 A, and the rising speed of the current i _T depends on the voltage v ₁ −v between the primary windings of the transformer T _{1. It} is determined by the value of _{2 and} the value of the leakage inductance of the transformer T ₁ , and can be expressed by the equation (2).

D _it / d _t = (v ₁ −v ₂ ) / L _l (2) However, in the equation (2), L ₁ is the leakage inductance seen from the primary side of the transformer T ₁ .

In accordance with the change in the primary side current i _T of the transformer T ₁ as described above, the secondary side current also changes, and changes to currents i ₃ and i ₄ as shown in FIG. To do. That is, at the beginning of the period t ₁ , the current i ₃ begins to decrease and the current i ₄ begins to increase. At the end of the period t ₁ , i ₃ = i ₄ and its value is 1/2 of the load current i _L. And
From this time point, at the beginning of the period t ₂ after the lapse of the period corresponding to the period t ₁ , i ₃ = 0 and i ₄ = i _L are changed.
During the period in which the secondary current is changing, both the MOS transistors M ₅ and M ₆ connected to the secondary side are passing current through the body diodes D ₅ and D ₆ which are parasitic diodes. . Therefore, the secondary side of the transformer T ₁ is short-circuited, and both ends of the winding on the secondary side of the transformer T ₁ are
No voltage is generated. Therefore, the first period of the period t ₂ is a period in which the output voltage cannot be generated on the secondary side even when the primary side of the transformer T ₁ is driven and the current i _T is passed. This is based on equation (2).

The change in the voltages v ₄ and v ₃ on the secondary side of the transformer T ₁ shown in FIG.
Only for a period corresponding to ₁ , the change rises with a delay from the start time of the period t ₂ . If the voltage v ₄ Re rising, MOS transistors M also rising voltage v ₅ through _6, thereby, starts to flow a current i _L toward the inductance L _1. The remaining period of the period t ₂ is a period in which the current i _L continues to flow toward the inductance L ₁ , and electric power is being sent out toward the load R _L.

The next period t ₃ is the most characteristic point of the present invention, and this period will be described below.

The period t ₃ is a period in which the MOS transistor M ₄ is turned off and the inverter stops driving the transformer T ₁ . And during this period, the MOS transistor,
M ₁ and M ₆ are kept in the ON state following the period t ₂ . When the inverter stops driving, the transformer T ₁
The electric power is no longer transmitted to the secondary side of the device and tries to stop the current supply. However, i _L flowing in the inductance L ₁ tries to keep flowing current due to the nature of the inductance. This is called a return current.

Now, assuming that all the MOS transistors M _{1 to} M ₄ driving the primary side of the transformer T ₁ are turned off,
If the impedance becomes high, the inductance L
_The return current flowing in ₁ tries to keep flowing the current i ₄ through the MOS transistor M ₆ . However, since the primary side has a high impedance, the current i _T does not flow, and therefore the current i ₃ flows through the other winding on the secondary side. The MOS transistor M ₅ is turned off at a low level of the gate control voltage V ₅ during the off period of the rectifying operation. Therefore, the current i ₃ is M
Flowing through the body diode D ₅ of the OS transistor M ₅ ,
A large power loss occurs due to the drop voltage of 0.8V to 1.0V. The above-described operation of turning off all of the primary side MOS transistors M _{1 to} M ₄ is the operation itself according to the conventional technique.

In one embodiment of the present invention, even after the MOS transistor M ₄ is turned off, the MOS transistor M ₁ is controlled so as to remain in the on state. MOS transistor M ₄
If There turned off, the cut current i _T of the primary side of the transformer T _1, the fly-back due to the inductance of the transformer T _1, upstream vane drain potential of the MOS transistor M _4, the MOS transistor M ₂ Bodei diode D _The current i _T will flow in ₂ . Therefore, the transformer T
_The voltage applied to the primary winding of 1 becomes 0V, and the voltage between the secondary windings also becomes 0V.

In this state, the return current i _L flowing through the inductance L ₁ flows through the MOS transistor M ₆ held in the ON state, and as a result, i ₄ continues to flow, and the return current i _L flowing through the inductance L ₁ changes. The current i _T continues to flow to the primary side of the transformer T ₁ . As shown in the operation waveforms of FIG. 2, since the gate driving signal V ₆ for the MOS transistor M ₆ is at the high level during a period t _3, MOS
The transistor M ₆ is in the ON state and conducts with a low resistance even while the return current continues to flow, and the power loss thereof is suppressed to a small level.

On the other hand, in the prior art, the primary side of the transformer T ₁ is opened at the end of the period t ₂ , the leakage inductance of the transformer T ₁ and the drain-source and drain of the MOS transistors M _{1 to} M ₄ and the drain. −
Resonance is caused by the stray capacitance existing between the gates,
The voltage on the primary side of the transformer T _{1 was} violently vibrated.
Therefore, in the conventional technology, it is necessary to insert a snubber circuit in order to suppress the vibration between the primary windings of the transformer T ₁ .
Power loss due to this snubber circuit is not small.

In one embodiment of the present invention, during period t ₃ , M
Since the OS transistor M ₁ remains on,
The primary side of the transformer T ₁ is not opened, and the current i _T can continue to flow, and as a result, voltage oscillation does not occur. Therefore, the power supply device according to the embodiment of the present invention does not need the primary snubber circuit of the transformer T ₁ , and the loss can be reduced also here.

The period t ₄ is a period for cutting off the current i _T, which is the return current i _L induced by the inductance L ₁ on the primary side, by turning off the MOS transistor M ₁ .
When the MOS transistor M ₁ is turned off, a flyback voltage due to the leakage inductance of the transformer T ₁ is generated from that point, and the voltage v ₁ is swung to −V _I ,
The current i _T tries to continue flowing through the body diode D ₃ of the MOS transistor M ₃ , but starts decreasing from the positive current toward 0 A. The operation from here is the same as that in the case of the period t ₁ described above except that the direction of the current is reversed.

In the subsequent periods t ₅ and t ₆ , the same operation as that in the periods t ₂ and t ₃ described above is performed except that the direction of the current is reversed. Further, the period t ₇ is exactly the same as the period t ₁ .

In the operation of the above-described embodiment of the present invention, the MOS transistors M _{1 to} M are operated during the periods t ₁ , t ₄ , and t _7.
This is a period in which the drive direction of the current is switched by the inverter of ₄ , and thus ZVS can be realized at the time of switching. The power supply device according to the embodiment of the present invention can set the switching loss of the inverter to almost zero by setting this period. Periods t ₂ and t ₅ are rectification operation periods, and M for rectification is used.
This is a period in which the OS transistors M ₅ and M ₆ are turned on. As described above, by using the MOS transistor for rectification, it is possible to reduce the loss due to the forward voltage drop (semiconductor energy gap) of the diode that occurs in the conventional diode rectification.

Further, during the periods t ₃ and t ₆ , the inductance L
_{In the} period in which the return current of ₁ flows, the return current flowing in the body diode of the rectifying MOS transistor is transferred to the transformer T.
_This is a period in which the current is supplied to the MOS transistor M ₁ or M ₂ on the primary side of 1. By causing the return current flowing through the body diode of the rectifying MOS transistor to flow through the primary-side MOS transistor M ₁ or M ₂ of the transformer T ₁ , the loss caused by the forward voltage drop of the body diode is caused. the lost, also the return current on the primary side of the transformer T ₁ can be reduced by the transformer T ₁ winding ratio content can also be reduced loss due to this. Further, in the prior art, the snubber circuit, which was required for the primary side inverter, can be eliminated and the loss here can be eliminated.

According to one embodiment of the present invention, the power loss can be reduced as described above.
As in the schematic below looking to reduce the power loss as compared to the prior art power supply with power supply having an output of about KW, (1) the period t _1, t _4, the effect of ZVS operation of t ₇ 55W (2) Effect of synchronous rectification during periods t ₂ and t ₅ 50W (3) Effect of return current to the primary side during periods t ₃ and t ₆ 35W Total 140W of power loss can be reduced.

Next, the effects of the above-described embodiments (1) to (3) of the present invention will be described based on the structural difference and the operational difference from the prior art.

Regarding the effect of (1) In the case of the prior art, as described with reference to FIG. 3 and FIG. 4, the inverter 1 is used at the end timing of the periods t ₂ and t _5.
Since the secondary drive current i _T is cut off, a flyback voltage is generated by the leakage inductance of the transformer T _{1 in} the beginning of the periods t ₃ and t ₆ , and a large oscillating voltage is generated. To avoid this, capacitor C ₃ ,
A snubber circuit composed of the resistor R ₁ is required, and the current i _SN flows through this snubber circuit, and the vibration energy is absorbed. The power consumption of this snubber circuit in the case of the prior art requires 20W to 40W.

Further, in the prior art, the inverter constituted by the MOS transistors M _{1 to} M ₄ has a switching loss P _SW because ZVS is not controlled. The switching loss P _SW is power consumed by charging and discharging the drain capacitances of the MOS transistors M _{1 to} M ₄ , and is represented by the equation (1), as already described.
Number of MOSs = 4, output capacitance = 2 × 10 to ⁹ F, V _I = 13
When 5V and f = 100 × 10 ³ , P _SW ≈15 W.

In the embodiment of the present invention, the snubber circuit is not required, and the ZVS operation is performed during the flyback voltage rising time of 100 ns to 200 ns in the periods t ₁ , t ₄ , and t _7. Therefore, the snubber circuit loss is 40
W and switching loss 15 W can be set to 0,
It is possible to reduce the power loss of 55 W.

Regarding the effect of (2) This effect is due to the synchronous rectification and is not an effect peculiar to the present invention, but during the rectification operation period of the periods t ₂ and t ₅ , the voltage drop between the diode and the MOS transistor is caused. The loss can be reduced by the difference of
_{LOSS (D)} can be expressed by equation (3).

P _{LOSS (D)} = V _{DF (D)} × i _L × (t ₂ + t ₃ ) × f (3) However, V _{DF (D)} is the difference voltage of the voltage drop, and f is the switching frequency. is there.

Specifically, assuming that the forward drop voltage of the diode is 0.5 V and the voltage drop of the MOS is 0.1 V, there is a differential voltage of 0.4 V, and the output current i _L =
Assuming 250 A, t ₂ = t ₃ = 2.5 μs, and f = 100 kHz, the loss difference is P _{LOSS (D)} = 0.4 V × 250 A × (2.5 + 2.5) × 100 kHz = 50 [W] Become.

That is, the synchronous rectification can reduce the power loss of 50 W as compared with the prior art.

Regarding the effect of (3) In the case of the prior art, the inductance L _{1 is set in the} periods t ₃ and t _6.
The reflux current i _{L of the above} is applied to the diodes D ₅ and D ₆ . On the other hand, in the embodiment of the present invention, the return currents during the periods t ₃ and t ₆ are controlled so as to flow through the MOS transistors M ₁ and M ₂ on the primary side. That is, in one embodiment of the present invention, the MOS transistor that has completed the rectifying operation is kept in the ON state, and the return current is caused to flow with a small voltage drop, and the return current is induced to the primary side of the transformer T _1. ,
The MOS transistor forming the inverter is operated so that a return current flows. In this way, the return current flowing through the primary side of the transformer T _1, can be one of the current amount of the turns ratio of the transformer T ₁ minute, transformer T ₁
Power consumption can be significantly reduced as compared with the case where the recirculation operation is performed on the secondary side. To what extent the loss at the time of reflux differs will be described below according to an embodiment of the present invention.

In the case of the prior art, the loss P _LOSS at the time of return is
It can be expressed by equation (4).

P _LOSS = V _D × i _L × (t ₃ + t ₆ ) × f (4) where V _D is the forward voltage drop of the diode and f is the switching frequency.

Specifically, V _D = 0.4 V, i _L = 250
If A, t ₃ = t ₆ = 2.5 μs, and f = 100 kHz, then P _LOSS = 0.4 V × 250 A × 5 μs × 100 kHz = 50 W.

The loss P _LOSS at the time of reflux in the case of one embodiment of the present invention can be expressed by the equation (5).

P _LOSS = (V _MOS × i _L + V _DMOS × i _L / n) × (t ₃ + t ₆ ) × f (5) However, V _MOS is the ON voltage drop of the secondary side MOS, V _DMOS Is the voltage drop of the body diode of the primary side MOS, and n is the winding ratio of the transformer.

Specifically, V _MOS = 0.1 V, V _DMOS =
0.7 V, i _L = 250 A, n = 35, t ₃ = t ₆ = 2.
If 5 μs and f = 100 kHz, then P _LOSS = (0.1 V × 250 A + 0.7 V × 250 A /
35T) × 5 μ × 100 kHz = 15 W.

As described above, according to the embodiment of the present invention, the return current is supplied to the primary side MOS transistors M ₁ and M _2.
By controlling so that the current flows in the above range, the loss in this reflux period can be reduced by 35 W, which is the difference described above.
It can be reduced to about 1/3 of the case of the conventional technique.

[0073]

As described above, according to the present invention, the loss due to the drop of the rectifying diode in the switching power supply device and the switching loss of the inverter can be reduced, and the efficiency of the power supply device can be greatly improved. .

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a switching power supply device according to an embodiment of the present invention.

FIG. 2 is a diagram showing operation waveforms for explaining the operation of the embodiment of the present invention.

FIG. 3 is a diagram showing a circuit configuration of a conventional switching power supply device.

FIG. 4 is a diagram showing operation waveforms for explaining the operation of the conventional technique.

[Explanation of symbols]

M ₁ ~M ₆ MOS transistors T ₁ transformer L ₁ inductance D _5, D ₆ rectifier diodes C ₁ -C ₃ capacitor R ₁ resistance R _L load

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hotaro Umizawa 1 Horiyamashita, Hadano-shi, Kanagawa Hitachi, Ltd. General-purpose computer division (72) Inventor Kazuaki Mohri 1 Horiyamashita, Hadano, Kanagawa Hitachi, Ltd. In computer electronics (72) Inventor Koji Nishisu 1 Horiyamashita, Hadano-shi, Kanagawa Hitachi, Ltd. General-purpose computer division (72) Inventor Hirokazu Maeda 1-horiyamashita, Hadano, Kanagawa Hitachi, Ltd. General-purpose computer business Inside (72) Inventor Kiyoshi Kubota 1 Horiyamashita, Hitachi Ltd., Hadano, Kanagawa General Computer Division, Hitachi Ltd. (72) Inventor Mamoru Yaeshima 1 Horiyamashita, Hadano, Kanagawa Hitachi Ltd. General Computer Division Within (56) References JP-A-7-194107 (JP, A) JP-A-7-107743 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H02M 3/28 H02M 3 / 335

Claims (4)

(57) [Claims] 1. A switching power supply device comprising an inverter provided on the primary side of a transformer, a center tap type full-wave rectifier circuit provided on the secondary side of the transformer, and a smoothing inductance , The rectifying element of the full-wave rectifying circuit is composed of a switching element, and the on-time is maintained during the rectifying operation and while the reflux current of the smoothing inductance flows, and the reflux current is induced to the primary side of the transformer. The switching power supply device is characterized in that the switching power supply device is caused to flow through the switching element that constitutes the inverter. 2. The inverter feeds the transformer
A MOS transistor that periodically inverts the current
Is constituted by Ruburijji circuit, the timing to enter the anti-rolling operation by cutting the return current, MOS transient inversion driving side flyback voltage the transformer may occur
The body diode of the star becomes conductive and the MOS transistor
Switching power supply device according to claim 1, wherein the voltage across the Njisuta is set to a period that is close to 0V. 3. A switching power supply device comprising a transformer, an inverter provided on the primary side of the transformer, a center tap type rectifier circuit provided on the secondary side of the transformer, and an output filter. Has a full bridge configuration including a pair of MOS transistors for switching the high voltage side and another pair of MOS transistors for switching the low voltage side. One of the low-voltage side MOS transistors facing each other via the winding of the transformer is turned on to drive the transformer, and one of the high-voltage side or low-voltage side MOS transistors of the MOS transistors driving the transformer is It is controlled so that it is turned on for a predetermined fixed time, and the other is after the fixed time,
The rectifier circuit is controlled so as to continue to be turned on until the transformer is inverted, and the rectifier circuit is composed of two MOS transistors, and is synchronized with the inverter, and has a predetermined fixed time different from the above. During the period when the MOS transistor is turned on and the MOS transistor of the inverter is turned on for a fixed time, a rectification operation is performed and a current is passed through the output filter, and then the output filter is turned on during the period until the inverter is reversely driven. Continue to flow the reflux current of the constituent inductance, the reflux current is,
A switching power supply device, wherein the switching power supply device is induced through the transformer to a primary side of the transformer and flows into a MOS transistor which is kept in an ON state until the transformer of the inverter is driven to invert. 4. The switching timing of the pair of MOS transistors on the high voltage side is controlled so that one of the MOS transistors is turned on for a fixed time.
The bias voltage applied to the facing MOS transistor is almost 0 V due to the flyback voltage due to the leakage inductance of the transformer connected to the inverter in the time until the facing MOS transistor is turned on after being turned off.
And at the same time, the M of the rectifier circuit is set.
The switching operation of the OS transistor is performed by the inverter
5. The process according to claim 4, which is performed during the switching operation.
The switching power supply described.