JP3439376B2 - Slot machine - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a slot machine gaming machine, and more particularly to a slot machine gaming machine in which the load of a CPU or the like is reduced.

[0002]

2. Description of the Related Art A slot machine game machine is usually provided with a plurality of switches. Then, these switches include a setting switch 80 operated by a clerk in the game hall and a game switch 70 operated by the player. The setting switch 80 includes, for example, a probability setting switch 81 for setting the probability of lottery performed inside the gaming machine.

Further, in the game switch 70, for example, a start switch 71 for variably displaying the three symbols displayed side by side on the symbol variation display device, and three symbols displayed on the symbol variation display device. A first stop switch 72 for stopping and displaying the symbol on the left side, a second stop switch 73 for stopping and displaying the symbol in the center,
The third stop switch 74 for stopping and displaying the symbol on the right side, the first bet switch 75 for inserting one of the gaming medals stored inside the gaming machine, and the same two There is a second bet switch 76 for the purpose, a third bet switch 77 for inserting the same three, a cancel switch 78 for paying out the gaming medals stored inside the gaming machine, and the like.

In the conventional slot machine game machine, as shown in FIG. 5, the probability setting switch 81 has an input port A.
20 is connected to the start switch 71, the first stop switch 72, the second stop switch 73, the third stop switch 74, the first bet switch 75, the second bet switch 76, the third bet switch 77 and the cancel switch. 78 is connected to the input port B30.

In addition, the input port A20 and the input port B30
Are connected to the CPU 10 via an address bus and a data bus. Then, for example, when the player turns on the start switch 71, three symbols of the symbol variable display device are variably displayed, and when the player turns on the first stop switch 72, the symbol variable display device is displayed. The left design is formed so as to be stopped and displayed.

Further, for example, when the player turns on the first stop switch 72 and the second stop switch 73 at the same time when the three symbols of the symbol variable display device are variably displayed, such a switch. The operation is ignored, and it is formed so that the state in which all the symbols of the symbol variable display device are variably displayed is maintained. That is, the number of players is 2
When more than one switch is turned on at the same time, such a switch operation is ignored and the current state is maintained.

Hereinafter, a conventional slot machine game machine will be further described. The input port A20 and the input port B30 are turned on at predetermined time intervals of the connected switches.
The state or OFF state (hereinafter referred to as "ON / OFF state") is replaced with 1 or 0 data (hereinafter referred to as "1/0 data") and latched as 8-bit data.

Further, when the CPU 10 designates the input port A20 via the address bus, it becomes possible to read the 8-bit data latched in the input port A20 via the data bus, and also via the address bus. When the input port B30 is designated by the input, the 8-bit data latched in the input port B30 can be read via the data bus.

For example, the input port B30 latches 1/0 data indicating the ON / OFF state of the first stop switch 72 in correspondence with the 0th bit of 8-bit data. Similarly, the second stop switch 73 to the first bit,
The third stop switch 74 is set to the second bit, the start switch 71 is set to the third bit, the third bet switch 77 is set to the fourth bit, the second bet switch 76 is set to the fifth bit, and the first bet switch 75 is set to the sixth bit. Bit, cancel switch 78
To the 7th bit respectively.

As shown in FIG. 6, when the start switch 71 is in the ON state and all the other switches remain in the OFF state, the states of these switches are "00".
It is replaced with 8-bit data "001000" and latched at the input port B30. Similarly, when the first stop switch 72 is turned on and all the other switches remain off, the states of these switches are replaced with 8-bit data "00000001" and latched. If the start switch 71 and the first stop switch 72 are turned on at the same time and all the other switches remain off, the states of these switches are "00001."
It is replaced with the 8-bit data "001" and latched, and if all the switches are in the OFF state, the status of these switches is replaced with the 8-bit data "00000000" and latched.

When the input port B30 is designated via the address bus, the CPU 10 reads 8-bit data (hereinafter referred to as "input data B") latched at the input port B30 via the data bus. It becomes possible. Then, the CPU 10 collates the input data B read via the data bus with the input data B determination table shown in FIG. 7, and outputs an instruction corresponding to each pattern of the input data B.

For example, when the CPU 10 reads "00001000" as the input data B, the start switch
It is determined that 71 is in the ON state, and a command to variably display the symbols of the symbol variable display device is output. Similarly, when "00000001" is read as the input data B, it is determined that the first stop switch 72 is in the ON state, and a command to stop and display the symbol on the left side of the symbol variable display device is output. , When "00000000" is read as the input data B, it is determined that none of the switches are in the ON state and the current state is maintained, and the input data B is "00001001" or "00".
2 or more switches are turned on when "001111" is read
It judges that it is in the state and ignores the switch operation and maintains the current state.

The CPU 10 reads the input data B, collates the input data B with the input data B determination table, and outputs a command corresponding to each pattern of the input data B. For example, 200μ
It was repeated every second). It should be noted that without providing the input data B judgment table, the CPU 10 is caused to sequentially check whether the bit 0 of the input data B is “0” or “1” so that the instruction corresponding to each pattern of the input data B is issued. It may be output.

In this case, when the CPU 10 obtains the detection result that the 0th bit is "1" and all the other bits are "0", the first stop switch 72 turns off.
It judges that it is in the N state, and outputs a command to stop and display the symbol on the left side of the symbol variable display device. Similarly, when the detection result that the fourth bit is "1" and all the other bits are "0" is obtained, it is determined that the start switch 71 is in the ON state, and the variable display of symbols is displayed. When an instruction to variably display the design of the device is output and a detection result that all bits are "0" is obtained, it is determined that none of the switches is in the ON state and the current state is maintained. Also, two or more bits are "1"
In such a case, at the time when the second "1" is detected, it is determined that two or more switches are in the ON state, the check of the subsequent bits is stopped, and the current state is maintained.

Also in this case, the CPU 10 reads the input data B, sequentially checks the input data B from the 0th bit, and outputs a command corresponding to the detection result. (For example, every 200μ seconds)
Was repeated.

[0016]

However, when causing the CPU to determine the ON / OFF state of each gaming switch and outputting the command corresponding to the state of each gaming switch,
Input data B by reading input data B every predetermined time
However, if the input data B determination table is collated, it takes a long time to collate, and the control program becomes long.

That is, since there are 256 patterns in the 8-bit data, the load on the CPU for collation becomes large, and the processing takes a long time. Also,
Since the input data B determination table also defines 256 patterns, the portion of the control program related to the input data B determination table becomes long.

Also, when the CPU sequentially checks the 0th bit to the 7th bit of the input data B, it takes a long time to judge the state of each switch and output an instruction corresponding to the detection result. However, there is also a problem that the control program becomes long. That is,
Even if the 0th bit is "1" and all the other bits are "0", all the other bits are "0" unless the check up to the 7th bit is completed.
Therefore, it takes a long time to determine the state of each switch and output an instruction corresponding to the detection result. Further, in order to sequentially check the input data B from the 0th bit and output the instruction corresponding to the detection result, since the case determination is often required, the portion related to the case determination of the control program becomes long. It ends up.

Further, although the control program is normally stored in the ROM, the capacity of the ROM is also limited. Therefore, if the portion related to the input data B determination table and the portion related to the case determination in the control program become long, There is also a problem that other parts (for example, a part for controlling the effect device that enhances the interest of the player) have to be shortened.

Then, the load on the CPU is reduced to shorten the processing time, and the control program is shortened to reduce the RO.
There was a request to increase the free space of M. Therefore, the invention described in claim 1 of the present invention indicates whether or not only one of the 8 bit data indicating the ON / OFF state of the eight gaming switches is in the ON state. Provide a circuit to convert to 2-bit data,
The CPU always reads this 2-bit data,
Only when it is determined that only one of the switches is in the ON state, ON / O of the eight game switches
By reading 8-bit data indicating the FF state and determining which switch is in the ON state, the load on the CPU is reduced, the processing time is shortened, and the control program is shortened. R
It is an object of the present invention to provide a slot machine game machine for increasing the free capacity of the OM.

Further, in addition to the object of the invention described in claim 1, the invention described in claim 2 of the present invention is any one of 8-bit data indicating the ON / OFF state of eight gaming switches. By forming a circuit for converting 2-bit data indicating whether or not only one switch is turned on by a combination of a decoder, an AND element, and an OR element, the manufacturing is easy and the manufacturing cost is low. It is an object of the present invention to provide a slot machine game machine capable of keeping the cost low.

The invention described in claim 3 of the present invention is, in addition to the object of the invention described in claim 1 or 2,
The CPU reads 8-bit data indicating the ON / OFF state of the eight game switches only when only one of the switches is in the ON state,
When letting the CPU determine which switch is in the ON state, it is made to sequentially check "0" or "1" from the 0th bit of the 8-bit data, and when "1" is detected, the subsequent steps are performed. An object of the present invention is to provide a slot machine gaming machine that further reduces the load on the CPU and shortens the processing time by canceling the bit check.

Further, in addition to the object of the invention described in claim 1, 2 or 3, the invention described in claim 4 of the present invention is such that the slot machine gaming machine is used as a game switch.
At least a start switch for variably displaying the three symbols displayed on the symbol variable display device, a first stop switch for stopping and displaying the left symbol of the three symbols displayed on the symbol variable display device, the same center 2nd stop switch for stopping and displaying the symbol, a 3rd stop switch for stopping and displaying the symbol on the right side, a bet switch for inserting game medals stored inside the slot machine gaming machine, And a cancel switch for adjusting the gaming medals stored inside the slot machine gaming machine, and the first stop at the 0th bit of the 6-bit data indicating the ON / OFF state of the 6 gaming switches. Switch to the first bit and the second
The stop switch, the third stop switch for the second bit, the start switch for the third bit, the bet switch for the fourth bit, and the cancel switch for the fifth bit are respectively turned on. It is an object of the present invention to provide a slot machine gaming machine that further reduces the load on the CPU and shortens the processing time by first checking the bit corresponding to the frequently used switch.

Further, in addition to the object of the invention described in claim 4, the invention described in claim 5 of the present invention is such that the slot machine gaming machine functions as a bet switch among the stored gaming medals. Equipped with a first bet switch for throwing in one of the two, a second bet switch for throwing in the same two, and a third bet switch for throwing in the same three, and eight game switches are turned on. The 0th bit of the 8-bit data indicating the ON / OFF state is the 1st stop switch, the 1st bit is the 2nd stop switch, the 2nd bit is the 3rd stop switch, and the 3rd bit is the start switch. , The 4th bit is the 3rd bet switch, the 5th bit is the 2nd bet switch, the 6th bit is the 1st bet switch, and the 7th bit is the cancel switch. By response, by checking the bits corresponding to the high frequency of being in the ON state the switch earlier, and an object thereof is to provide a slot machine game machine to shorten the processing time further reduce the burden on the CPU.

[0025]

(Claim 1) The invention according to claim 1 of the present invention, n (n is a natural number of 2 or more) gaming switches (70), and each gaming switch (7
The first input port that latches the ON state or OFF state of 0) as n-bit data and the n-bit data latched in the first input port are read, and an instruction corresponding to each pattern of n-bit data is output. CPU (10)
Is a slot machine gaming machine provided with, and whether the slot machine gaming machine has n-bit data indicating the ON state or the OFF state of each gaming switch (70) in any switch , An interlock circuit (50) for converting to any one of the switches, or an interlock circuit (50) for converting into two bit data indicating whether two or more switches are in the on state, and this two bit data is latched. A second input port for
U (10) reads the 2-bit data latched in the second input port and determines that only one of the n gaming switches (70) is in the ON state. , N-bit data latched in the first input port is read.

Here, the "game switch (70)" means
A switch operated by the player, for example, a start switch (71) for variably displaying the three symbols displayed side by side on the symbol variable display device, the left side of the three symbols displayed on the symbol variable display device Stop switch (72) for stopping and displaying the symbol, the second stop switch (73) for stopping and displaying the symbol in the center, and the third stop switch (74) for stopping and displaying the symbol on the right side ), A first bet switch (7) for inserting one of the gaming medals stored inside the gaming machine
5), the second bet switch (7
6), the third bet switch (7
7), and a switch such as a cancel switch (78) for adjusting the gaming medals stored inside the gaming machine.

The game switch (70) is not limited to the case of eight, but may be four or six. Further, "n-bit data" refers to data represented by a binary number such as 4-bit data, 8-bit data and 16-bit data. For example, if the slot machine gaming machine is equipped with the above eight switches as the gaming switch (70),
Set the ON / OFF state of the first stop switch (72) to 1 /
Replaced with 0 data and made it correspond to the 0th bit.
The ON / OFF state of each other game switch 70 is also changed to 1/0 data to correspond to the 7th bit, so that each game switch (70) is turned ON / OFF.
The state can be indicated by 8-bit data.

In addition, ON / O of each game switch (70)
The replacement of the FF state with 1/0 data can be performed by, for example, the latch circuit (60), but can also be performed by the first input port. When replacing the ON / OFF state of each gaming switch (70) with 1/0 data, the "ON state" may be expressed as "1" and the "OFF state" may be expressed as "0". , "O
The “N state” may be expressed as “0” and the “OFF state” may be expressed as “1”.

Further, the ON / O of the start switch (71)
The 1/0 data indicating the FF state may be associated with the 0th bit, and the 1/0 data indicating the ON / OFF state of the first stop switch (72) may be associated with the 1st bit. That is, ON / OFF of each game switch (70)
The 1/0 data indicating the state is not limited to a specific bit.

If the number of game switches (70) is four, the ON / OFF state of each game switch (70) can be indicated by 4-bit data, and the game switch (70) If the number of 16 is 16, the ON / OFF state of each gaming switch (70) can be indicated by 16-bit data. Also, if the number of gaming switches (70) is 6, the ON / OFF state of each gaming switch (70) can be indicated by 6-bit data, but 2 bits are unused bits and 8 bits. It can also be shown by data.

That is, the number of game switches (70) and the number of bits of data indicating the ON / OFF state of each game switch (70) are not limited. Also, the "first input port" means ON / OF of each game switch (70).
It refers to one that reads and latches n-bit data indicating the F state. Further, when the CPU (10) specifies the first input port via the address bus, it becomes possible to read the n-bit data latched in the first input port via the data bus.

For example, in the case where there are eight gaming switches (70) and data is exchanged between the CPU (10) and the first input port by 8 bits,
The first input port is for turning on eight game switches (70)
Latch 8-bit data indicating the / OFF state, and
CPU (10) is latched at the first input port 8
Read the bit data as it is.

If there are four game switches (70), the ON / OFF state of each game switch (70) can be indicated by 4-bit data.
When data is exchanged with the input port by 8 bits, the first input port reads 4
Bit data is replaced with 8-bit data with 4 bits as unused bits and latched, and CPU (10)
Will read the 8-bit data latched in the first input port. However, since 4 bits of 8-bit data are unused bits, the CPU (10)
Would read the 4-bit data and determine "which switch is in the ON state".

Further, the "interlock circuit (50)" means n-bit data indicating the ON / OFF state of the n game switches (70) "is none of the switches in the ON state"? , A circuit for converting into 2-bit data indicating whether "only one of the switches is turned on" or "two or more switches are turned on".

For example, 2-bit data "00" indicates that "none of the switches are turned on",
"Only one of the switches is in the ON state" is indicated by 2-bit data "11", and "two or more switches are in the ON state" is indicated by 2-bit data "01" be able to. In addition, "no switch is turned on" is indicated by 2-bit data "11", and "any one switch is O
"N state" is indicated by 2-bit data "00", and "two or more switches are in ON state".
This may be indicated by 2-bit data “10”.

Then, such an interlock circuit (50) can be formed by appropriately combining a decoder, an AND element, and an OR element. For example, an interlock circuit (50) for converting 8-bit data into 2-bit data is appropriately combined with two decoders each having four input terminals and 16 output terminals, and an AND element and an OR element. Can be formed by Alternatively, one decoder having eight input terminals and 64 output terminals can be combined with an OR element to form the decoder.

Similarly, an interlock circuit (50) for converting 4-bit data into 2-bit data and an interlock circuit (50) for converting 16-bit data into 2-bit data can be formed. The "second input port" is a port that reads and latches 2-bit data output from the interlock circuit (50).

When the second input port is designated via the address bus, the CPU (10) can read the 2-bit data latched in the second input port via the data bus. For example, when data is exchanged between the CPU (10) and the second input port by 8 bits, the second input port converts the read 2 bit data into 6 bit unused bits. And 8
Bit data is replaced and latched, and CPU (1
0) will read the 8-bit data latched in the second input port. However, since 6 bits of 8-bit data are unused bits, the CPU (1
0) is substantially reading 2-bit data, and "whether any switch is not turned on" or "only one of the switches is turned on",
Alternatively, it is determined whether “two or more switches are turned on”.

As described above, the slot machine gaming machine according to the present invention turns ON / OFF the n game switches (70).
The n-bit data indicating the status is changed to "O
Converted to 2-bit data indicating "not in N state", "only one of the switches is in an ON state", or "two or more switches are in an ON state" An interlock circuit (50) is provided, and the CPU (10) normally reads this 2-bit data, and only when it is determined that only one switch is in the ON state, n games are played. Switch (7
It is formed so as to read "n-bit data" indicating the ON / OFF state of 0) and determine "which switch is in the ON state".

Therefore, it is possible to provide a slot machine game machine which reduces the load on the CPU (10) to shorten the processing time and shortens the control program to increase the free space of the ROM. (Claim 2) Further, in the invention described in claim 2 of the present invention, in addition to the configuration of the invention described in claim 1, the interlock circuit (50) includes a decoder, an AND element and an OR element. It is characterized by being formed by a combination.

As described above, by forming the interlock circuit (50) by the combination of the decoder, the AND element, and the OR element, it is easy to manufacture and the manufacturing cost can be kept low. You can do it. (Claim 3) Further, in the invention described in claim 3 of the present invention, in addition to the configuration of the invention described in claim 1 or 2, the CPU (10) has each game switch (70). ON
When reading the n-bit data indicating the state or the OFF state and determining which switch is in the ON state, the n-bit data is sequentially checked from the 0th bit to indicate that the switch is in the ON state. When the bit is detected, the check of the subsequent bits is stopped.

In this way, when the CPU (10) is made to sequentially check from the 0th bit of the n-bit data to "0" or "1" and the bit indicating that the switch is in the ON state is detected, By stopping the checking of bits thereafter, it is possible to provide a slot machine game machine that further reduces the load on the CPU (10) and shortens the processing time. (Claim 4) Further, in the invention described in claim 4 of the present invention, in addition to the configuration of the invention described in claim 1, 2 or 3, the slot machine game machine has three displayed side by side. Equipped with a symbol variation display device for varying and displaying symbols, the player can play the game by inserting a game medal or by inserting the game medal stored inside the slot machine gaming machine. And, the slot machine game machine, as a game switch (70),
At least a start switch (71) for variably displaying the three symbols displayed on the symbol variable display device, a first stop switch for stopping and displaying the left symbol of the three symbols displayed on the symbol variable display device (72), a second stop switch (7) for stopping and displaying the central symbol of the three symbols displayed on the symbol variable display device
3), a third stop switch (74) for stopping and displaying the symbol on the right side of the three symbols displayed on the symbol variable display device, and inserting the gaming medals stored inside the slot machine gaming machine It has a bet switch and a cancel switch (78) for paying out the gaming medals stored inside the slot machine gaming machine, and the 0th bit of the n-bit data has the first stop switch (72). , A second stop switch (73) for the first bit of the n-bit data, a third stop switch (74) for the second bit of the n-bit data, and a start switch (71) for the third bit of the n-bit data. ), The bet switch corresponds to the fourth bit of the n-bit data, and the cancel switch (78) corresponds to the fifth bit of the n-bit data. To.

As described above, by checking the bit corresponding to the switch that is frequently turned on first, the load on the CPU (10) is further reduced and the processing time is shortened. You can do it. (Claim 5) Further, in the invention described in claim 5 of the present invention, in addition to the configuration of the invention described in claim 4, the slot machine gaming machine is provided as a bet switch inside the slot machine gaming machine. A first bet switch (75) for inserting one of the stored gaming medals, and a first bet switch for inserting two of the gaming medals stored inside the slot machine gaming machine. It is equipped with a 2 bet switch (76) and a 3rd bet switch (77) for throwing in three of the gaming medals stored inside the slot machine gaming machine. Is the first stop switch (72), the first bit of the n-bit data is the second stop switch (73), and the second bit of the n-bit data is the third stop switch (7).
4), the start switch (71) is on the third bit of the n-bit data, the third bet switch (77) is on the fourth bit of the n-bit data, and the second bet is on the fifth bit of the n-bit data. The switch (76) controls the sixth bit of the n-bit data.
The first bet switch (75) corresponds to the bit, and the cancel switch (78) corresponds to the seventh bit of the n-bit data.

As described above, by checking the bit corresponding to the switch that is frequently turned on first, the load on the CPU (10) is further reduced and the processing time is shortened. You can do it.

[0045]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a slot machine gaming machine according to the present invention will be described below with reference to the illustrated examples. FIG. 1 is a block diagram showing a schematic configuration of a slot machine gaming machine according to the present embodiment, FIG. 2 is a conceptual diagram of an interlock circuit, FIG. 3 is a circuit diagram of the interlock circuit, and FIG.
[Fig. 3] is a flowchart showing an outline of the operation of the CPU.

The slot machine gaming machine according to the present embodiment has eight gaming switches 70, a first input port for latching 8-bit data indicating the ON or OFF state of each gaming switch 70, and The CPU 10 reads the 8-bit data latched in the first input port and outputs an instruction corresponding to each pattern of the 8-bit data.

Further, in this slot machine gaming machine, 8-bit data indicating the ON state or OFF state of each gaming switch 70 is not turned ON, or only one of the switches is turned ON. State, or an interlock circuit 50 for converting into 2-bit data indicating whether two or more switches are in the ON state, and a second bit for latching 2-bit data output from the interlock circuit 50 And an input port.

Then, the CPU 10 normally reads the 2-bit data latched in the second input port and determines that only one of the eight gaming switches 70 is in the ON state. Only in this case, the 8-bit data latched in the first input port is read. In this way, this slot machine gaming machine reduces the load on the CPU 10 to shorten the processing time, and shortens the control program to increase the free space in the ROM.

In the present embodiment, the first input port is the input port B30 and the second input port is the input port C40. Hereinafter, the slot machine gaming machine according to the present embodiment will be further described in detail. As shown in FIG. 1, the slot machine gaming machine according to the present embodiment includes a setting switch 80 operated by a store clerk in a game hall and a gaming switch 70 operated by a player.

The setting switch 80 has a probability setting switch 81 for setting the probability of a lottery performed inside the gaming machine. Further, the game switch 70, the start switch 71 for variably displaying the three symbols displayed side by side on the symbol variation display device, the left symbol of the three symbols displayed on the symbol variation display device The first stop switch 72 for stopping and displaying, the second stop switch 73 for stopping and displaying the symbol in the center, the third stop switch 74 for stopping and displaying the symbol on the right side, and stored inside the gaming machine A first bet switch 75 for throwing in one of the playing medals, a second bet switch 76 for throwing in the two medals, a third bet switch 77 for throwing in the three medals, and There is a cancel switch 78 for paying out the gaming medals stored inside the gaming machine.

Further, the probability setting switch 81 is connected to the input port A20, and the start switch 71,
The first stop switch 72, the second stop switch 73, the third stop switch 74, the first bet switch 75, the second bet switch 76, the third bet switch 77 and the cancel switch 78 are connected to the input port B30 via the latch circuit 60. It is also connected to the input port C40 via the latch circuit 60 and the interlock circuit 50.

Input port A20 and input port B30
The input port C40 is connected to the CPU 10 via an address bus and a data bus. (Input port A20) The input port A20 is turned on at every predetermined time (for example, every 200 μsec) of the probability setting switch 81.
The / OFF state is replaced with 1/0 data and latched as 8-bit data.

This input port A20 is a probability setting switch
The 1/0 data indicating the ON / OFF state of 81 is latched in correspondence with the 0th bit of the 8-bit data. Further, the first bit to the seventh bit are unused. Therefore, if the probability setting switch 81 is turned on, this state is replaced with 8-bit data "00000001" and latched. If the probability setting switch 81 remains in the off state, this state is " 0
It is replaced with 8-bit data "0000000" and latched.

When the input port A20 is designated via the address bus, the CPU 10 reads 8-bit data latched in the input port A20 (hereinafter referred to as "input data A") via the data bus. It will be possible. (Latch circuit 60) Further, the latch circuit 60 includes a start switch 71, a first stop switch 72, a second stop switch 73, a third stop switch 74, a first bet switch 75, a second bet switch 76, and a third bet. The ON / OFF state of each of the switch 77 and the cancel switch 78 at every predetermined time (for example, every 200 μsec) is replaced with 1/0 data and latched as 8-bit data.

The latch circuit 60 latches 1/0 data indicating the ON / OFF state of the first stop switch 72 in correspondence with the 0th bit of 8-bit data. Similarly, the second stop switch 73 is set to the first bit, the third stop switch 74 is set to the second bit, the start switch 71 is set to 3 bits, the third bet switch 77 is set to the fourth bit, and the second bet switch 76 is set. The 5th bit corresponds to the 1st bet switch 75 to the 6th bit, and the cancel switch 78 corresponds to the 7th bit.

For example, if the first stop switch 72 is in the ON state and all other switches remain in the OFF state, the states of these switches are "00000".
It is replaced with 8-bit data "001" and latched. Further, when the start switch 71 and the first stop switch 72 are turned on at the same time and all the other switches are still turned off, the states of these switches are replaced with 8-bit data "00001001". Be latched.

Further, when all the switches remain in the OFF state, the states of these switches are "000000".
It is replaced with 8-bit data "00" and latched. Then, the latch circuit 60 outputs the latched 8-bit data every predetermined time (for example, every 200 μsec).
Output to the input port B30 and the interlock circuit 50. (Input Port B30) Further, the input port B30 reads and latches the 8-bit data from the above-mentioned latch circuit 60 every predetermined time (for example, every 200 μsec).

Since the input port B30 reads the 8-bit data from the latch circuit 60 described above in parallel,
The 0th bit of the 8-bit data latched by the input port B30 indicates the ON / OFF state of the first stop switch 72. Similarly, the first bit is the second stop switch
73, the second bit is the state of the third stop switch 74, the third bit is the state of the start switch 71,
The bit indicates the state of the third bet switch 77, the fifth bit indicates the state of the second bet switch 76, the sixth bit indicates the state of the first bet switch 75, and the seventh bit indicates the state of the cancel switch 78. .

When the input port B30 is designated via the address bus, the CPU 10 reads 8-bit data latched in the input port B30 (hereinafter referred to as "input data B") via the data bus. It will be possible. (Interlock circuit 50) In addition, the interlock circuit 50 uses the 8-bit data from the latch circuit 60 described above,
That is, the start switch 71, the first stop switch 72,
O of each of the second stop switch 73, the third stop switch 74, the first bet switch 75, the second bet switch 76, the third bet switch 77, and the cancel switch 78.
The 8-bit data indicating the N / OFF state is read every predetermined time (for example, every 200 μsec), and
The bit data is set to "no switch is turned on", "any one switch is turned on", or "two or more switches are turned on". Is converted to 2-bit data.

The interlock circuit 50 will be described in detail below. As shown in FIG. 2, the interlock circuit 50 has eight input terminals (from input terminal A to input terminal H) for reading the 8-bit data from the latch circuit 60 in parallel. It has two output terminals (output terminal X and output terminal Y) for outputting 2-bit data in parallel.

In the drawings, A is the input terminal A, B is the input terminal B, C is the input terminal C, D is the input terminal D, and E is
Is the input terminal E, F is the input terminal F, G is the input terminal G
, H indicates the input terminal H, X indicates the output terminal X, and Y indicates the output terminal Y, respectively. 8-bit data from the above-mentioned latch circuit 60 is input in parallel to the input terminal.

For example, the 0th bit of 8-bit data is input to the input terminal A. Similarly, the input terminal B has the first bit, the input terminal C has the second bit, and the input terminal D has the second bit.
To the input terminal E, the fourth bit, the input terminal F, the fifth bit, the input terminal G, the sixth bit, and the input terminal H, the seventh bit. It

From the output terminal, whether any of the eight gaming switches 70 is "ON", or "only one of the switches is ON". , Or 2-bit data indicating that “two or more switches are turned on” is output. For example, when "none of the switches are turned on", 2-bit data "00" is output. That is, both output terminals X and Y are "0".
Is output.

In addition, "only one of the switches is O
In the case of "N state", 2-bit data "1"
1 ”is output. That is, “1” is output from both the output terminal X and the output terminal Y. Further, when "two or more switches are turned on", 2-bit data "01" is output. That is, “1” is output from the output terminal X, and “0” is output from the output terminal Y.

Then, such an interlock circuit 50
Can be formed by, for example, appropriately combining a decoder, an AND element, and an OR element as shown in FIG. In the drawings, D1 and D2 are decoders, A1, A2 and A3 are AND elements, and O1, O2 and O3 are OR elements.

Decoder D1 and decoder D2 shown in FIG.
Has four input terminals from input terminal α to input terminal δ and 16 output terminals from output terminal a to output terminal p. The decoder D1 and the decoder D2
For example, when 4-bit data “0001” is input, 16-bit data “01000000000000” is input.
00 ”is output. That is, when “1” is input only to the input terminal α, “1” is output only from the output terminal o. Similarly, when 4-bit data “0010” is input, 1
6-bit data "0010000000000000"
When the 4-bit data “1111” is input, the 16-bit data “000000000000” is output.
"0001" is output, and 4-bit data "000" is output.
When "0" is input, 16-bit data "100000"
"0000000000" is output.

The decoder D1 and the decoder D
2 by using the output terminal h, the output terminal 1, the output terminal n, and the output terminal o of the input terminal α to the input terminal δ.
It is possible to detect that "1" has been input to only one of the above, and by using the output terminal p, "1" is input to any of the input terminals α to δ. It can detect that it was not done.

Further, as shown in FIG. 3, this decoder D
1 and the decoder D2 are used, and the AND element and the OR are used.
By properly combining the elements, the 8-bit data indicating the ON / OFF state of each of the eight gaming switches 70 is changed to "no switch is turned on" or "only one of the switches is turned on". It can be converted into 2-bit data indicating whether it is "ON state" or "two or more switches are ON state".

For example, when "1" is input only to the input terminal A, "1" is output from the output terminal X and "1" is also output from the output terminal Y. That is, when the 8-bit data “00000001” is input, the 2-bit data “11” is output. Further, even if "1" is input only to the input terminal E, "1" is output from the output terminal X, and
"1" is also output from the output terminal Y. That is, even if the 8-bit data “00010000” is input, the 2-bit data “11” is output.

Also, "1" is applied to the input terminals A and B.
Is input and "0" is input to all the other input terminals, "1" is output from the output terminal X and "0" is output from the output terminal Y. That is, when the 8-bit data “00000011” is input, the 2-bit data “01” is output. Further, even if "1" is input to the input terminal A and the input terminal E and "0" is input to all the other input terminals, "1" is output from the output terminal X and output. "0" is output from the terminal Y. That is,
Even if 8-bit data "00010001" is input,
2-bit data "01" is output.

When "1" is not input to any of the input terminals A to H, "0" is output from the output terminal X and "0" is output from Y as well. That is, when the 8-bit data “00000000” is input, the 2-bit data “00” is output. In this way, the interlock circuit 50 changes the 8-bit data indicating the ON / OFF state of each of the eight gaming switches 70 to "no switch is in the ON state".
Alternatively, it can be converted into 2-bit data indicating "only one of the switches is turned on" or "two or more switches are turned on".

The interlock circuit 50 is not limited to the one formed by the combination of the decoder, AND element, and OR element shown in FIG. 3, and although not shown, for example, 8 input terminals and 64 A decoder having an output terminal and an O having eight input terminals and one output terminal
It can also be formed by combining with an R element. (Input Port C40) Also, the input port C40 is 2 bit data from the interlock circuit 50 described above, that is, "no switch is turned on" among the eight gaming switches 70, 2-bit data indicating "only one of the switches is in the ON state" or "two or more switches are in the ON state" at predetermined time intervals (for example, every 200 μsec) Read and latch as 8-bit data.

The input port C40 reads the 2-bit data from the interlock circuit 50 in parallel and outputs the 1/0 data output from the output terminal X to the 0th bit and the output terminal Y. 1/0 data corresponding to the first bit is latched. In addition, the second bit to the seventh bit are unused.

Therefore, of the eight gaming switches 70, "when none of the switches are turned on",
The 8-bit data "00000000" is latched at the input port C40. In addition, when "only one of the switches is turned on" among the eight game switches 70, "0
8-bit data "0000011" is latched.

In addition, of the eight game switches 70, "2
When more than one switch is in the ON state ”, 8-bit data“ 00000001 ”is latched at the input port C40. When the input port C40 is designated via the address bus, the CPU 10 can read 8-bit data latched in the input port C40 (hereinafter referred to as "input data C") via the data bus. become. (Operation of CPU 10) Next, an outline of the operation of the CPU 10 will be described with reference to the flow chart shown in FIG.

First, the CPU 10 reads the input data C (S100), and either "none of the switches is turned on" out of the eight gaming switches 70 or "only one of the switches is turned on". It is determined whether it is in the "state" or "two or more switches are in the ON state" (S110). Then, when it is determined that "none of the switches are turned on" or "two or more switches are turned on",
After a lapse of a predetermined time (for example, after 200 μs has elapsed), the input data C is read again (S100), and “either switch is not turned on” or “only one switch is turned on”. Has been done "or" 2
It is determined whether or not more than one switch has been turned on ”(S110).

In addition, "only one of the switches is O
If it is determined that the "N state" is set, the input data B is read next (S120), and "which switch is ON".
Whether it is in a state ”is determined and a predetermined command is output (S130). For example, when it is determined that the start switch 71 is in the ON state, a command to variably display the three symbols displayed on the symbol variable display device is output.

When it is determined that the first stop switch 72 is in the ON state, a command to stop and display the left symbol of the three symbols displayed on the symbol variable display device is output. Then, after outputting a predetermined command corresponding to the switch in the ON state (S130), the input data C is read again (S100), and "no switch is in the ON state" or " Only one of the switches is in the ON state ", or" two or more switches are in the ON state ".
Whether or not is determined (S120).

Here, the CPU 10 reads "input data C,""no switch is turned on" or "only one of the switches is O."
Judgment of "is in the N state" or "two or more switches are in the ON state", and judgment of "which switch is in the ON state" by reading the input data B Will be described in more detail.

First, the CPU 10 reads the input data C "no switch is turned on", "only one switch is turned on", or "two switches are turned on". The determination of whether the above switches are in the ON state will be described. Since the input data C is always "0" from the 2nd bit to the 7th bit, the CPU 10 has the 0th bit and the 1st bit.
Only the bits need to be checked.

That is, the CPU 10 substantially reads 2-bit data, and "either switch is not turned on" or "only one switch is turned on".
It is determined whether or not it is in the "state" or "two or more switches are in the ON state". Then, as the procedure, first, the CPU 10 is made to sequentially check the 0th bit and the 1st bit.

If the 0th bit is "1" and the first bit is also "1", then the CPU
Read the input data B into 10. When the 0th bit is “1” and the 1st bit is “0”,
Alternatively, when the 0th bit is “0” and the 1st bit is also “0”, the input data C is input to the CPU 10 again.
To read.

The 8-bit data "0000001"
1 "," 00000001 "and" 00000000 "
It is also possible to provide a table corresponding to the above in advance and have the CPU 10 collate the table with the input data C. In addition,
In the present embodiment, the interlock circuit described above is used.
Since 50 does not output 2-bit data "10", the case where the 0th bit is "0" and the 1st bit is "1" is not considered.

Next, the determination of "which switch is turned on" by the CPU 10 reading the input data B will be described. The CPU 10 reads the input data B when "only one of the eight switches 70 is in the ON state" out of the eight game switches 70, that is, any one of the 8-bit data of the input data B Since it is limited to the case where only one bit is "1", the CPU 10 only needs to check what number bit is "1".

As the procedure, first, the CPU
Check the 0th bit in 10 and if "1" is detected in the 0th bit, stop checking the 1st bit and thereafter, and the symbol on the left side of the three symbols displayed on the symbol variation display device. Stop display. If "0" is detected in the 0th bit, then the CPU 10 is caused to check the 1st bit.

Further, the CPU 10 is made to check the first bit, and when "1" is detected in the first bit, the check after the second bit is stopped, and the three symbols displayed on the symbol variation display device. The central design is stopped and displayed. If "0" is detected in the first bit, then the CPU 10 is caused to check the second bit. Also, C
PU10 to check the second bit, when "1" is detected in the second bit, stop checking the third bit and after, and the symbol on the right side of the three symbols displayed on the symbol variation display device Stop display. If "0" is detected in the second bit, then the CPU 10
Check bits.

Further, the CPU 10 is made to check the third bit, and when "1" is detected in the third bit, the check after the fourth bit is stopped, and the three symbols displayed on the symbol variation display device. Is variably displayed. When "0" is detected in the 3rd bit, the CPU 10 next receives the 4th bit.
Check bits. Further, when the CPU 10 is made to check the 4th bit and "1" is detected in the 4th bit, the check after the 5th bit is stopped, and among the gaming medals stored inside the gaming machine. Insert 3 sheets. When "0" is detected in the 4th bit,
Next, the CPU 10 is made to check the fifth bit.

If the CPU 10 is made to check the 5th bit and "1" is detected in the 5th bit, the check of the 6th bit and thereafter is stopped, and the game is stored inside the gaming machine. Insert two of the medals. Also,
If "0" is detected in the fifth bit, then the CPU
Let 10 check the 6th bit. Further, when the CPU 10 is made to check the 6th bit and "1" is detected in the 6th bit, the check of the 7th bit is stopped, and among the gaming medals stored inside the gaming machine. Insert one. When "0" is detected in the 6th bit, the CPU 10 is made to check the 7th bit next.

When the CPU 10 checks the seventh bit, the gaming medals stored inside the gaming machine are settled. In addition, 8-bit data "000000
01 "," 00000010 "," 0000010 "
0 "," 00001000 "," 00010000 ",
"001000000", "01000000" and "1"
A table corresponding to "0000000" may be provided in advance, and the CPU 10 may collate this table with the input data B.

As described above, the slot machine gaming machine according to the present embodiment is ON / OF of eight gaming switches 70.
The 8-bit data indicating the F state is set to "none of the switches are turned on", "only one of the switches is turned on", or "two or more switches are turned on". It is equipped with an interlock circuit 50 for converting into 2 bit data indicating whether or not the data is stored. Also, the CPU 10 always reads this 2 bit data and judges that only one of the switches is in the ON state. Only when you do, O of eight game switches 70
It is formed so that 8-bit data indicating the N / OFF state is read to determine "which switch is in the ON state".

By operating the CPU 10 as described above, the load on the CPU 10 is reduced, the processing time is shortened, and the control program is shortened.
The free space of M can be increased. Further, in the slot machine gaming machine according to the present embodiment, the interlock circuit 50 is formed by the combination of the decoder, the AND element, and the OR element, so that the manufacturing is easy and the manufacturing cost can be kept low. You can do it.

Further, in the slot machine gaming machine according to the present embodiment, the CPU 10 turns on the eight gaming switches 70.
When reading the 8-bit data indicating the ON / OFF state and determining which switch is in the ON state, it is sequentially checked from the 0th bit of the 8-bit data whether it is “0” or “1”. Since it is formed so that the checking of the bits thereafter is stopped when "1" is detected, the load on the CPU 10 can be further reduced and the processing time can be shortened.

Further, in the slot machine gaming machine according to the present embodiment, the first stop switch 72 is set to the 0th bit of the 8-bit data indicating the ON / OFF state of the game switch 70, and the first bit is set to the 1st bit. The 2 stop switch 73, the 3rd stop switch 74 for the 2nd bit, the start switch 71 for the 3rd bit, the 3rd bet switch 77 for the 4th bit, and the 2nd bet switch 76 for the 5th bit. To
Since the first bet switch 75 is associated with the sixth bit and the cancel switch 78 is associated with the seventh bit, the bit corresponding to the switch that is frequently turned on is checked first. The load on the CPU 10 can be further reduced and the processing time can be shortened.

In the above embodiment, one of the stored gaming medals is used as a bet switch.
A slot machine provided with a first bet switch 75 for throwing in two coins, a second bet switch 76 for throwing in two coins, and a third bet switch 77 for throwing in three coins I have shown a gaming machine, but one for loading one
Slot machine gaming machine equipped with only one bet switch,
Or a one bet switch for throwing one,
It is also possible to use a slot machine gaming machine provided with two, a maximum bet switch and a maximum bet switch for inputting the maximum number that can be inserted.

Here, in the slot machine game machine provided with only the one bet switch, it is possible to form a plurality of game medals by pushing the one bet switch a predetermined number of times. Further, even in a slot machine gaming machine equipped with two bet switches, a one bet switch and a MAX bet switch, it is possible to insert a plurality of game medals by pressing the one bet switch a predetermined number of times. can do.

Furthermore, the present invention can be applied to such a slot machine game machine. That is, the latch circuit 60 is 6-bit data indicating the ON / OFF state of 6 gaming switches, or 7-bit data indicating the ON / OFF state of 7 gaming switches, 2 bits,
Alternatively, it is latched as 8-bit data in which 1 bit is an unused bit.

The input port B30 latches 8-bit data (substantially 6-bit data or 7-bit data) from the latch circuit 60. Further, the interlock circuit 50 converts the 8-bit data (substantially 6-bit data or 7-bit data) from the latch circuit 60 into predetermined 2-bit data.

Further, the input port C40 latches the predetermined 2-bit data output from the interlock circuit 50 as 8-bit data having 6 bits as unused bits. Then, the CPU 10 always reads the 8-bit data (substantially 2-bit data) latched in the input port C40, and only when it judges that only one of the switches is in the ON state, Input port B30
The 8-bit data (substantially 6-bit data or 7-bit data) latched in is read to determine "which switch is in the ON state".

Further, in the slot machine game machine provided with only one bet switch, the first stop switch 72 is at the 0th bit of the 8-bit data latched at the input port B30, and the second stop switch is at the 1st bit. 73,
The third stop switch 74 is associated with the second bit, the start switch 71 is associated with the third bit, the single bet switch is associated with the fourth bit, and the cancel switch 78 is associated with the fifth bit. It is possible to have the bit corresponding to the switch that is frequently put in the state checked first.

Also in the slot machine game machine having two bet switches, one bet switch and the MAX bet switch, the first stop switch 72 is set to the 0th bit of the 8-bit data latched at the input port B30.
, The second stop switch 73 for the first bit, the third stop switch 74 for the second bit, the start switch 71 for the third bit, the MAX bet switch for the fourth bit,
By making the 5th bit correspond to the 1-sheet bet switch and the 6th bit correspond to the cancel switch 78,
The CPU 10 can first check the bit corresponding to the switch that is frequently turned on.

In this way, as a bet switch, a slot machine gaming machine provided with only one bet switch for throwing one, or a one bet switch for throwing one, can be turned on. Even in a slot machine game machine provided with two MAX bet switches for throwing in the maximum number of cards, by using the present invention, the load on the CPU 10 can be reduced, the processing time can be shortened, and the control program can be changed. This can be shortened to increase the free space in the ROM.

[0102]

As described above, according to the invention described in claim 1, the slot machine gaming machine displays the n-bit data indicating the ON / OFF state of the n gaming switches as "any switch. Is not turned on. "
CPU provided with an interlock circuit for converting into 2-bit data indicating whether "only one of the switches is turned on" or "two or more switches are turned on" Always reads this 2-bit data, and only when it determines that only one switch is in the ON state, it reads the n-bit data and determines "which switch is in the ON state". To do.

Therefore, the load on the CPU is reduced to shorten the processing time, and the control program is shortened to reduce the RO.
It is possible to provide a slot machine gaming machine that increases the free capacity of M. According to the invention described in claim 2, the interlock circuit includes a decoder and an AN.
Since it is formed by the combination of the D element and the OR element, it is possible to provide a slot machine gaming machine which is easy to manufacture and whose manufacturing cost is kept low.

According to the invention described in claim 3,
When the CPU reads the n-bit data and determines which switch is in the ON state, the n-bit data is sequentially checked from the 0th bit and the switch is turned ON.
When the bit indicating the state is detected, the check of the subsequent bits is stopped, so that it is possible to provide the slot machine game machine which further reduces the load on the CPU and shortens the processing time. .

According to the invention described in claim 4,
The 0th bit of the n-bit data has the 1st stop switch, the 1st bit has the 2nd stop switch, the 2nd bit has the 3rd stop switch, the 3rd bit has the start switch, and the 4th bit. Bet switch is the 5th
Since the cancel switch corresponds to each bit, the CPU first checks the bit corresponding to the switch that is frequently turned on, so that C
It is possible to provide a slot machine game machine that further reduces the load on the PU and shortens the processing time.

According to the invention described in claim 5,
The 0th bit of the n-bit data has the 1st stop switch, the 1st bit has the 2nd stop switch, the 2nd bit has the 3rd stop switch, the 3rd bit has the start switch, and the 4th bit. Is the third bet switch,
The second bet switch corresponds to the fifth bit, the first bet switch corresponds to the sixth bit, and the cancel switch corresponds to the seventh bit.
Since the bit corresponding to the switch that is frequently turned on is checked first, it is possible to provide a slot machine game machine that further reduces the load on the CPU and shortens the processing time.

[Brief description of drawings]

FIG. 1 is a block diagram showing an outline of a configuration of a slot machine gaming machine according to the present embodiment.

FIG. 2 is a conceptual diagram of a latch circuit, an interlock circuit, and an input port C.

FIG. 3 is a circuit diagram of an interlock circuit.

FIG. 4 is a flowchart showing the outline of the operation of the CPU.

FIG. 5 is a block diagram showing a schematic configuration of a conventional slot machine gaming machine.

FIG. 6 is a conceptual diagram of a conventional input port B.

FIG. 7 is a conceptual diagram of an input data B determination table.

[Explanation of symbols]

10 CPU 20 Input port A 30 Input port B 40 Input port C 50 interlock circuit 60 Latch circuit 70 Game switch 71 Start switch 72 1st stop switch 73 Second stop switch 74 3rd stop switch 75 First Bet Switch 76 Second bet switch 77 Third Bet Switch 78 Cancel switch 80 setting switch 81 Probability setting switch

Claims (5)

(57) [Claims] 1. An n-number (n is a natural number of 2 or more) gaming switch, a first input port for latching an ON state or an OFF state of each gaming switch as n-bit data,
A slot machine gaming machine provided with a CPU that reads n-bit data latched in the first input port and outputs an instruction corresponding to each pattern of n-bit data. ON of the game switch
Whether n-bit data indicating the state or the OFF state is not turned on by any switch, only one switch is turned on, or two or more switches are turned on. And a second input port for latching the 2-bit data, wherein the CPU reads the 2-bit data latched in the second input port and A slot machine gaming machine characterized by reading n-bit data latched in a first input port when it is determined that only one of the gaming switches is turned on. 2. The interlock circuit comprises a decoder and an AN.
The slot machine gaming machine according to claim 1, wherein the slot machine gaming machine is formed by a combination of a D element and an OR element. 3. The CPU reads n-bit data indicating an ON state or an OFF state of each game switch, and when determining which switch is in the ON state,
3. The n-bit data is sequentially checked from the 0th bit, and when the bit indicating that the switch is in the ON state is detected, the check of the subsequent bits is stopped. Slot machine game machine. 4. The slot machine gaming machine is provided with a symbol variation display device for variably displaying three symbols displayed side by side, and by the player inserting a game medal,
Alternatively, the player can play the game by inserting game medals stored inside the slot machine game machine, and the slot machine game machine is used as a game switch.
At least a start switch for variably displaying the three symbols displayed on the symbol variation display device, a first stop switch for stopping and displaying the left symbol of the three symbols displayed on the symbol variation display device, a symbol variation Of the three symbols displayed on the display device, a second stop switch for stopping and displaying the central symbol, and a third stop for stopping and displaying the right symbol of the three symbols displayed on the symbol variable display device A switch, a bet switch for inserting the gaming medals stored inside the slot machine gaming machine, and a cancel switch for adjusting the gaming medals stored inside the slot machine gaming machine; The first stop switch is for the 0th bit of bit data and the second stop switch is for the 1st bit of n-bit data. Switch, the third stop switch for the second bit of the n-bit data, the start switch for the third bit of the n-bit data, the bet switch for the fourth bit of the n-bit data, and the fifth switch of the n-bit data. The slot machine gaming machine according to claim 1, 2 or 3, wherein a cancel switch corresponds to each bit. 5. The slot machine gaming machine, as a bet switch, a first bet switch for inserting one of the gaming medals stored inside the slot machine gaming machine, and the inside of the slot machine gaming machine. A second bet switch for inserting two of the game medals stored in the slot machine, and a third bet for inserting three of the game medals stored in the slot machine gaming machine. A bet switch is provided, wherein the 0th bit of the n-bit data has a first stop switch, the first bit of the n-bit data has a second stop switch, and the second bit of the n-bit data has a third stop switch. The start switch is on the third bit of the n-bit data, the third bet switch is on the fourth bit of the n-bit data, and the fifth bit of the n-bit data. The is the second bet switch, the sixth bit of the n bit data 1
The slot machine game machine according to claim 4, wherein the bet switch corresponds to the seventh bit of the n-bit data, and the cancel switch corresponds to the seventh bit.