JP3450438B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a charge storage layer and a control gate.
Electrically rewritable memory having a structure in which
Nonvolatile semiconductor memory device using memory cells (EEPRO
M) and other semiconductor devices and MOS transistors
You. [0002] 2. Description of the Related Art Conventionally, semiconductor devices such as EEPR
FIGS. 28 and 2 show that the OM can be highly integrated.
NAN in which a plurality of memory cells as shown in FIG. 9 are connected in series
D-cell type EEPROMs are known. FIG.
29 is a plan view of the ND cell type EEPROM, and FIG.
(A) and (b) are AA 'and BB' in FIG. 28, respectively.
It is sectional drawing. In this device, the memory cell is an n-type semiconductor
SiO 2 is formed on a P-type well provided on the substrate 1._Two Etc. Tunnel
Floating gates 41, 42, 43, 44 via
And a control gate in which control gates 61, 62, 63 and 64 are stacked.
Has a gate structure, and a plurality of memory cells are adjacent
Connected in series by sharing source and drain 9
Of the NAND cell. And like this
Memory cells are arranged in a matrix
Rays are configured. [0003] A NAND cell array is arranged in the column direction of a cell array.
The drains on one end are connected to select gates 45 and 65, respectively.
Connected to bit line 8 via select transistor
The source at the other end also has select gates 46 and 66
To the common source line 9 via the select transistor
It is connected. Control gates 41-44 of memory cells and
And select gates 45 and 46 are connected in the row direction of the memory cell array.
Control gate line (word line), select gate line and
Connected in common. Also, select gates 45, 65 and 4
6, 66 are respectively electrically connected.
You. The operation of this NAND cell type EEPROM is as follows.
It is as follows. Writing data is far from the bit line
It is performed in order from the memory cell of one side. In case of n channels
For example, a memory cell to be written (write cell)
High potential Vpp (for example, 20 V) is marked on the control gate 6 of FIG.
Should not be written further on the bit line side
(Non-written cell) control gate 6 and select gate 45,
65 has an intermediate potential V_MG(For example, 10 V) is applied.
0 V (for example, data
"1") or the intermediate potential V_Mbit(Eg de
(Defined as data "0"). At this time, the potential of the bit line 8 is
Through the select transistor on the side and the unwritten cell.
To the drain of the embedded cell. Write
Intermediate potential V_MbitIs applied. write
Write when there is data to be used (when data is "1")
A high electric field is applied between the gate and drain of the
Whole channel or drain formed in well 2 of
To the floating gate through the tunnel insulating film 3
Flannel injection. As a result, the threshold value of the write cell
Moves forward. When there is no data to write
(At the time of “0” data), there is no threshold change. [0006] Data erasure is performed on an n-type substrate and the substrate.
High potential is applied to the p-type wells
The control gate and select gate of the memory are set to 0V. This
As a result, floating gates in all or some memory cells
The electrons of the heat are transferred to the well of the substrate 1 through the tunnel insulating film 3.
2 and the threshold moves in the negative direction. [0007] Data reading is performed by a selector transistor and
From the memory cell to be read (read cell)
Memory cells that should not be read (non-read cells)
It is turned on, and 0 V is applied to the gate of the read cell.
At this time, by reading the current flowing through the bit line,
Data "0" and "1" are determined. [0008] In the conventional EEPROM, as described above,
A high electric field is applied to the tunnel insulating film 3 to make electrons Fow.
flowing as ler-Nordheim tunnel current
Is writing / erasing. Apply this electric field and
When a tunnel current flows, the tunnel insulating film 3 becomes a carrier.
(Electron, hole) trap
Slaking occurred, and furthermore, dielectric breakdown occurred. This poor
Phenomena, E^Two Number of programming / erasing of PROM cell
Is usually 10^Five Times and the tunnel oxide film
Thinning is also hindered. Such a problem is caused by the fact that a memory cell
Not only the NAND type EEPROM but also the memory cell
Tunneling voltage that applies a high electric field between the drain and the floating gate
EEPROM using current or between source and drain
By hot electron injection using potential difference of
In the EEPROM which performs the operation, the tunnel insulating film is used locally.
This is particularly noticeable because In addition, floating
Not only for gate type EEPROM, but also for oxide film and nitride film
Carrier trapping by different types of laminated films
Configure the area. It is also a problem in so-called MNOS
You. [0010] SUMMARY OF THE INVENTION As described above, the EEPR
In OM, a high level is applied to the tunnel insulating film during writing / erasing.
A voltage is applied and the carrier traps
And the characteristics of the film deteriorated. The present invention has been made in view of the above circumstances.
The purpose is ton / write
High performance and high reliability can be operated without deterioration of the tunnel insulating film
To provide an EEPROM cell. [0012] An EEPROM memory according to the present invention is provided.
The molycell is a part where a high voltage is applied and a tunnel current flows.
Remove the film, fill with vacuum or gas, and
No topping occurs. That is, it is deteriorated by writing / erasing.
It is characterized by being constituted by a non-film. [0013] According to the present invention, the tunnel current at the time of writing / erasing is
Traps in the insulating film caused by vacuum or vacuum
An EEPROM cell that does not degrade and does not generate gas
Can provide. [0014] Embodiments of the present invention will be described below with reference to the drawings.
I do. FIG. 1 shows a NAND cell according to an embodiment of the present invention.
Is a layout showing NAND cells of a type EEPROM.
2 and 3 are AA 'and BB' of FIG. 1, respectively.
FIG. 4 is a sectional view, and FIG. 4 is an equivalent circuit of a NAND cell array.
is there. In this embodiment, four memory cells M1 to M1
M4 and two select transistors S1 and S2
These source and drain diffusion layers are shared between adjacent ones
In this way, the NAND cells are connected in series to form a NAND cell.
Such NAND cells are arranged in a matrix and
Ray is configured. The drain at one end of the memory cells connected in series
IN is a select transistor having a select gate SG1
S1 is connected to the bit line BL1 via the
Is a select transistor S having a select gate SG2.
2 is connected to the ground line. Control of each memory cell
The control gates CG1 to CG4 are continuously connected to the bit lines.
And become a word line. In this embodiment, four menus are used.
A memory cell constitutes a NAND cell.ⁿ
One NAND cell can be composed of memory cells
it can. FIGS. 2 and 3 show a specific memory cell structure.
A more detailed description will be given. In this embodiment, the n-type silicon substrate 10 is
The substrate 10 is used to form a p-type well 11,
Cell array is formed in the p-type well 11 of FIG.
A silicon substrate n-type well and p-type well may be formed.
Absent. Peripheral circuits are formed separately from the cell array area
Formed in p-type and n-type wells. As a NAND cell, a p-type well 11
Element isolation oxide film 12 is formed by trench element isolation method
The element region surrounded by the element isolation oxide film 12
The floating gate 14 (14₁ ~ 14_Four )
Is formed thereon, and is controlled via a second gate oxide film 15.
Your gate 16 (16₁ ~ 16_Four ) Is formed. true
The space is 3 to 20 nm / thick, and the second gate oxide film
15 is a thermal oxide film or silicon nitride of 10 to 40 nm
Film or a stacked film of silicon oxide film and silicon nitride film
is there. In addition, the floating gate 14 has a first width of 50 to 400 nm.
The control gate 16 is formed of polycrystalline silicon
Formed by a second layer polycrystalline silicon having a thickness of 100 to 400 nm.
It is. N-type diffusion to be the source and drain of each memory cell
Layer 17 has four memories shared by adjacent ones
Cells are connected in series. Gate and diffusion layer formed
The substrate is covered with a CVD insulating film 18 and a bit
A line 19 is provided. Part of two select gates SG1 and SG2
Means that the thickness of the gate oxide film 20 is 10 to 40 nm,
It is formed thicker than the vacuum part of the cell part. Gate electrode 1
4_Five , 14₆ Is the same first-layer polycrystalline silicon as the floating gate 14.
It is formed using a capacitor film. And control gate 1
6. Wiring formed of the same second-layer polycrystalline silicon film as in 6.
16_Five , 16₆ , Are gate electrodes 14_Five , 14₆ On top of
Formed and the gate electrode 14_Five , 14₆ Connected to
You. The floating gate 14 of each memory cell and the control gate
16 and the select gate electrode 14 of the select transistor
_Five , 14₆ And wiring 16_Five , 16₆ Is in the gate length direction
Simultaneously patterned using the same etching mask
ing. And an n-type layer serving as a source / drain diffusion layer
Reference numeral 17 denotes a mask using these gate electrodes and wirings as masks.
It is formed by ion implantation of elemental or phosphorus. The control gate 6 of the memory cell is shown in FIG.
As shown in FIG.
Pattern to be used for the capacitance of the gate 14 and the control gate 16
Is formed. Control gate 14 of memory cell and substrate 1
0 between the capacitance C1 and the floating gate 14 and the control gate 16
The capacity C2 will be described with reference to specific numerical examples.
Floating gate 14 and control gate 1 according to the 1 μm rule
6 is 1 μm in width and 1 μm in channel length. Also floating game
The height of the side wall of the gate 14 is 0.5 μm. Vacuum thickness
Is 10 nm, and the second gate oxide film 15 is 25 nm.
Assuming that the dielectric constant of the thermal oxide film is ε, the coupling capacitances C1 and C2 are
Respectively, [0022] (Equation 1) That is, the capacitive coupling ratio C_R Is [0023] (Equation 2) This is the conventional SiO_Two Compared with tunnel oxide film
Then, the partial capacitance of the tunnel oxide film becomes C '₁ Then [0024] (Equation 3) And by making it a vacuum gate,_R Is from 0.444
It is improved to 0.757. That is, the voltage required for writing
Vpp can be reduced. FIG. 4 shows two bit lines BL1 and BL2.
2 shows two adjacent NAND cell sections connected to each other,
The operation of the EEPROM will be described using this. First,
Data erasing is performed on the memory cells that constitute the NAND cell.
Erasure is performed. Therefore, in this embodiment, the NAND cell
Control gates CG1 to CG4 of memory cells to be erased in the memory cell
Is set to 0V, the source line, the substrate 10 and the p-type well 11
High voltage Vpp (for example, 18 V)
You. High potential Vpp is also applied to bit lines BL1 and BL2.
You. Thus, the control gate of the memory cell and p
An electric field is applied between the mold wells 11 and the floating gate 14
Electrons are emitted into the mold well 11 by a tunnel current.
All memory cells move the threshold value in the negative direction
Then, the state becomes “0”. Next, data writing is performed in the NAND cell.
The memory cell on the source line side, that is, the one farther from the bit line
Are performed in order from the first memory cell. Now, the memory cell M4
(Cell A surrounded by a broken line in FIG. 4)
To explain the case of writing, select transistor
The selection gate SG2 of the data gate S2 is set to 0V, and the control gate C2
High potential Vpp (for example, 16-18 V) is applied to G4,
The remaining control gates CG1 to CG3 and the selection gate SG1
Voltage V_M Applied. Also, the selected bit line BL1
0V is applied, and the power supply potential V is applied to the unselected bit line BL2.
cc is given. 0V for p-type well and Vcc for n-type substrate
I do. As a result, in the selected cell A,
Is controlled by transmitting 0 V of the bit line BL1 to the drain.
A high electric field is applied between the gate and the
Injected. As a result, in cell A, the threshold value increases in the positive direction.
Then, “1” is written. Another memory cell connected to bit line BL1
The weak write mode is set in M1 to M3, but the electric field is small.
There is no threshold change. Not selected (or write "0")
) Of the memory cells M5 to M7 of the bit line BL2 value
When the control gate is at Vcc and the channel potential (Vcc-Vth)
The potential difference is 1 to 3 V, and the threshold
There is no conversion. In this way, writing to cell M4 is
When finished, the next higher memory cell in the NAND cell
M3 is similarly programmed, and the memory cells M3 are sequentially written.
2, M1 is written. In the above write operation, the memory cell
A high potential Vpp is applied to the control gate.
Since the current is only the tunnel current, the current is at most 1 μA or less.
You. Also, at the time of batch erasing, the n-type substrate 1 and the p-type well 2 are kept high.
The potential is increased to Vpp.
Current and p-type well and n-type substrate of peripheral circuit kept at 0V
Leakage current, which is also 10 μA or less. Obedience
Thus, the high potentials Vpp and Vpp used for writing and erasing
(These may be the same value) are provided inside the chip
Can be sufficiently covered by the booster circuit. Also, it flows due to a high potential at the time of selective writing.
Since the current is small as described above, one control gate
Data to all memory cells connected to the line (word line) at the same time.
Data writing is possible. That is, writing in page mode
And high-speed writing is possible. The data read operation is performed in cell M4 (cell M4) shown in FIG.
A) will be described. Select transistor S1
Vcc is applied to select gate SG1 of non-selected memory cell SG1.
The control gates CG1 to CG3 of the M1 to M3 have a "1" state.
Vcc is also a potential that turns on the memory cell in the active state.
And the control gate CG4 of the read cell A is set to 0V.
Is done. Then, the bit line BL connected to the read cell A
1 is supplied with a read potential of 1 to 5 V, and other non-selected
The cut line BL2 is set to 0V. As a result, a current flows through bit line BL1.
Whether data "0" or "1" is determined depending on whether
It is. Next, an embodiment of the manufacturing process of the memory cell of the present invention will be described.
This will be described with reference to the cross-sectional views of FIGS. FIGS. 5 to 8
Shows a cross-sectional view taken along the line AA 'in FIG. A p-type well 1 formed on an n-type Si substrate
1, for example, a thermally oxidized SiO having a thickness of 10 nm._Two Shape the membrane 21
Then, the poly-Si film 14 is formed to a thickness of, for example, 400 nm.
It is deposited and doped with, for example, P (phosphorus). Then Si
O_Two A film 22 is deposited to a thickness of 200 nm (FIG. 5A).
Then, selectively SiO 2 by photolithography technique
_Two Film 22, poly-Si film 14, SiO_Two Membrane 21
And then remove the Si substrate by, for example, 500 nm.
It is removed by etching (FIG. 5B). Then for example NH
_Four SiO treatment by F treatment_Two Remove the film. At this time select
10 nm thermal oxide film 21 other than
SiO_Two The film 22 is removed, and as shown in FIG.
The lower side of the poly-Si film 14 in the memory cell region is hollow.
You. The poly-Si film 14 is made of the selected type shown in FIG.
Supported by the source part of the Lanista, like a bridge
It becomes a shape floating in the air. Also, at this time,
SiO 2 selectively by the lithography technique_Two Removing the membrane
Both are possible. For example, CG1 to CG4 shown in FIGS.
Only the part where the transistor connected to_Four F
The thermal oxide film 21 can be removed by the treatment. Then for example C
VD SiO_Two The film 12 is deposited, for example, to a thickness of
Fill the groove of the plate and the space of poly-Si14
(FIG. 6 (b)). At this time, between the poly-Si 14 and the substrate
Is not filled with a CVD film and a hollow (vacuum) state 13 is formed.
It is. The above-mentioned CVDSiO_Two The film 12 is composed of two layers of a normal pressure CVD film.
Film or CVD SiN film or SiO_Two And S
A stacked film of iN may be used. FIG. 7 shows a modified example of Si.
The N film 23 is buried, for example, in a thickness of 20 nm (FIG. 7A).
CVD SiO using TEOS after_Two The figure with embedded membrane
(FIG. 7B). Hollow shape using SiN film
Impurity diffusion and oxidation with respect to state 13
The state is kept well controlled. Next, the CVD film 12 is etched and
Stop etching around the center of poly-Si14
You. Next, for example, O to become a poly-poly insulating film.
An NO film 24 is formed (FIG. 8A). Then the second layer
Poly-Si16 is patterned to form a control layer.
And Next, ONO film 24, poly-Si14
Is patterned with the same mask as poly-Si16.
You. Next, the interlayer insulating film 18, bit line contacts and vias are formed.
In this case, the memory cell is completed (FIG. 8).
(B)). FIG. 9 shows a MOS transistor formed in a similar process.
FIG. 2 shows a cross-sectional view of a resistor. In this figure, the EEPR shown earlier
Poly-poly ONO in OM memory cell manufacturing process
The second poly-Si film 16 is directly formed without forming the film 24.
a is formed in contact with the first poly-Si film 14a.
The gate electrode is made of these laminated films. This MO
The S transistor is a cell of the NAND type EEPROM of FIG.
To form the gates and the like of the rect transistors S1 and S2.
It is also possible to apply to. FIG. 10 shows a case where the element isolation is LOCOS.
The example of the case is shown. Next, FIG. 11 shows the gate and the substrate part.
FIG. FIG. 10A is described above.
As in the case of the embodiment, the space between the gate electrode 14 and the substrate 11 is all true.
It indicates the state of being empty or gaseous,
As shown in FIG. 10B, the space between the gate electrode and the substrate is all
It need not be a vacuum. That is, the opposite gate side,
SiO on the substrate side surface_Two A film is formed, during which a vacuum is
You may. Also, only on either the gate side or the substrate side
SiO_Two A film may be formed. In addition, the above thermal oxidation
After the film 21 is removed by etching, the inside of the hollow
Then, a CVD film is deposited and formed, and the inside thereof is vacuum^-6Mind
Can be about pressure. Conversely, pressure is applied to the hollow part by applying pressure.
For example, it can be formed by filling the atmosphere with 10 atm. Sa
If the gas that fills the inside is a substance that becomes a gas at room temperature,
Anything is fine. For example, inactivation of He, Ne, Ar, and Kr
If the gas is used, the device operates stably. Also, Si
O_Two And H that is relatively stable on Si_Two , F_Two , Cl_Two , B
_r , O_Two , N_Two , CO_Two , NH_Three , NF_Three , Si F_Four Ah
Or compounds of N, O, Si, C, F, H, Cl
Or a mixture of these. The hollow shown in FIGS. 11A and 11B is used.
And Si, hollow and SiO_Two Traps and fields at the interface of
It is important to stabilize so as not to form plane levels.
You. For example, an H, F, -OH group, 基 O, N, C,
Al, B, P, A_s , G_e Terminates atomic bonds with
Can be. The method of stabilizing the interface is not limited to this, and other
Method may be used. FIG. 12 shows a vacuum insulation according to an embodiment of the present invention.
An example of the voltage-current characteristics of (vacuum gate) is a conventional SiO
_Two Shown in comparison with the membrane. SiO_Two Fowler-N for membrane
Leakage current occurs after ordheim stress,
It does not occur in the case of a vacuum gate. Key for vacuum gate
This is because carrier traps do not occur. This makes
Volatile memory cells significantly improve data retention
You. In addition, there is a risk of deterioration of Read disturb, etc.
Degradation due to sleek can be reduced. Also,
No write-on / erase, no lectron trap
Window narrowing occurs after
Absent. Also, no dielectric breakdown occurs. FIGS. 13 and 14 show still another embodiment.
You. FIG. 13B is a plan view thereof, and FIG.
It is CC 'sectional drawing of FIG.13 (b). In FIG. 13, the source side (or the drain side)
A part of the gate insulating film on the (side) is a vacuum gate.
As a result, no trap occurs in the vacuum portion 13b and the
By electron injection (hot electron).
Degradation is reduced. Also, true both sides of source / drain
An empty gate is also possible. FIG. 14 (a),
(B) Oxidation of the portion of the gate oxide film close to the element isolation
Only the film is removed by etching to make gas or vacuum 13c.
ing. As a result, parasitic transformers at the element isolation edge
Reduction of the effect and reliability of the register can be prevented.
You. FIG. 15 shows still another embodiment of the present invention.
You. In FIG. 15A, between the diffusion layer 9 and the charge storage layer 14a,
Some are formed thinner than other gate insulating films,
Both of them have vacuum or gas 13d in the thin part
You. FIG. 15B shows the state shown in FIG.
Pointed shape so that the electric field concentrates on the thin part 13e
Of the charge storage layer 14b. Also, in FIG.
Indicates that the thin portion 13f is not on the diffusion layer 9 but on the channel
It is in. In FIG. 16, vacuum or gas is filled.
The surface of the charge storage layer 14d on the side of the
Is shown. In this case, the write
The electric field is concentrated, and writing / erasing can be performed at a low voltage.
FIG. 16 shows a case where only the charge storage layer 14d has irregularities.
As shown, when there is unevenness only on the substrate side 11, the charge accumulation
It is also possible to have both the layer 14d and the substrate 11. When there are irregularities on both sides, there is a vacuum.
Or it may be in the part facing through 13 g of gas
Then, the charge storage layer 14d side and the substrate 11 side are located in different places.
May be placed. FIG. 17 shows a charge storage layer (p in this case).
poly-Si14) and control gate poly-Si16
13h between poly-poly is vacuum or gas
An example in the case of is shown. In this case, the charge storage layer 14
Charge injection and discharge are performed between the poly-poly vacuum portions 13.
It is also possible to do via h. Of course, the substrate 11
And between the charge storage layer 14. FIG. 18 shows a charge storage layer (Fl).
Oating Gate) Control gate (Control)
  Gate) and an erase gate (Erase Gat).
An example in the case of having e) is shown. In this case, at least
Electric field between the charge storage layer and the erase gate,
The concentrated portion of the insulating film is vacuum or gas.
As a result, deterioration of the insulating film due to rewriting is eliminated. Next, FIG. 17 shows another embodiment of the present invention.
Vacuum exists between charge storage layer 14 and control gate 16 as shown
An example of the operation in the case of the gas 13h will be described.
FIG. 19 shows an equivalent circuit of the memory cell of the above embodiment. Figure
20 shows the operating voltage of the memory cell alone. First
To erase data, set the control gate (CG) to 0V,
High voltage V on the substrate (well)_pp′ To control
Electrons from the gate (CG) to the charge storage layer (FG)
Inject. As a result, as shown in FIG.
The threshold value of the recell increases. Next, writing is performed using the control gate (C
G) to V_ppIs applied to set the D / S to 0V. In the charge storage layer
Are emitted to the control gate, and FIG.
As shown in FIG._thGoes down. Memory cells
If you do not want to write, V / S_M (= 10V) marked
Add. For reading, set the control gate to 0 or
About 3 V, read for example by applying 1 V to the drain
You. As shown in FIG. 22, write and erase memory cells
Depending on the selection of the threshold voltage,
Voltage is different. That is, in FIG.
V, and 3 V in FIG. FIG. 21 shows another operation method in FIG.
Is different from the method of Erase. in this case
Is -V at the control gate (CG)._pp'And apply D / S,
Set the well to 0 V and inject electrons into the charge storage layer (FG)
You. Next, referring to FIGS.
The operation of the memory cell when the memory cell is configured will be described.
First, data erase (Erase) constitutes a NAND cell
Erase is performed on the memory cell to be erased. So this
In the embodiment, the control of the memory cell to be erased in the NAND cell is performed.
The control gates CG11 to CG14 and CG21 to CG24
0V and the voltage is boosted to the source line, substrate and p-type well.
High potential V_pp(For example, 18 V). Bit line
High potential V is applied to BL1 and BL2_ppIs given. In addition, saw
Lines and bit lines BL1 and BL2 can be floating
Good. As a result, the control gate of the memory cell and p
An electric field is applied between the mold wells, causing the control gate to float
Is injected by a tunnel current. All memory cells
As a result, the threshold value moves in the positive direction and the state is “0”.
become. In Erase (selection 1) of FIG.
For example, V_ppTo prevent erasure.
Next, data writing is performed on the source line side in the NAND cell.
Memory cells, that is, the memory cells farthest from the bit line.
Are performed in order from the Now, the cell connected to CG14
To selectively write "1" data to
If the select gate SGS1 of the select transistor S2 is
0V, and the high voltage V is applied to the control gate CG14._pp(For example,
16 to 18 V), and the remaining control gate CG11
To CG13 and select gate SGD1_M Is applied
Is done. Also, 0 V is applied to the selected bit line BL1,
The power supply potential V is applied to the unselected bit line BL2._ccIs given.
0V for p-type well, V for n-type substrate_ccAnd As a result, in the selected cell,
0V of the bit line BL1 is transmitted to the drain to control
A high electric field is applied between the floating gate (CG) and the floating gate (F).
G) emits electrons to the control gate. As a result,
In the selected cell, the threshold value moves in the negative direction to “1”.
Writing is performed. Another memory cell connected to bit line BL1
In this case, the writing mode is weak, but the electric field is small.
No threshold change. Not selected (or write "0")
Of the memory cell on the side of the bit line BL2 in FIG.
Is V_ppOr V_M , The channel potential is (V_cc-V_th)so
The potential difference is small and the threshold value does not change.
No. Writing to the selected cell is completed in this way.
Then, M4, M3, M2, M of the first embodiment described above.
Next, the NAND cell is written in the same manner
From the memory cell one above to the next memory cell
Inscription is made. In the above write operation, the memory cell
High potential V_ppIs applied, but flows
Since the current is only a tunnel current, it is at most 1 μA or less.
is there. At the time of batch erasing, the n-type substrate 1 and the p-type well 2 are removed.
High potential V_ppThe current flowing at this time is
Current and p-type well and n-type base of peripheral circuit kept at 0V
This is the leak current between the plates, which is also 10 μA or less.
Therefore, the high potential V used for writing and erasing is_pp(This
These may be the same value)
The pressure circuit can provide sufficient power. Also, the flow due to the high potential during the selective writing
Current is very small as described above, so one control
At the same time for all memory cells connected to the
Data writing is possible. That is, page mode
Can be written, and high-speed writing is possible
You. The data read operation is performed, for example, on the CG12.
When reading connected memory cells, select
V is applied to the selection gate SG1 of the star S1._ccGiven, unselected
Control gates CG11, C of memory cells M1, M3, M4
The memory cells in the “1” state are turned on in G13 and CG14.
V_ccAnd the readout security
The control gate CG12 of the channel A is set to 0V. And read
1 to 5 V is applied to the bit line BL1 connected to the overflow cell A.
The subsequent potential is applied, and other unselected bit lines BL2 are set to 0.
V. Also, the bit line BL2 is set to a read voltage of 1 to 5V.
And read it simultaneously with reading BL1.
Wear. As a result, a current flows through bit line BL1.
Whether data "0" or "1" is determined depending on whether
It is. Next, channel hot using FIGS.
Inject electrons into the charge storage layer with electrons to write
To extract electrons from the charge storage layer to the control gate.
The operation of erasing will be described. FIG. 25 shows the voltage relationship of the operation. Eras
e is V at the control gate (CG)_pp″ To apply source drain
In (D / S) and well are set to 0V,
Emit electrons to the control gate. As a result,
The threshold value of the memory cell is lowered to the "0" state. This and
D / S, negative voltage V_E May be applied. Writing is performed by applying V to the control gate._pp, Drain
To V_pp'And apply channel-ot electrons to the substrate
Inject electrons into the charge storage layer. As a result,
Morisel's V_thRises to the "1" state. The reading is performed by a usual method. writing
/ V after erase_thAre W / E shared as shown in FIG.
To V_thBecomes positive. Next, FIG. 26 shows a NOR type array and the like.
FIG. 27 shows a voltage circuit of operation. In this operation, a high voltage is applied only to WL (CG).
Apply high voltage to the source to erase
Erase current is smaller than high-speed memory cell
ase becomes possible. Also, the configuration of peripheral circuits has been simplified.
It is. The present invention is limited to the above-described embodiment.
Not widely applied to semiconductor devices.
is there. For example, in this embodiment, the charge storage layer is made of poly-Si
I wrote about the case of SiN / SiO_Two Interface track
Or a metal electrode may be used. [0067] As described above, according to the present invention, the vacuum
Or use a gas gate to prevent deterioration
This allows the formation of a gate insulating device.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is an NAN of an EEPROM according to an embodiment of the present invention.
FIG. 2 is a plan view showing a D cell structure. FIG. 2 is a sectional view taken along line AA ′ of FIG. 1; FIG. 3 is a sectional view taken along the line BB ′ of FIG. 1; FIG. 4 is an equivalent circuit diagram of a NAND cell according to the embodiment of the present invention. FIG. 5 is a process sectional view according to the embodiment of the present invention. FIG. 6 is a process sectional view according to the embodiment of the present invention. FIG. 7 is a process sectional view according to the embodiment of the present invention. FIG. 8 is a process sectional view according to the embodiment of the present invention. FIG. 9 is a sectional view of a MOS transistor according to another embodiment of the present invention. FIG. 10 is a sectional view of a MOS transistor according to another embodiment of the present invention. FIG. 11 is an enlarged sectional view of a vacuum section according to the embodiment of the present invention. FIG. 12 is a characteristic diagram showing current-voltage characteristics of a vacuum gate according to an example of the present invention. FIG. 13 is a structural view showing still another embodiment of the present invention. FIG. 14 is a structural view showing still another embodiment of the present invention. FIG. 15 is a structural view showing still another embodiment of the present invention. FIG. 16 is a structural view showing still another embodiment of the present invention. FIG. 17 is a structural view showing still another embodiment of the present invention. FIG. 18 is a structural view showing still another embodiment of the present invention. 19 is an equivalent circuit diagram of the embodiment in FIG. FIG. 20 is a diagram showing operating voltages according to the embodiment of the present invention. FIG. 21 is a diagram showing still another operating voltage of the embodiment of the present invention. FIG. 22 shows a state after erasing the EEPROM according to the embodiment of the present invention.
FIG. 9 is a diagram showing a threshold distribution after writing. FIG. 23 is a NAND type EEPROM according to an embodiment of the present invention.
FIG. 3 is an equivalent circuit diagram of the OM. FIG. 24 is a NAND EEPROM according to an embodiment of the present invention.
FIG. FIG. 25 is a diagram showing operating voltages according to another embodiment of the present invention. FIG. 26 shows a NOR type EEP according to another embodiment of the present invention.
FIG. 3 is an equivalent circuit diagram of a ROM. FIG. 27 is a NOR type EEP according to another embodiment of the present invention.
FIG. 3 is a diagram showing operating voltages of a ROM. FIG. 28 is a plan view illustrating a conventional technique. FIG. 29 is a cross-sectional view illustrating a conventional technique. [Description of Signs] 10 ... n-type silicon substrate 11 ... p-type well 20 ... first gate oxide films 13, 13a, 13b, 13c, 13d, 13e, 13
f, 13g, 13h vacuum or gas region 14 floating gate 15 second gate oxide film 16 control gate 18 CVD insulating film 19 bit line 17 n-type diffusion layers M1 to M4, M5 to M8 memory cells S1, S2 ... select transistors SG1, SG2 ... select gates BL1, FG2 ... bit lines CG1 to CG4 ... control gates

Continuation of the front page (56) References JP-A-6-112443 (JP, A) JP-A-4-158858 (JP, A) JP-A-6-180992 (JP, A) JP-A-6-120490 (JP) JP-A-61-183969 (JP, A) JP-A-5-48088 (JP, A) JP-A-7-283404 (JP, A) VACUMUM-SEALED SIL ICON-RICH-OXIDE EE PROM CELL, IBM Tech. Disclosure Bulletin, November 1991, Vol. 6, PP. 238−241 (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/8247 H01L 27/115 H01L 29/788 H01L 29/792

Claims (1)

(57) [Claim 1] A charge storage layer and a control gate are formed on a semiconductor substrate.
A layer is formed, and an electric charge is applied between the semiconductor substrate and the charge storage layer.
Injection / release of load is possible, which enables electrically rewriting
Function memory cells are adjacent to each other.
Source and drain diffusion layers are connected in series.
Select the drain and source sides of this series connection
A select transistor having a select gate is provided and N
In a semiconductor device having an AND cell , at least a part between the semiconductor substrate and the charge storage layer is true.
It can be empty or gaseous.
A selective gate on the semiconductor substrate via a gate oxide film.
And the gate oxide film thickness is
Semiconductor device characterized by being thicker than the thickness of the air or gas
Place.