JP3460956B2 - Adiabatic charging logic - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention performs adiabatic charging logic by using a power supply voltage having a waveform that gently rises and falls gently, and a BDD logic circuit and a D latch that significantly reduce power consumption and circuit scale. The present invention relates to a logic circuit such as a logic circuit.

[0002]

2. Description of the Related Art Adiabatic charging logic has been attracting attention as a method capable of performing logic processing with low power consumption. A feature of this adiabatic charging logic is that the power supply voltage changes gently and periodically (slowly rises and gently falls). By the way, Low
When the power supply voltage rises from the (low voltage level) to the High (high voltage level) sufficiently slower than the RC time constant of the inverter, which is a logic circuit, the work of the power supply voltage at this time is 1 / 2.CV ² Therefore, it is known that the energy is equal to the energy stored in the load capacity. Also, H
The energy stored in the load capacitance is not discharged to the ground (GND) and returns to the power supply circuit (charge recycling) at the time of shifting from the high level to the low level, ideally consuming almost no energy, and the low level. It is known to perform logical processing of → High → Low (Reference 1: Davi
dJ. Frank and Paul Solomo
n, White paper on low power LSI technology, page 105, published by Nikkei BP, Nikkei Microdevices).

An example of a power supply circuit for realizing this is an AC circuit using an inductor and a capacitor.
If a resonance circuit is created by an inductor and a capacitor to generate an AC voltage and this is used as a power reusable power source, adiabatic charging and charge recycling are possible. In addition, a circuit that uses N-1 capacitors to form N staircase voltages (voltages that change and rise in N staircase shapes and similarly change and fall in N staircase shapes) It is known (Reference 1). This also allows adiabatic charging and charge recycling.

However, when an adiabatic charge or charge recycle is attempted to be performed by a normal CMOS circuit using the power reusable power supply, the output voltage of the power reusable power supply rises and falls with respect to one logic gate. Even if the timing is adjusted properly, the timing must be newly adjusted for the logic gate in the next stage. Here, as an example in which it is difficult to match the timing, a transmission gate type retractable logic circuit which is different from the CMOS circuit described above but is known to be easier to realize adiabatic charging and charge recycling will be shown. .

FIG. 67 (a) is a diagram showing the retractable logic circuit, in which 501 to 504 are logic gates and 50 is a logic gate.
5, 506 are capacitors. Here, the input signals A and B are input and their AND logic (= A · B) is processed, and the result and the input signal C are ORed (= A · B).
B + C). As a logic gate of this retractable logic circuit, it has been proposed to use a two-wire logic by a transmission gate 507 as shown in FIGS. 68 (b) and 68 (c). Here, the complementary input signals A and * A and the complementary input signals B and * B are input and output signals A and B and * (A and B) are output. Note that * indicates an inverted signal. In this retractable logic circuit, as shown in the time charts of FIGS. 67 (b) to (f), the waveforms of the power supply voltages V1 and V2 are controlled according to the number of gates. That is, the power supply voltage V1 rises gently (at a constant slope) after the rising of the input signals A and B, and the power supply voltage V1 rises before the falling of the input signals A and B.
It is necessary to control so as to slowly drop. The same applies to the relationship between the input signal C and the power supply voltage V2.

69 (a) and 69 (b) are diagrams showing an example of a conventional BDD logic circuit. B used in this logic circuit
DD graph (2-minute decision graph; Binary Dici
69 (a) is a graph having start points 1 and 2 and end points 3 and 4, and input variables (A, B, C in the figure) correspond to each node 5. To do. When obtaining the value of the logical output under the given input variable value, enter from the start point 1 or 2 of the graph, trace each node 5 downward, and finally reach either of the two end points 3 or 4. To do. At each node 5, one of the two branches 6 and 7 is traced according to the input variable value. That is, for example, if the input variable C is C = "0", the 0 branch 6 is followed, and if C = "1", the 1 branch 7 is taken.
Follow That is, given an input, one path from the start point to the end point is specified. If the end of the path is the end point "0", the logical output is "0", and if the end point is "1", the logical output is "1".

The BDD logic circuit is the BDD shown in FIG.
Using the graph, as shown in FIG. 69 (b), each branch of the BDD is associated with a logic element satisfying the above condition, for example, an n-channel MOSFET 8 and a wiring 9. Further, logical outputs are made to correspond to the starting points 1 and 2 of the BDD graph. Furthermore, the grounding (G
ND) and the constant power supply voltage VDD is connected to the end point 4 of “1” of the BDD graph (Reference 2: Kuroda, Sakurai, White Paper on Low Power LSI Technology, page 98, published by Nikkei BP, Nikkei Micro Device Edition).

Next, FIG. 70 is a diagram showing the structure of a conventional D-latch logic circuit. This logic circuit includes two transmission gates 601 and 6 which form a data acquisition circuit.
02, the cross-connected transmission gates 603 and 604 and the inverter 605 that form a memory circuit.
And 606. The clock signal CK and its inverted signal * CK are input to the transmission gates 601 to 604, and the constant power supply voltage VDD is applied to the power supplies of the inverters 605 and 606.

In this D-latch logic circuit, when the clock signal CK is High, the signals input to the nodes 607 and 608 are transmitted to the transmission gate 601, respectively.
It passes through 602 to reach the nodes 609 and 610, is inverted by the inverters 605 and 606, and passes through the nodes 611 and 6
Output to 12. Then, the clock signal CK is Lo
At w, the nodes 610 and 611 are connected, the nodes 609 and 612 are connected, and the inverters 605 and 60 are connected.
Inverters 606, 60 whose output signals are opposite to each other
5 is applied to the input side, and then the clock signal CK goes high.
The output signal is held until it becomes h (memory mode).

Further, the wiring 400 of the conventional CMOS logic circuit such as the combinational logic circuit and the D latch logic circuit shown in FIG.
Has a large wiring cross-sectional area in order to rapidly drive the gate of the next stage in a time of about ps. This wiring cross section is 0.25um of Nippon Telegraph and Telephone Corporation (NTT)
In the process, as shown in FIG. 67, 550 nm
(0.55 μm: signal wiring width W ₀ ) × 550 nm (0.
55 μm: signal wiring thickness H ₀ ) and CR in this case
The time constant is about 0.5 ns.

[0011]

In the retractable logic circuit described above, the power supply voltage waveform of hundreds or thousands is controlled for a circuit having hundreds or thousands of gates. There must be. Therefore, when adiabatic charging and charge recycling are performed using a power reusable power source, there is a problem that power is rather consumed. Also, D
In the latch-type logic circuit, in the transmission gate portion, M constituting the transmission gate is formed.
It is necessary to charge and discharge the gate of the OSFET and charge and discharge of the clock signal line. In this charge and discharge, C _TG VDD ²
There was a problem that only extra energy was consumed. Here, VDD is the power supply voltage, and C _TG is the sum of the gate capacitance of the transmission gate and the capacitance of the clock signal line. Further, also in the memory circuit, there is a problem that extra energy is consumed by C _ME VDD ² . Note that C _ME is the capacity of the memory circuit. Also, conventional CMO
Since the wiring cross-sectional area is large in the S logic circuit, there is a problem that it is difficult to reduce the circuit scale. Further, there is a problem that the self capacitance of the wiring and the mutual capacitance between the wirings cannot be reduced.

The present invention has been made in view of the above points, and it is an object of the present invention to efficiently realize adiabatic charging logic and also reduce the wiring cross-sectional area, thereby reducing the circuit. It is to provide a logic circuit that can realize power consumption reduction and circuit scale reduction.

[0013]

In order to solve such a problem, the present invention provides a logic circuit composed of a plurality of logic elements and a power supply to the logic circuit after an input signal is applied to the gate of each logic element. Supply it for logical processing,
The logic circuit is provided with a power supply unit that stops the supply of power before the logic process ends and a new input signal is applied to the gate of the logic element , and the logic circuit includes one start point, an end point, the start point and the end point.
Connect the nodes placed between the points and the nodes placed at the nodes
Based on a binary decision graph with branches and
The plurality of logic elements are each branch of the binary decision graph.
It is provided corresponding to and in front of the binary decision graph
A BDD logic circuit in which a portion corresponding to the starting point is grounded,
The output and gate are connected together and the gate is in front
Note: Connected to the output of the BDD logic circuit, and the power source is
Flip-flop circuit or PMOS connected to the source
It is composed of either one of the latch logic circuits . In addition, the logic circuit has one start point, an end point, and the start point.
And a node placed between the end points and between the nodes placed at the nodes
Constructed based on a binary decision graph with a branch connecting
And the plurality of logic elements are connected to each block of the binary decision graph.
It will be provided for lunch and the 2 minute decision
The part corresponding to the starting point of the cable is connected to the power supply unit.
BDD logic circuit, output and gate connected to each other
And the gate is connected to the output of the BDD logic circuit.
And an NMOS latch circuit whose source is grounded
It is composed. Also, the logic circuit is
And an end point, a node arranged between the start point and the end point, and a node
Binary decision with branches placed at points and connecting nodes
And the plurality of logic elements are configured based on the graph.
It is provided corresponding to each branch of the minute decision graph
And the part corresponding to the starting point of the binary decision graph is
BDD logic circuit connected to the power supply, output and gate
Are connected to each other and the gate is connected to the BDD logic circuit.
Connected to the output of the circuit and the power supply is connected to the power supply section.
And a PMOS latch circuit.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. [First Embodiment] The contents of the first embodiment are BD
The B shown in FIG. 65B, which has already been described, is a circuitization of the D graph.
Instead of the constant power supply voltage VDD of the DD logic circuit, a power reusable power supply was used, and the logic of the gate of hundreds or thousands of stages was performed by adiabatic charging once, and then stored in the BDD logic circuit. The charge is returned to the power supply circuit again. Here, FIG.
The BDD graph will be described again with reference to FIG. The BDD graph is a graph having start points 1 and 2 and end points 3 and 4, and each node 5 has an input variable (A,
B, C) correspond. When obtaining the value of the logical output under the given input variable value, enter from the start point 1 or 2 of the graph, trace each node 5 downward, and finally reach either of the two end points 3 or 4. To do. At each node 5, one of the two branches 6 and 7 is traced according to the input variable value. That is, for example, the input variable C is C
If 0 = “0”, follow 0 branch 6, and if C = “1”, follow 1 branch 7. That is, given an input,
One path from the start point to the end point is specified. If the end of the path is the end point "0", the logical output is "0", and if the end point is "1", the logical output is "1".

B of the first embodiment of the present invention shown in FIG.
The DD logic circuit associates each branch of such a BDD graph with a logic element that satisfies the above condition, for example, an n-channel MOSFET 8 and a wiring 9. Further, logical outputs are made to correspond to the starting points 1 and 2 of the BDD graph. Furthermore, the ground (GND) is connected to the end point 3 of "0" of the BDD graph, and the power reusable power source 10 is connected to the end point 4 of "1" of the BDD graph. As this power reuse type power source 10, as will be described later, for example, an AC power source circuit using an inductor and a capacitor, or a power source circuit generating N-step staircase voltage using N-1 capacitors is used. . The timing of power supply to the BDD logic circuit and the D-latch logic circuit, which will be described later, of the power reusable power supply 10 is controlled by the timing controller 450 as shown in FIG. The BDD logic circuit 30A shown in FIG. 66 is the BDD logic circuit shown in FIGS. 1 and 2, and the BDD logic circuit 30B shown in FIG. 66 is the BD shown in each of FIGS.
D logic circuit. In addition, recycling of the gate portion of the BDD logic circuit by the power reuse type power source 10 (# 2) will be described in each of fourth, fifth, sixth and seventh embodiments described later.

FIG. 2 shows an example of an AC power supply circuit 10A using an inductor 11 and a capacitor 12, and FIG. 3 shows an example of a power supply circuit 10B using four capacitors 13 to 15 to generate a four-step staircase voltage. Show. In FIG. 3, 16 to 23 are n-channel MOSFETs. These power supply circuits 1
At 0A and 10B, an AC waveform (repetitive waveform) that gradually increases and gradually decreases the output voltage can be obtained. As another example of the alternating voltage generated by the power reusable power source, the triangular wave shown in FIG.
The trapezoidal wave shown in (b) can also be used. Further, voltage waveforms generated from the sine waves shown in FIGS. 4C, 4D, and 4E can also be used. The triangular wave can be generated approximately by, for example, passing a voltage having a stepped waveform through an integrating circuit.

Next, the operation of the BDD logic circuit 30A shown in FIG. 1 will be described. First, at time t = 0, the input voltages * A, * B, * C, A, B, and C are input to the gates of the respective n-channel MOSFETs 8 of the BDD logic circuit. Next, the output voltage of the power reuse type power supply 10 is gradually increased. This allows the BDD logic circuit to be adiabatically charged. A logical operation is performed by this charging and an output signal is obtained. Then, after this adiabatic charging, the output voltage of the power reusable power source 10 is gradually decreased. At this time, the electric charge stored in the BDD logic circuit is returned to the power reusable power source 10. At time t = T after the output potential of the BDD logic circuit becomes Low, the next input signal is input to the gate. Hereinafter, by repeating this as the cycle T, it is possible to perform adiabatic charging and charge recycling. From the above, even when the number of gates is increased to several hundreds or thousands, the common power reusable power source 10 is used, so unlike the conventional retractable logic circuit, the power consumption does not increase and the power consumption is complicated. Low power consumption can be realized even in a logic circuit having a logic structure. Figure 4
(F) is an explanatory view showing a comparison of power consumption in the power supply section between the BDD logic circuit of the present invention and the conventional retractable logic circuit. As is clear from this explanatory diagram, in the conventional retractable logic circuit, the power consumption increases as the number of gates of the logic circuit increases, whereas in the BD of the present invention.
In the D logic circuit, the power consumption always maintains a constant low power.

FIG. 5 shows an example in which there are a plurality of BDD logic circuits. Here, the BDD logic circuits are denoted by reference numerals 301 to 30.
As shown by n, there are n pieces (n ≧ 4), and the i-th and the j-th are adjacent to each other (j = i + 1). At this time,
Each BDD logic circuit is an optimal power reusable power supply 101
10n to operate independently. For example, as the power supply for the kth BDD logic circuit, frequency f _k and phase φ
Use a power reusable power source of _k . A BDD logic circuit requiring a fast logic operation uses a power reusable power supply with a large frequency f _k, and a BDD logic circuit requiring a slow logic operation uses a power reusable power supply with a low frequency f _k . As a result, parallel processing can be efficiently performed for each BDD logic circuit.

Further, particularly for BDD logic circuits which may be power supplies of the same frequency and the same phase, a common power reusable power supply is used by connecting power supply lines, and the number of power supply circuits is reduced to reduce the power consumption. Can be realized. FIG. 6 is a diagram showing an example using a common power reusable power source. Here, the circuit configuration is such that the first to i-th power sources are the common power reusable power source 101 and the j-th to n-th power sources are the common power reusable power source 10n.

[Second Embodiment] FIG. 7 is a diagram showing a BDD logic circuit according to a second embodiment. In FIG.
In the BDD logic circuit shown in FIG.
This is an example in which, in the channel type MOSFET 8, the element whose inverted signals * A, * B, and * C are input to the gate as input signals is replaced with a logic element having a complementary relationship with the logic element. That is, here, the logic element is replaced with the p-channel MOSFET 24, and the input signals to the gates thereof are non-inverted signals A, B and C.
As a result, since only the non-inverted signals A, B, C can be used as the input signal, it is possible to omit one inverter for creating the inverted signal from the non-inverted signals. Therefore, the power consumption can be reduced as compared with the BDD logic circuit shown in FIG. The same applies to the BDD logic circuits shown in FIGS. 2, 3, 5, and 6.

The operation example of the mixed BDD logic circuit of the n-channel type MOSFET 8 and the p-channel type MOSFET 24 shown in FIG. 7 will be described in detail below by using simulation results. Here, as a power reuse type power source,
As shown in FIG. 8, a power source 10B of the type (the same as that shown in FIG. 3) that uses four capacitors 13 to 15 to generate a four-step staircase voltage is used. This power reuse type power source 10B has four constant power source voltages VDD and 3 / 4VD.
D, 2/4 VDD, 1/4 VDD, 3 capacitors 1
3 to 15 and 8 n-channel MOSFETs 16 to 23
It is composed of The three capacitors 13-15 are each 3
It is charged to a voltage of / 4 VDD, 2/4 VDD, 1/4 VDD. The input signal Pre is applied to the gates of the three n-channel MOSFETs 16 to 18, and the input signal T1 is applied to the gates of the four n-channel MOSFETs 19 to 22.
~ T4 is applied and one n-channel MOSFET 2
The input signal CL is applied to the gate of 3. 3 /
The power supplies of 4 VDD, 2/4 VDD, and 1/4 VDD are naturally in a stable state, even without them, because the capacitors 13, 14, and 15 are charged to 3/4 VDD, 2/4 VDD, and 1/4 VDD, respectively. However, here, the circuit mechanism as shown in FIG. 10 is used in consideration of the case of charging at high speed.

Detailed time charts of the operation of the power reusable power source 10B are shown in FIGS. 9 (a) to 9 (h). First, the input signal Pre of FIG. 9A is set to High for a certain period of time, the n-channel MOSFETs 16 to 18 are turned on, and the capacitors 13 to 15 are set to 3/4 VDD and 2/4 VD, respectively.
D, charged to 1/4 VDD. Next, FIG. 9 (e)
9 to the input signals T1 to T4 of FIG.
Hi for a predetermined time in the order of T3 → T4 → T3 → T2 → T1
gh to turn on the n-channel MOSFETs 19 to 22, and the voltage 3 /
4VDD, 2 / 4VDD, 1 / 4VDD are output as the output voltage Vout in a time division manner, and finally the input signal T1 is L
When it becomes ow, the input signal CL is set to High and the n-channel MOSFET 23 is turned on for a predetermined time to set the output voltage Vout to the ground potential. By such timing control, the output voltage Vout of the power reusable power source 10B
4 rises and falls as shown in FIG. 9 (c).
The waveform has two steps.

The above-mentioned input signals (pulses) CL, T1,
As shown in FIGS. 10A to 10F, T2, T3, and T4 are, for example, three T-type flip-flop circuits 41 to 4.
It can be generated by a circuit using 3,11 NAND circuits 44 to 54 and three inverters 55 to 57. In FIGS. 10A to 10F, 200 is an input terminal of a predetermined clock CK, 211 is an output terminal of the signal T1, 2
Reference numeral 12 is an output terminal of the signal T2, 213 is an output terminal of the signal T3, 214 is an output terminal of the signal T4, and 215 is an output terminal of the signal CL. Other codes are nodes, and nodes having the same code are commonly connected.

In the simulation, the capacitors 13 to 15 of the power reusable power source 10B each have a capacitance of 50.
00pF, 8 n-channel MOSFETs 16-23
The width W of each transistor was 36 μm. Also, FIG.
In each of the 3-input XOR BDD logic circuits, the transistor width W was set to 6 μm, and the load capacitance of the output on the XOR side was set to 0.5 pF. Here, B of this 3-input XOR
Regarding a circuit in which 1000 DD logic circuits are connected in parallel,
A simulation was performed. Also, the input clock signal C
The frequency of K was 4 MHz. The simulation results are shown in FIGS.

FIG. 11 is a waveform diagram of the signals Pre, CK, CL, T1 to T4 and Vout of the power reusable power source 10B. Certainly, it can be seen that the desired waveforms similar to those shown in FIGS. 9A to 9H are obtained. Since the total output load is 1000 times 0.5 pF (= 500 pF), the waveform has a slightly smoother shape than the stepwise shape. FIG. 12 shows input signals A, B, C, power supply voltage Vout,
It is a waveform diagram of the voltage of the output signals XOR and XNOR. As described above, the switching of the input voltage is performed by the power supply voltage Vou.
It is set to be performed when t is Low level. When all the input signals A, B and C are "1", XOR becomes "1" and XNOR becomes "0". Also, A = B
= “1”, C = “0”, XOR is “0”,
XNOR becomes "1", which shows that the logical processing is performed well. The pulse width (bit width) of signal C is 2μ
s, and the frequency of the output voltage is 500 kHz.

The result of power consumption is 4.76 × 10 ^-4 W at a frequency of 500 KHz. On the other hand, the power consumption per logic process of one normal CMOS XOR circuit is 1.06 × 10 ⁻⁶ W, and 1000 XO circuits
The power consumption per logical processing of R is 1.06 × 10 ⁻³ W. It can be seen that when the circuit of the present invention is used, the power consumption is reduced to about 1/2 as compared with a normal CMOS logic circuit. From the above discussion, it can be confirmed that the BDD logic circuit using the power reusable power supply of the present invention has low power consumption.

[Third Embodiment] FIG. 13 shows a BDD logic circuit according to a third embodiment using a power reusable power source. Here, the n-channel MOSFET 8 which is the logic element in the BDD logic circuit shown in FIG. 1 is replaced with a transmission gate 81 in which an n-channel MOSFET and a p-channel MOSFET are connected in parallel. The input signal of the p-channel MOSFET is n
It is an inverted signal of the input signal of the channel MOSFET.
As a result, as compared with the circuit shown in FIG. 1, the High level signal obtained as the output signal is VDD-Vth (V
Since th increases from the threshold voltage of the n-channel MOSFET to the power supply voltage VDD, there is an advantage that the voltage amplitude of the logic signal can be increased. That is, in the n-channel MOSFET, although the propagation characteristic of the Low level signal is good, the propagation of the High level signal has a voltage drop corresponding to the threshold voltage, which can be prevented. In addition, p-channel type MOSFET
Therefore, although the propagation characteristics of the High level signal are good, the propagation of the Low level signal is poor. Transmission gates can improve these.

[Fourth Embodiment] FIG. 14 shows a BDD logic circuit according to a fourth embodiment which uses a power reusable power supply. An AC power supply is used as the power reusable power supply and an input gate is used. In order to recycle the stored charge,
AC voltages Aac, Bac and Cac having the same frequency and phase as AC power supply voltage V1ac are applied to the input gate of the logic element. The circuit of FIG. 14 and the inverters 25 to 27 are combined and shown by a concrete circuit of FIG.
It is (d). Here, the power supply voltage of the BDD logic circuit is the AC voltage V1ac. The power supply voltage of the inverter 25 that receives the inverted signal * A and outputs the non-inverted signal A is also the AC voltage V1ac. The same applies to the other inverters 26 and 27. Here, as V1ac, a sine wave having an offset of 1V (center voltage of 1V) and an amplitude of 1V is used. Also, as * A, * B, * C, Lo
A signal having a w level of 0 V and a high level of 2 V is used.

FIG. 16 shows the result of simulation performed at an operating speed of 500 KHz. FIG. 16 shows the AC voltage V
1ac, waveforms of input signals * A, A, * B, B, * C, C and output signals XOR, XNOR are shown. In the input signal A, an AC voltage having a peak of 2V corresponds to a high level (“1”), and 0V corresponds to a low level (“0”). A, B, C is from 7μs to 2
Up to 5 μs, 111100001 and 110011 respectively
It can be seen that it is 001, 101010101. When A = B = C = “1”, XOR is “1”, A = B
It can be seen that XOR is “0” when C = “0” when “= 1”. The power consumption is 2.71 × 10 ⁻⁷ W in the BDD logic circuit. AC BDD shown here
The power consumption of the logic circuit is about 1/4 that of CMOS.
It can be seen that it is reduced to. Although a sine wave is used as the AC voltage here, it does not have to be a sine wave. For example, the voltage Vlac is generated from the triangular wave, the trapezoidal wave, and the sine wave shown in FIGS. It may be a voltage waveform. In addition, the power reuse type power source 1 shown in FIG.
0B, the stepwise voltage waveform (V in FIG. 9C)
Of course, out) may be used.

[Fifth Embodiment] FIG. 17A to FIG.
(F) and FIG. 18 are examples of the BDD logic circuit of the fifth embodiment that uses a power recycling type power supply. Here, when the AC power source V1ac is used as the power reuse type power source of the BDD logic circuit shown in FIG.
Instead of using the inverters 25 to 27 shown in (c), a circuit in which transmission gates 81 are connected in series is used. Then, as shown in FIGS. 17A and 17B, the logic signals Ain and * Ain are input to generate the AC voltage signals A and * A. Further, as shown in FIGS. 17 (c) and 17 (d), the logic signals Bin and * Bin are input to generate the AC voltage signals B and * B. Furthermore, FIG. 17 (e), (f)
Input the logic signals Cin and * Cin to generate the AC voltage signals C and * C as shown in FIG. And this AC voltage A,
* A, B, * B, C, * C are input to the BDD logic circuit of FIG. 18 to perform logic processing.

[Sixth Embodiment] FIG. 19A to FIG.
(D) is an example of the BDD logic circuit of the sixth embodiment using a power reusable power supply, in which the AC voltage V1ac described above is used as an input voltage, and an AC voltage V2ac 'is used as a power reusable power supply. To use. This AC voltage V2ac 'has twice the frequency of the AC voltage V1ac. Also,
An n-channel MOSFET 28 having a switch function is connected between the BDD logic circuit and the AC voltage V2ac '. By supplying a clock signal φ (the same frequency as the AC signal V1ac) to the gate of the n-channel MOSFET 28, the AC voltage V2ac obtained by taking out every other peak of the AC voltage V2ac ′ is used as the power supply voltage.

The simulation results are shown in FIG. Here, the AC voltage V2ac ′, the clock signal φ, the AC voltage V2ac after passing through the n-channel MOSFET 28, the AC voltage V1ac, the input signal C, the output signals XOR and XNO.
The waveform of R is shown. The input signals A and B have the same waveforms as those in FIG. 16, although they are not shown. It can be seen that the XOR and XNOR signals are correctly output as in the result shown in FIG. In the case of this circuit, power consumption is 3.6 ×
It is 10 ⁻⁸ W, which is low power of about 1/30 as compared with CMOS. The reason is that the input AC voltage V1a is
It is considered that this is because the waveform of the AC voltage V2ac of the power supply is contained in the waveform of c, so that the leak from the power supply to the ground is almost eliminated.

[Seventh Embodiment] FIG. 21A to FIG.
FIG. 22 (f) and FIG. 22 are examples of the BDD logic circuit of the seventh embodiment using a power reusable power source. The AC voltage V1ac described above is used as an input voltage, and the BDD logic circuit shown in FIG.
AC voltage V2a as a power reusable power source for a DD logic circuit
Use c '. This AC voltage V2ac 'is AC voltage V1.
It has twice the frequency of ac. In addition, a transmission gate 91 is connected between the BDD logic circuit and the AC voltage V2ac 'as shown in FIG. A clock signal φ (the same frequency as the AC signal V1ac) and a clock * φ are shown in the transmission gate 91.
The AC voltage V2ac 'is obtained by taking every other peak of the AC voltage V2ac' as the power supply voltage.
In the seventh embodiment and the fifth and sixth embodiments, as described above, the AC voltage does not have to be a sine wave, but a trapezoidal wave or a power reusable power source 10
It may be a stepwise waveform by B or the like. The timing relationship between the AC voltages V1ac and V2ac is that V1ac is V
It only needs to rise faster than 2ac and fall slowly. Some examples are shown in FIG.

[Eighth Embodiment] FIG. 24A shows an eighth embodiment.
It is a figure which shows the BDD logic circuit of embodiment. Here, the power reusable power supply 1 of the BDD logic circuit shown in FIG.
0 is replaced with a power non-reusable power source 10 '. The power non-reusable power supply 10 ′ is an AC power supply that does not reuse power (generates a voltage that rises and falls slowly and changes periodically). The AC power supply, the power reusable power supply 10 and the power non-reusable power supply 10 'are shown in FIG. 24 (b).
The relationship is as shown in. FIG. 25 is a diagram showing a circuit including a specific example of the power non-reusable power source 10 '. Here, the rectangular wave output from the inverter 35 is integrated by the resistor 36 and the capacitor 37 to create a repetitive voltage with a gentle rise and fall. An AC power source that does not reuse such power cannot recycle electric charges, but unlike rectangular waves, it can be charged adiabatically,
There is an advantage that power consumption is halved.

[Ninth Embodiment] FIG. 26 is a view showing an example of an IC card 60 according to the ninth embodiment. Here, an inductor (antenna) 6 is generated from a wireless electromagnetic wave such as the reader / writer 61 used for communication (or power transmission).
In the case where an AC voltage induced via 2 exists, the AC voltage itself is used as the power reusable power supply voltage of the IC card 60. Where 63
Is a BDD logic circuit, 64 is a rectification power supply circuit for creating a DC power supply for the CMOS logic circuit 65, and 66 is a capacitor. M is the transconductance.

[Tenth Embodiment] FIG. 27 shows a part of a BDD logic circuit according to a tenth embodiment. Here, as a logic element, a complementary TFT (Thin Film Transistor) is used instead of the complementary MOSFET.
tor) was used. Even with a circuit configuration using such a TFT, adiabatic charging and charge recycling are possible. The TFT operates at a lower speed than the MOSFET, and is considered to be an extremely suitable device for adiabatic charging.

A circuit using this TFT can be highly integrated three-dimensionally, whereby elements can be connected in parallel in the thickness direction, and the logic processing speed can be improved. In FIG. 27, 71 is a substrate, 72 is an insulating film, 73 is a metal or polysilicon wiring or gate, 74 is a gate insulating film, 75 is an n-type region to be a source or drain, and 76 is a p-type region to be a channel. , 77 is a p-type region serving as a source or drain, 78 is an n-type region serving as a channel, and 79 is a global through hole. In addition, here, the BDD logic circuits (FIGS. 7, 8, 13, 14, 14) used in the second to seventh embodiments are used.
Although complementary TFTs are formed in order to realize FIGS. 15 (d), 18, 19 (d) and 22), the complementary TFTs are not the complementary TFTs of FIGS. 1 to 3 and FIGS. B of the first embodiment
Of course, it can be applied to the DD logic circuit.

[Eleventh Embodiment] FIG. 28E is a diagram for explaining a BDD graph used in a BDD logic circuit according to an eleventh embodiment of the present invention. The BDD graph shown in FIG. 28 (e) corresponds to each BD shown in FIGS. 28 (a) to (d).
This is a shared D graph. 29 (a),
FIG. 28B is a BDD logic circuit using the shared BDD graph shown in FIG. By sharing each BDD graph in this manner, the number of transistors used in the BDD logic circuit can be reduced.

[Twelfth Embodiment] FIG. 30 shows a structure of a BDD logic circuit 30B according to a twelfth embodiment of the present invention. Here, input signals A, * A and B, * B
, C, * C, and carry output f = (A
B + BC + CA) and * f = * (AB + BC + CA) are shown in the BDD logic circuit. The BDD logic circuit 30B according to the twelfth embodiment is the same as the first embodiment described above.
-Unlike the BDD logic circuit 30A shown in the eleventh embodiment, the power reusable power source 10 is connected to the starting point 1 and given as a power supply voltage, and the output signal f from the end point 4 "1" and the end point 3 The output signal * f is extracted from "0". The waveform of the output voltage of the power reusable power source 10 is shown in FIGS. 4 (a) to 4 (e) and FIG. 9 described above.
As shown in (c), there are a stepwise waveform, an AC-like waveform (the polarity does not change, and the level changes smoothly) and the like.

FIGS. 31 (a) and 31 (b) show 2-bit input signals A0 and A1 and 2-bit input signals B0 and B1 in the 2-bit adder 140 shown in FIG. 31 (c).
The carry C0 of the bit is input and the sum output signal S1,
It is explanatory drawing when outputting * S1. Figure 31
31A is its BDD graph, FIG. 31B is its logic circuit, and FIG. 31C is a diagram showing the input / output relationship of the adder 140. 32A and 32B, in the 2-bit adder 140 shown in FIG. 32C, 2-bit input signals A0 and A1 and 2-bit input signals B0 and B1 and 1
It is explanatory drawing at the time of inputting the carry C0 of a pit, and outputting the carry output signals C2 and * C2. Here, FIG. 32A is its BDD graph, FIG. 32B is its logic circuit, and FIG. 32C is a diagram showing the input / output relationship of the adder 140.

Here, as the power reusable power source 10, an AC power supply circuit using an inductor and a capacitor, or a power supply circuit generating N steps of staircase voltage using N-1 capacitors can be used. it can. FIG. 33 shows an AC power supply circuit 10A using an inductor 11 and a capacitor 12.
For example: In addition, FIG. 34 shows three capacitors 13 to 1
Power supply circuit 10B for generating a four-step staircase voltage using 5
For example: In FIG. 34, 16 to 23 are n-channel MOSFETs. These power supply circuits 10A, 10
At B, the output voltage can be gently increased and gradually decreased.

Next, the operation of the BDD logic circuit shown in FIG. 34 will be described. First, at time t = 0, an input signal * is input to the gate of each n-channel MOSFET 8 of the BDD logic circuit.
Input A, * B, * C, A, B, C. Next, the output voltage of the power reusable power source 10B is gradually increased. This allows the BDD logic circuit to be adiabatically charged. By this charging, a logical operation is performed and an output signal is obtained. Then, after this adiabatic charging, the power reuse type power source 10
The output voltage of B is gradually decreased. At this time, the electric charge accumulated in the BDD logic circuit is returned to the power reusable power source 10B again. After the potential of the BDD logic circuit becomes Low, at time t = T, the next input signal is input to the gate. Hereinafter, by repeating this as the cycle T, it is possible to perform adiabatic charging and charge recycling.

From the above, even when the number of gates is increased to several hundreds or thousands, the common power reuse type power supply is used, so that the power consumption does not increase and the logic circuit has a complicated logic structure. Can achieve low power consumption. Note that FIG.
Since the specific operation of the power reusable power source 10B shown in FIG. 9 is the same as the operation already described in the time chart of FIG. 9, its operation description will be omitted. In addition, the power reuse type power source 10B
The circuit for generating each input signal given to is also equivalent to the circuit of FIG. Further, the power reusable power supply 10B generates a voltage waveform equivalent to Vout in FIG. 9C already described and supplies it to the BDD logic circuit.

FIG. 35 shows an example in which there are a plurality of BDD logic circuits. Here, the BDD logic circuits are 301 to 30n.
As shown in FIG. 3, there are n pieces (n ≧ 4), and the i-th and the j-th are adjacent to each other (j = i + 1). At this time, each of the BDD logic circuits has an optimal power reusable power supply 101-
10n to operate independently. For example, as the power supply for the kth BDD logic circuit, frequency f _k and phase φ _k
The power reusable power source of is used. A BDD logic circuit that requires a fast logic operation uses a power reusable power supply with a large f _k, and a BDD logic circuit that requires a slow logic operation uses a power reusable power supply with a small f _k . As a result, parallel processing can be efficiently performed for each BDD logic circuit. In addition, especially for BDD logic circuits that require power supplies of the same frequency and the same phase, a common power reusable power supply is used by connecting power supply lines, and the power consumption is reduced by reducing the number of power supply circuits. It becomes possible to do. FIG. 36 is a diagram showing an example in which a common power reusable power supply is used. The first to i-th power supplies are the common power reusable power supply 101, and the j-th to n-th power supplies are common. The circuit configuration is a power reusable power source 10n.

[Thirteenth Embodiment] FIG. 37 shows a BDD logic circuit according to the thirteenth embodiment. Here, in the BDD logic circuit shown in FIG. 30, in the n-channel MOSFET 8 as a logic element, an element to which the inverted signals * A, * B and * C of FIG. It is replaced with a logic element having a complementary relationship with the logic element. That is, here, the p-channel MO
It is replaced with the SFET 24, and the input signal to the gate thereof is the non-inverted signals A, B and C. As a result, since only the non-inverted signals A, B, C can be used as the input signal, it is possible to omit one inverter for creating the inverted signal from the non-inverted signals. Therefore, the circuit scale and the power consumption can be reduced as compared with the circuit shown in FIG. 31 (b) and 32
The same can be applied to the BDD logic circuits shown in (b), FIG. 33, FIG. 34, FIG. 35, and FIG.

[Fourteenth Embodiment] FIG. 38 shows a BDD logic circuit according to a fourteenth embodiment which uses a power reuse type power supply. Here, each n-channel MOSFET 8 which is a logic element in the BDD logic circuit shown in FIG.
n-channel MOSFET and p-channel MOSFET
And are replaced by a transmission gate 81 connected in parallel. The input signal of the p-channel MOSFET is an inverted signal of the input signal of the n-channel MOSFET. As a result, as compared with the circuit shown in FIG. 30, the High level signal obtained as the output signal is VDD−
Since the voltage rises from Vth (Vth is the threshold voltage of the n-channel MOSFET) to the power supply voltage VDD, there is an advantage that the voltage amplitude of the logic signal can be made large.
That is, in the n-channel MOSFET, although the propagation characteristic of the Low level signal is good, the propagation of the High level signal has a voltage drop corresponding to the threshold voltage, which can be prevented. Although the p-channel MOSFET has good propagation characteristics of a high level signal,
Propagation of ow level signals is not good. Transmission gates can improve these.

[Fifteenth Embodiment] FIG. 39 shows a BDD logic circuit according to a fifteenth embodiment which uses a power reusable power supply. An AC power supply is used as the power reusable power supply and further input. In order to recycle the charge stored in the gate, an AC voltage A having the same frequency and phase as the AC voltage V1ac of the power supply is applied to the input gate of each logic element.
Give ac, Bac, and Cac. FIGS. 40 (a) to 40 (d) show specific circuits by combining the circuit of FIG. 39 and the inverters 25 to 27. The power supply voltage of the BDD logic circuit is an AC voltage V1ac. Also, an inverter 2 that receives the inverted signal * A and outputs the non-inverted signal A
The power supply voltage of 5 is also an AC voltage V1ac. The same applies to the power supply voltages of the other inverters 26 and 27. Here, V
As 1ac, for example, an offset of 1V (center voltage 1
Use a sine wave with V) and an amplitude of 1V. Also,*
As A, * B and * C, Low level is 0V, High
A signal with a level of 2V is used. Although a sine wave is used as the AC voltage here, it is necessarily a sine wave.
It is not necessary to use, for example, the voltage V1ac as shown in FIG.
It may be a voltage waveform generated from the triangular wave, the trapezoidal wave, or the sine wave shown in FIG. Further, it goes without saying that a stepwise voltage waveform (Vout in FIG. 9C) obtained by the power reusable power source 10B shown in FIG. 8 may be used.

[Sixteenth Embodiment] FIG. 41A to FIG.
(F) and FIG. 42 are the 16th which uses a power reuse type power supply.
It is an example of the BDD logic circuit of the embodiment. here,
When the AC power source V1ac is used as the power reuse type power source of the BDD logic circuit shown in FIG. 39, FIG.
Instead of using the inverters 25 to 27 as shown in (c), a circuit in which a transmission gate 81 is connected in series is used. Then, as shown in FIGS. 41 (a) and 41 (b), the logic signals Ain and * Ain are input to generate the AC voltage signals A and * A. Further, as shown in FIGS. 41 (c) and 41 (d), the logic signals Bin, * Bin are input to create the AC voltage signals B, * B. Further, FIG. 41 (e),
As shown in (f), the logic signals Cin and * Cin are input to generate AC voltage signals C and * C. Then, the generated AC voltages A, * A, B, * B, C, * C are input to the BDD logic circuit of FIG. 42 to perform logic processing.

[Seventeenth Embodiment] FIG. 43A to FIG.
(D) is an example of the BDD logic circuit of the seventeenth embodiment using a power reuse type power supply, in which the AC voltage V1ac described above is used as an input voltage, and the AC voltage V2ac is used as the power supply of the BDD logic circuit. 'Is used. This AC voltage V2ac 'has twice the frequency of the AC voltage V1ac. Also, the BDD logic circuit and the AC voltage V2ac '
N-channel type MOSF having a switch function between
Connect ET28. This n-channel type MOSFET 2
The clock signal φ (AC signal V
By applying the same frequency as 1ac), the AC voltage V2ac obtained by taking out every other beak of the AC voltage V2ac 'is used as the power supply voltage.

[Eighteenth Embodiment] FIG. 44A to FIG.
(F) and FIG. 45 are the 18th which uses a power recycling type power supply.
43 is an example of the BDD logic circuit of the embodiment of the present invention, in which the AC voltage V1ac described above is used as an input voltage, and the AC voltage V2ac ′ is used as a power reusable power source of the BDD logic circuit shown in FIG. Similar to the BDD logic circuit of (d), the AC voltage V2ac obtained by taking out every other beak of the AC voltage V2ac 'is used as the power supply voltage. The eighteenth embodiment and the above-mentioned first embodiment
In the sixth and seventeenth embodiments, the AC voltage does not have to be a sine wave, and is based on the trapezoidal wave, the triangular wave, and the sine wave as shown in FIGS. It may be an alternating voltage or a staircase waveform generated by the power reusable power source 10B. In addition, AC voltages V1ac and V2ac
As for the timing relationship of, V1ac needs to rise faster than V2ac and fall later than V2ac.

[Nineteenth Embodiment] FIG. 46A shows a BDD logic circuit according to a nineteenth embodiment. Here, the power reusable power supply 10 of the BDD logic circuit shown in FIG. 30 is replaced with a power non-reusable power supply 10 '. The power non-reuse power source 10 'is an AC power source that does not reuse power. AC power supply and power reuse type power supply 1
0 and the power non-reusable power source 10 'have a relationship as shown in FIG. 46 (b). FIG. 47 is a diagram showing a specific example of the power non-reusable power source 10 '. Here, the rectangular wave output from the inverter 35 is integrated by the resistor 36 and the capacitor 37 to create an AC voltage having a gradual rise and fall. Even with such an AC power supply that does not reuse electric power, unlike a rectangular wave, since it can be adiabatically charged, there is an advantage that the power consumption is halved.
The elements of the logic circuits according to the twelfth to nineteenth embodiments described above are extremely suitable for adiabatic charging as described above.
FT can be used. Further, as shown in FIG. 27, it is also possible to integrate them three-dimensionally. Further, the logic circuits of the above twelfth to nineteenth embodiments can be similarly applied to the IC card 60 already described in the ninth embodiment of FIG.

[Twentieth Embodiment] FIG. 48A shows a D-latch logic circuit 90 which is a logic circuit according to the twentieth embodiment of the present invention. This circuit 90 includes two transmission gates 9 that form a data acquisition circuit.
1, 92, cross-connected transmission gates 93, 94 and inverters 95, 9 that form a memory circuit.
6 and 6.

Here, as the power supply voltage for the inverters 95 and 96, as shown in FIG. 48 (b), the voltage V3ac having a gentle rising and falling waveform is used. Further, as the clock signal, as shown in FIG. 48 (c), the voltage V4ac rises after the voltage V3ac falls, falls before the voltage V3ac rises, and has a waveform with a small duty such that the rise and the fall are gentle. And its inversion voltage * V4ac. In order to generate these voltages V3ac and V4ac, the oscillation type power supply circuit 10 shown in FIG.
A. Stepwise power supply circuit 10B shown in FIGS. 3 and 8 in which switching and charging / discharging are performed by using a plurality of capacitors to generate a staircase voltage, and one or a plurality of sin waves are used. 4 (a) to (e), a power reuse type power source such as a power source circuit generated, an alternating current obtained by the inductor for guiding the wireless electromagnetic wave already described in FIG. 26, etc. is used. Alternatively, a waveform similar to that shown in FIGS. 23A to 23H (a waveform in which V2ac is 180 degrees out of phase with V1ac) can be used. Furthermore, the voltage V3
To generate ac and V4ac, a power non-reusable power source 10 '
(FIGS. 24 (a) and 25) can also be used.

The D-latch logic circuit 90 first detects the voltage V
In the process in which 4ac changes from Low to High to Low, transmission gates 91 and 92 are temporarily turned on, and the signals input to nodes 97 and 98 at this time are transferred to nodes 99 and 100. In addition, the voltage V4a
When c changes from High to Low, the transmission gates 91 and 92 are cut off and the transmission gate 9
3, 94 are conductive, and the memory mode is entered. When this storage mode is entered, V3ac = 0 at first, so that the node 102 or 103 outputs the H signal at the H level.
Even when it should be in the high state, the voltage Vth
(P-channel type MOS forming the inverters 95, 96
FET threshold voltage). If it is in the Low state, it remains at 0V.

Next, the voltage V3ac changes from 0V to the power supply voltage V
When rising toward DD, the potential of the node 102 or 103 having the threshold value Vth slowly rises to the power supply voltage VDD. After this, the voltage V3ac is VDD
From 0V to 0V, the potential of the node 102 or 103 which has been at the power supply voltage VDD drops to the threshold voltage Vth. Through such a series of processes, the threshold voltage Vt
Charging is performed almost adiabatically in the process of increasing from h to the power supply voltage VDD. Further, when a power recycle power source is used for the voltage V3ac, the charges are adiabatically recycled to the power source side of V3ac in the process of decreasing from the power source voltage VDD to the threshold value Vth. Such adiabatic charging and charge recycling are similarly carried out in the portion of the transmission gate driven by the voltages V4ac and * V4ac.

From the above, in the portion driven by the clock signal (transmission gates 91 to 94),
The charge / discharge energy of the conventional circuit (FIG. 70) was C _TG VDD ² , as described above, but in the circuit of the present invention, it is ² τ / T times as C _TG VDD ² · 2 τ / T. Become. Where τ is C of the circuit when charging with voltage V4ac
R time constant, T is the rise time (fall time) of the voltage V4ac. Therefore, by setting τ << T, if charging / discharging is performed slowly enough, FIG. 49 (a)
As shown in, the energy can be made sufficiently small and the power consumption can be reduced. On the other hand, in the portion related to the memory circuit, in the circuit of the present invention, the information is not V
for storage in th, charging energy may be reduced from 1/2 · C _ME VDD ² of the conventional circuit in 1/2 · C _ME Vth ^2. Therefore, the energy required for charging / discharging this portion was C _ME VDD ² as described above in the conventional circuit, but becomes C _ME Vth ² + C _ME VDD ² · 2τ / T (FIG. 49 (b)). ). Note that T and τ are the same as those used when driving the clock signal portion. As described above, it is understood that the D latch logic circuit 90 of the present invention can reduce the power consumption of both the transmission gate portion and the storage circuit portion.

[Twenty-first Embodiment] FIG. 50 is a diagram showing a D-latch logic circuit according to a twenty-first embodiment of the present invention. The input to the D-latch logic circuit 90 shown in FIG. 48 (a). The outputs of the power reuse type BDD logic circuits 110 and 120 are respectively connected to the nodes 97 and 98 on the side. The BDD logic circuits 110 and 120 are n-channel type MOS
It is composed of a combination of the FET 8 and the p-channel MOSFET 24. The signals A, B and C applied to the gates of the MOSFETs are, as shown in FIGS. 51 (a) to (c), the inverter 1 using the voltage V3ac as the power supply voltage.
31-133, rectangular wave input signals * a, * b, *
c is waveform-converted (inverted and the rising and falling slopes are made to correspond to the rising and falling of the voltage V3ac).

Further, here, in the path for transmitting the outputs of the BDD logic circuits 110 and 120 of FIG. 50 to the nodes 97 and 98 of the D latch logic circuit 90, the p-channel type MO is provided.
The SFET 24 is connected, and an inversion voltage * V5ac of the voltage V5ac having a waveform as shown in FIG. 52B is applied to its gate. This voltage V5ac is also a voltage generated by the power reusable power supply or the power non-reusable power supply described above, and is a voltage having a waveform that rises later and falls faster than the voltage V3ac in FIG. It is also applied to one end point of the BDD logic circuit 110 and the other end point of the BDD logic circuit 120.

Next, the operation of the BDD logic circuit shown in FIG. 50 will be described. First, the input signals A, B, and C change to High and Low in synchronization with the voltage V3ac, and the BDD logic circuit 11
It is input to 0,120. Next, when the voltage V5ac rises, the BDD logic circuits 110, 120
The power supply voltage is applied to. Therefore, the logical processing (in the BDD circuit 110, the exclusive OR (XO) of the signals A, B, and C is performed.
R) processing, and in the BDD logic circuit 120, signals A, B, C
Inversion exclusive OR (XNOR) processing of
The result of this logic processing (Low or High signal) is transmitted to the nodes 97 and 98 in synchronization with the rising of the voltage V5ac, and then the voltage V5ac falls. At this point, the signals are stored in the nodes 97 and 98. Also,
After the voltage V5ac falls, the voltage V3ac also falls, and the input signals A of the BDD logic circuits 110 and 120,
B and C fall.

Next, when the voltage V4ac rises, the transmission gates 91 and 92 become conductive and the node 9
The signals of 7, 98 are transferred to the nodes 99, 100. After that, the same operation as the operation described for the circuit of FIG. 48A is performed in the D latch logic circuit 90, and the signal obtained by inverting the signal input to the nodes 97 and 98 is the voltage V.
It is output to the nodes 102 and 103 in synchronization with 3ac.
The signal Q output to the nodes 102 and 103 or the inverted signal * Q thereof is used as an input signal of a D latch logic circuit having a similar structure in the next stage, or the BDD logic circuits 110 and 1
It can be any one of the 20 input signals A, B, C. 52D to 52H show a D latch logic circuit 90.
FIG. 3 is an explanatory diagram when the output of is input to the BDD logic circuits 110 and 120. As mentioned above, this 21st
In the logic circuit of the embodiment, the BDD logic circuit 110,
At 120, adiabatic charging and charge recycling perform logical processing, and the processing result is input to the D-latch logic circuit 90, and similarly adiabatic charging and charge recycling perform logical processing, and another circuit at the next stage or the BDD logic circuit 110. , 12
Since it can be sent to the input side of 0, low power consumption can be realized.

[Twenty-second Embodiment] FIG. 53 (a) is a diagram showing a D-latch logic circuit according to a twenty-second embodiment of the present invention, which is the D-latch logic circuit shown in FIG. 48 (a). 90
Of the inverter 10 at the nodes 102 and 103 on the output side of the
An inverter circuit 130 consisting of a pair of 4,105 is connected. In the figure, 106 and 107 are output nodes. Here, the power supply voltage V6ac of the inverters 104 and 105 has a gradual rise and fall, as shown in FIG. 53 (c), and the voltage V6 of FIG. 53 (b).
The voltage has a waveform that rises later and rises faster than the rise of 3ac. This power supply V6ac is also a voltage generated by the above-described power reusable power supply or power non-reusable power supply.

When a load having a very large capacity is connected to the output nodes 102 and 103 of the D latch logic circuit 90 without the inverter circuit 130, the node 10 of the output node 102 and 103 is connected to the node 10.
Even when 2 or 103 should be High due to the signal transmitted through the transmission gates 93 and 94 (at this time, since V3ac = 0V, the threshold value becomes Vth as described above), it is momentary. Becomes 0V,
This may be transmitted to the load side, causing an error in data retention. In this respect, as in this embodiment, the inverter circuit 130 is connected to the nodes 102 and 103.
, And the node 106 of the inverter circuit 130,
By connecting a large-capacity load to 107, node 1
06 and 107 are transmission gates 93,
Since the signal transmitted at 94 is not directly received,
Data can be retained correctly.

[Twenty-third Embodiment] FIG. 54 is a diagram showing a D-latch logic circuit according to a twenty-third embodiment of the present invention. The input to the D-latch logic circuit 90 shown in FIG. 53 (a). BDD logic circuits 110 and 120 shown in FIG. 50 are connected to the nodes 97 and 98 on the side. In this embodiment, the voltages V3ac, V4ac, V5ac, V6ac
As such, the timing and waveform voltages shown in FIGS. 55 (a) to 55 (d) are used. In particular, the voltage V5ac has a waveform that rises later and falls faster than the voltage V6ac, and the voltage V6ac has a waveform that rises later and falls faster than the voltage V3ac. As a result, the processing contents (XOR, XNOR) of the signals A, B, C input to the respective MOSFETs of the BDD logic circuits 110, 120 become the voltage V.
5ac is output to the nodes 97 and 98 in synchronism with 5ac, and then is transferred to nodes 99 and 100 in synchronism with the voltage V4ac.
Subsequently, the voltage is transferred to the nodes 102 and 103 in synchronization with the voltage V3ac, and further, the node 10 is transferred in synchronization with the voltage V6ac.
6, 107 is transferred. The signals obtained at the nodes 106 and 107 can be input signals to the BDD logic circuits 110 and 120.

[Twenty-fourth Embodiment] FIG. 56 (a) is a diagram showing a D-latch logic circuit 90A according to a twenty-fourth embodiment of the present invention, which is the D-latch logic shown in FIG. 48 (a). The transmission gates 91 and 92 of the circuit 90 are replaced with the n-channel type MOSFET 8. in this case,
A non-inverted voltage V4ac is applied to the gate of the MOSFET 8. The D latch logic circuit 90 of FIG.
As shown in B, the transmission gates 91, 9
2 can be replaced with the p-channel MOSFET 24. At this time, the voltage * V4ac which is the inverted voltage V4ac is applied to the gate of the MOSFET 24. By using a single MOSFET for the transfer gate as described above, the number of transistors can be reduced.

[25th Embodiment] FIGS. 57A to 57C.
(C) is a figure which shows the logic circuit of 25th Embodiment. Here, the 2-bit adder 14 shown in FIG.
In 0, 2-bit data A1, A0 and B1, B0
The circuit portion for outputting the sum S1 and its inverted signal * S1 from the 1-bit carry C0 is composed of a PMOS latch logic circuit 140A and a BDD logic circuit 140B as shown in FIG. 57 (b). First, the PMOS
The latch logic circuit 140A does not use a transmission gate or an inverter and does not include two p-channel type MOSs.
The FET 24 is used, and the voltage V3ac is connected to the source. In addition, the BDD logic circuit 140B has a configuration shown in FIG.
The BDD graph shown in FIG.
It was realized by T8, and nodes 141 and 142
The output signal S1 of the BDD logic circuit 140B and its inverted signal * S1 appearing in
It is held at and transferred to the next stage (not shown). This BD
The starting point of the D logic circuit 140B is grounded.

In this embodiment, the input signals A1, A
After inputting 0, B1, B0, C0, the voltage V3a of the power supply
c rises, whereby logical processing is performed, and then the voltage V3ac falls, and then the input signal A
1, A0, B1, B0, C0 fall. The output nodes 141 and 142 of the PMOS latch logic circuit 140A are
When the voltage V3ac = 0, the High side is lowered to the threshold voltage Vth of the p-channel MOSFET,
Adiabatic charging is performed when the voltage V3ac rises to the power supply voltage VDD, and charge recycle is performed when the voltage V3ac drops to 0V, so that power consumption can be reduced.

That is, the PMOS latch logic circuit and BD
By combining the D logic circuit, the output signal S1 and its inverted signal * S1 can be correctly brought to the peak value of V3ac for High, and 0V for Low. In addition, by using a BDD logic circuit, it is possible to reduce the number of transistors and efficiently incorporate the circuit, and the design using a computer facilitates the design and configuration of a large-scale BDD logic circuit. There is an advantage that can be done. In addition to the above-described gate input and power supply voltage control method, it goes without saying that control by a four-phase clock method is possible (Reference 3: Y. Mo.
on and D.I. K. Jeong “An Effic
ient Change RecoveryLogic
Circuit ”IEEE Journal of S
solid-state circuits p. 51
4)

[26th Embodiment] FIGS. 58A to 58C.
(C) is a figure which shows the logic circuit of 26th Embodiment. Here, the 2-bit adder 14 shown in FIG.
0 (same as the circuit of FIG. 57 (c)), 2-bit data A1, A0 and B1, B0 and 1-bit carry C
A circuit portion for outputting carry C2 and its inverted signal from 0 is constituted by a PMOS latch logic circuit 140C and a BDD logic circuit 140D as shown in FIG. 58 (b).

The PMOS latch logic circuit 140C, like the PMOS latch logic circuit 140A, has two p-types.
A channel type MOSFET 24 is used, and the voltage V
3ac is connected. Also, the BDD logic circuit 140D
58A shows the BDD graph shown in FIG. 58A realized by a plurality of n-channel MOSFETs 8.
The output signal C2 of the BDD logic circuit 140D appearing at 43 and 144 and its inverted signal * C2 are latched by the PMOS latch logic circuit 140C and transferred to the next stage (not shown). The operation of this embodiment is almost the same as that of the circuit shown in FIG. 57 (b), and the output nodes 143, 144 are the same.
When the voltage V3ac = 0, the High side is lowered to the threshold value Vth of the p-channel MOSFET,
Adiabatic charging is performed when the voltage V3ac rises to VDD, and charge is recycled when the voltage V3ac subsequently drops to 0V, so that power consumption can be reduced.

[Twenty-seventh Embodiment] FIG. 59 is a diagram showing a logic circuit according to the twenty-seventh embodiment. This logic circuit corresponds to an NMOS type BDD logic circuit 140B (or 140).
D) and a flip-flop circuit including inverters 140G1 and 140G2. A flip-flop circuit 140G including inverters 140G1 and 140G2 and an NMOS type BDD logic circuit 140B
(Or 140D) connection example in FIG. 60 (a), (b)
Shown in.

[Twenty-eighth Embodiment] FIG. 61A shows a logic circuit according to the twenty-eighth embodiment.
This is a modification of the logic circuit shown in (b). Here, as shown in 140A ', the NMOS latch logic circuit is composed of an n-channel type MOSFET 8, its source is grounded, and the BDD logic circuit is shown in 140B'.
All are constructed by p-channel MOSFETs 24, and the voltage V3ac is connected to the starting point thereof. Here, the logical processing result of the BDD logic circuit 140B ′ is the nodes 141, 14 when the voltage V3ac rises.
2 and is latched by the NMOS latch logic circuit 140A '. That is, also here, adiabatic charging and charge recycling are performed.

[Twenty-ninth Embodiment] FIG. 61B is a diagram showing a logic circuit according to a twenty-ninth embodiment.
This is a modification of the circuit shown in (b). here,
As shown in 140C ′ of the NMOS latch logic circuit, n
A channel type MOSFET 8 is used, the source of which is grounded, and a BDD logic circuit is constituted by p channel type MOSFET 24 as shown in 140D ', and its starting point is connected to voltage V3ac. Again, BDD logic circuit 1
The logic processing result of 40D 'appears at the nodes 143 and 144 when the voltage V3ac rises, and adiabatic charging and charge recycling are performed.

[Thirtieth Embodiment] FIG. 62A shows a logic circuit according to the thirtieth embodiment.
This is a modification of the circuit shown in (b). here,
P-channel type MOS of the PMOS latch logic circuit 140A
While connecting the voltage V3ac to the source of the FET24,
The same voltage V3ac is connected to the start point of the BDD logic circuit 140B. Here, the side of the nodes 141 and 142 where the Low signal appears is in a floating state, but has a potential close to the ground potential instead of a high impedance. This could be confirmed by simulation. Adiabatic charging and charge recycling are performed on the side where the High signal appears.

[31st Embodiment] FIG. 62B is a diagram showing a logic circuit according to the 31st embodiment.
This is a modification of the circuit shown in (b). here,
P-channel type MOS of the PMOS latch logic circuit 140C
While connecting the voltage V3ac to the source of the FET24,
The same power source V3ac is also connected to the start point of the BDD logic circuit 140D. Also here, the side of the nodes 143 and 144 where the Low signal appears is in a floating state, but has a potential close to the ground potential rather than a high impedance. Adiabatic charging and charge recycling are performed on the side where the High signal appears.

[Thirty-second Embodiment] FIG. 63 (a),
(B) is a figure which shows the logic circuit of 32nd Embodiment, Each MOSFET of BDD logic circuit 140E, 140F respectively connected to PMOS latch logic circuit 140C and NMOS latch logic circuit 140A 'is N channel M.
It is a mixed type of OSFET and P-channel MOSFET. Thereby, the inverter connected to each input gate can be omitted. For the elements of the logic circuits according to the twentieth to thirty-second embodiments described above, TFTs extremely suitable for adiabatic charging as described with reference to FIG. 27 can be used.

[Thirty-Third Embodiment] In the conventional CMOS logic circuit, the current density is set to a certain upper limit value J ₀ or less in order to avoid disconnection due to electromigration. Generally, the life τ of the wiring due to electromigration can be expressed by τ = KST / {J ² Dexp (−ΔE / kT)} (1) (Reference 4: Design of CMOS VLSI, page 87, supervised by Takuo Sugano) , Tetsuya Iizuka, published by Baifukan). Here, K is a proportional constant, S is a wiring cross-sectional area, T is an absolute temperature, J is a current density, D is a diffusion coefficient of an aluminum atom, and k is a Boltzmann constant.

In this way, the wiring width becomes shorter and the current density J
It can be seen that the higher τ, the shorter the time τ until the wire breaks. Therefore, in the case of the CMOS logic circuit, it is understood that the wiring cross-sectional area has a lower limit value. In other words, the current density has an upper limit value. For example, the actual CMOS logic L
In SI, when the power supply voltage is 2 V, a current of about 8 mA flows in the signal line, and the current density is 2.7 × 10.
It is about ⁶ A / cm ² . The cross-sectional area of the signal line at this time is about (0.55 μm) ² = 0.30 μm ² (see FIG. 6).
4 (b) and FIG. 71).

On the other hand, BDD using the adiabatic charging logic
In a logic circuit, a D-latch logic circuit, and the like, charging and discharging are performed adiabatically, so that the current density flowing through the metal wiring and the transistor becomes extremely small. Therefore, the electromigration effect in the wiring is also reduced. Therefore, the wiring cross-sectional area is described above (0.5
5 μm) ² = 0.30 μm ² . Therefore, in the thirty-third embodiment, in the logic circuit that performs adiabatic charging logic, the wiring cross-sectional area is reduced while keeping the life due to electromigration to be about the same as that in the conventional CMOS logic circuit. We have further improved the reduction of power consumption.

Since the current I is I = SJ, the above equation (1) can be rewritten as τ = KTS ³ / {I ² Dexp (-ΔE / kT)} (2). Therefore, the life of the wiring due to electromigration is S ³ / I ²
It turns out that it is proportional to. In the case of a CMOS logic circuit, the average life of the wiring, the wiring cross-sectional area, the current flowing through the wiring is τ ₀ ,
If S ₀ and I ₀ , the relationship between them is as follows: τ ₀ = aS ₀ ³ / I ₀ ² (3) Here, a is a proportional constant.

On the other hand, in the case of a logic circuit performing adiabatic charging, the average life of the wiring, the wiring cross-sectional area, and the current flowing through the wiring are represented by τ,
Letting S and I be the relations, τ = aS ³ / I ² (4). Therefore, if τ / τ ₀ = (S / S ₀ ) ³ (I ₀ / I) ² (5) holds and the average lifespans of both are equal, that is, if τ ₀ = τ, then S = S ₀ (I / I ₀ ) ^2/3 The relational expression (6) holds.

In the case of adiabatic charging, since it operates slowly, the current value is, for example, 1/10 of that of the CMOS logic.
It is possible to reduce the current up to 00 times, so the current is 1
When the cross-sectional area is reduced to 1/100 times, the wiring life is exactly the same. From the above, for example, as shown in FIG. 64A, the wiring width is 0.15 μm and the thickness is 0.02 μm (cross-sectional area: 0.
It is possible to use ultra thin film wiring of 0030 μm ² ). Thickness 0.2 μm (Cross section area = 0.030 μm ² )
Even if it is 1 / of the normal wiring cross-sectional area (0.30 μm ² ).
It is 10 and is sufficiently effective. As described above, the wiring capacity can be reduced to 1/10 to 1/100 times,
As shown in FIG. 4 (c), the power consumption during charging is 1/10.
It is possible to reduce the amount to 1/100 times. Also,
As a development of this, not only the wiring but also the transistor does not require a large current driving capability, so that the transistor width (channel width) can be reduced from about 10 μm to 0.1 μm, which is 1/100 times the conventional value. It is possible. As a result, the capacity of the transistor can be reduced.

[Thirty-fourth Embodiment] Next, in the case where adiabatic charging logic is used for transmission of an electric signal, it will be described that the wiring cross-sectional area can be reduced from the viewpoint of being gentle and slow. First, when the cross-sectional area A of the wiring is reduced, it is assumed that it is reduced to 1 / k times. At this time, the resistance value R is k
Doubled. Further, the capacitance of the wiring is usually sufficiently smaller than the capacitance of the load of the gate in the next stage. Therefore, the capacitance C may be considered to be constant. From the above, approximately A × CR = constant (constant) (7) is obtained.

When the cross-sectional area of the wiring of the CMOS logic circuit is S ₀ and the cross-sectional area of the wiring of the adiabatic charging logic circuit is S, S ₀ (CR) _CMOS = S (CR) _adiabatic (8) is established. During adiabatic charging, transmission of electric signals may be slow. Therefore, 10 × (CR) _CMOS ≦ (CR)
Can be _adiabatic . Therefore, the following formula is established. S = S ₀ (CR) _CMOS / (CR) _adiabatic ≦ 1/10 × S ₀ (9) Further, the time T required to raise the power supply of the adiabatic charging circuit T
Needs to be larger than the CR time constant of the adiabatic charging circuit, so (CR) _adiabatic . ≦ T (10) is established. Therefore, the following equation is established. S ₀ (CR) _CMOS = S (CR) _adiabatic ≦ ST (11)

When (CR) _CMOS = τ is set here, τ / T × S ₀ ≤S (12) is obtained. From equations (9) and (12), τ / T × S ₀ ≦ S ≦ 1/10 × S ₀ (13) is obtained.

That is, the signal wiring width W ₀ 550 nm (0.55 μm) of the wiring 400 of the CMOS logic circuit shown in FIG.
m), and signal wiring thickness H ₀ 550 nm (0.55 μm
When reducing the wiring cross section of m), τ / T is set to 1/1
00, the cross-sectional area S is 0.003 μm ² ≦ S
Within the range of ≦ 0.03 μm ² . From the above, FIG.
It becomes possible to use the ultrathin film wiring as shown in FIG.

[35th Embodiment] FIG. 65 is an explanatory view showing the 35th embodiment of the present invention. The cross-sectional area of the signal wiring of the CMOS logic circuit shown in FIG. 71 can be reduced to 1/10 to 1/100 as described above, but the power supply line and the ground line of such a logic circuit can be similarly reduced. is there. That is, for example, a width of 30 μ shown in FIG.
When the cross-sectional area of the power supply line or the ground line 410 of the logic circuit having m and a thickness of 3 μm is S ₀ , the adiabatic charging logic shows a cross-sectional area of 1/10 (1/10) as shown in FIG.
× S ₀ ), and as shown in FIG. 65 (c), the cross-sectional area can be 1/100 (1/100 × S ₀ ). In other words, the power supply line and the ground line of the logic circuit can be reduced in cross-sectional area to 1/10 to 1/100 by the adiabatic charging logic like the signal line.

In each of the thirty-third to thirty-fifth embodiments, it is needless to say that the cross-sectional areas of the signal line, the power line and the ground line can be reduced to 1/1000 times by performing the adiabatic charging more slowly. is there. In this way, in the adiabatic charging logic, the wiring cross-sectional area can be reduced, and a small number of electrons can be transported to efficiently implement the logic processing. As a result, the energy of one logic processing can be compared with that of the conventional CMOS logic circuit. It is possible to greatly reduce it.

[0088]

As described above, according to the present invention, adiabatic charging and charge recycling can be extremely easily realized in a BDD logic circuit or a D latch logic circuit having a number of gates of hundreds or thousands. , The conventional CMOS logic circuit,
As compared with the D-latch logic circuit, lower power consumption and smaller circuit scale can be achieved. Further, since the present invention performs charging and discharging adiabatically, the current density flowing through the metal wiring and the transistor is extremely small, so that the electromigration effect in the wiring is small and the cross-sectional area of the wiring is smaller than that of the CMOS logic circuit. Compared with the cross-sectional area of the wiring, it has a feature that it can be greatly reduced and the wiring capacitance can be greatly reduced. As described above, according to the present invention, logical processing can be efficiently realized by transporting a small number of electrons, and thus the energy of one logical processing can be significantly reduced as compared with the conventional CMOS logic circuit. To do.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a BDD logic circuit according to a first embodiment.

FIG. 2 is a diagram showing an example in which an AC power supply circuit is used as a power reuse type power supply of the BDD logic circuit of FIG.

3 is a diagram showing an example in which a power supply circuit that generates a staircase voltage is used as a power reusable power supply of the BDD logic circuit of FIG.

FIG. 4 is a diagram showing another voltage waveform or the like as a power reusable power source.

FIG. 5 is a diagram showing an example in which individual power-reuse-type power supplies are used in power supply circuits of a plurality of BDD logic circuits.

FIG. 6 is a diagram showing an example in which a plurality of BDD logic circuits are divided into two groups and a common power reuse type power source is used for each groove.

FIG. 7 is a circuit diagram of a BDD logic circuit according to a second embodiment.

8 is a diagram showing an example in which a power supply circuit that generates a staircase voltage is used as a power reuse power supply of the BDD logic circuit of FIG.

9 is a waveform diagram of the operation of the power supply circuit of FIG.

10 is a circuit diagram for generating a timing signal for each of the power supply circuits of FIG.

11 is a waveform chart showing a simulation result of the power supply circuit of FIG.

12 is a waveform diagram showing a simulation result of the BDD logic circuit of FIG.

FIG. 13 is a circuit diagram of a BDD logic circuit according to a third embodiment.

FIG. 14 is a circuit diagram of a BDD logic circuit according to a fourth embodiment.

FIG. 15 is a more specific circuit diagram of FIG.

16 is a waveform diagram showing a simulation result of the BDD logic circuit of FIG.

FIG. 17 is a circuit diagram of a BDD logic circuit according to a fifth embodiment.

FIG. 18 is a circuit diagram of a BDD logic circuit according to a fifth embodiment.

FIG. 19 is a circuit diagram of a BDD logic circuit according to a sixth embodiment.

20 is a waveform diagram showing a simulation result of the BDD logic circuit of FIG.

FIG. 21 is a circuit diagram of a BDD logic circuit according to a seventh embodiment.

FIG. 22 is a circuit diagram of a BDD logic circuit according to a seventh embodiment.

FIG. 23 is an explanatory diagram of another waveform of the AC power supply.

FIG. 24 is a circuit diagram of a BDD logic circuit according to an eighth embodiment.

FIG. 25: B to which a specific non-reusable power source was connected
It is a circuit diagram of a DD logic circuit.

FIG. 26 is an explanatory diagram of an IC card according to a ninth embodiment.

FIG. 27 is a partial cross-sectional view of the BDD logic circuit of the tenth embodiment.

FIG. 28 is an explanatory diagram showing an example of sharing a BDD graph applied to the BDD logic circuit of the eleventh embodiment.

FIG. 29 is a circuit diagram of a BDD logic circuit according to the eleventh embodiment.

FIG. 30 is a circuit diagram of a BDD logic circuit according to a twelfth embodiment.

31 is a diagram showing a BDD graph and a BDD logic circuit of an example in which the BDD logic circuit of FIG. 30 is applied to a sum operation of a 2-bit adder.

32 is a BDD graph and BD of an example in which the BDD logic circuit of FIG. 30 is applied to carry operation of a 2-pit adder.
It is a figure which shows a D logic circuit.

33 is a diagram showing an example in which a power supply circuit using an inductor is used as a power reuse type power supply of the BDD logic circuit of FIG. 30.

34 is a diagram showing an example in which a power supply circuit for generating a staircase voltage is used as a power reuse type power supply of the BDD logic circuit of FIG. 30.

FIG. 35 is a diagram showing an example in which individual power-reuse-type power supplies are used in the power supply circuits of a plurality of BDD logic circuits.

FIG. 36 is a diagram showing an example in which a plurality of BDD logic circuits are divided into two groups and a common power reusable power source is used for each group.

FIG. 37 is a circuit diagram of a BDD logic circuit of the thirteenth embodiment.

FIG. 38 is a circuit diagram of a BDD logic circuit of the fourteenth embodiment.

FIG. 39 is a circuit diagram of a BDD logic circuit according to the fifteenth embodiment.

FIG. 40 is a diagram showing a circuit embodying the circuit of FIG. 39.

FIG. 41 is a circuit diagram of a BDD logic circuit according to the 16th embodiment.

FIG. 42 is a circuit diagram of a BDD logic circuit according to the 16th embodiment.

FIG. 43 is a circuit diagram of a BDD logic circuit of the seventeenth embodiment.

FIG. 44 is a circuit diagram of a BDD logic circuit of the eighteenth embodiment.

FIG. 45 is a circuit diagram of a BDD logic circuit of the eighteenth embodiment.

FIG. 46 is an explanatory diagram of a BDD logic circuit according to the nineteenth embodiment.

47 is a diagram showing a power non-reusable power supply circuit of the BDD logic circuit of FIG. 46. FIG.

FIG. 48 is an explanatory diagram of a D latch logic circuit and a power supply voltage waveform according to the twentieth embodiment.

FIG. 49 is a comparative explanatory diagram of charge and discharge energies of a clock portion and a memory circuit portion.

FIG. 50 is a circuit diagram of a D-latch logic circuit according to a twenty-first embodiment.

51 is a circuit diagram for generating signals A, B, and C in the circuit of FIG. 50.

52 is a voltage waveform diagram of the circuit of FIG. 50. FIG.

FIG. 53 is an explanatory diagram of a D latch logic circuit and a power supply voltage waveform according to the 22nd embodiment.

FIG. 54 is a circuit diagram of a D-latch logic circuit according to a 23rd embodiment.

FIG. 55 is a voltage waveform diagram of the circuit of FIG. 54.

FIG. 56 is a circuit diagram of a D-latch logic circuit according to a 24th embodiment.

FIG. 57 is a circuit diagram of a PMOS latch logic circuit according to a 25th embodiment.

FIG. 58 is a circuit diagram of a PMOS latch logic circuit according to the 26th embodiment.

FIG. 59 is a block diagram of a logic circuit showing a twenty-seventh embodiment.

FIG. 60 is a circuit diagram of a logic circuit showing a twenty-seventh embodiment.

FIG. 61 is a circuit diagram of an NMOS latch logic circuit according to the 28th and 29th embodiments.

FIG. 62 is a circuit diagram of a PMOS latch logic circuit according to the 30th and 31st embodiments.

FIG. 63 is a circuit diagram of a thirty-second embodiment.

FIG. 64 is an explanatory diagram of the 33rd embodiment.

FIG. 65 is an explanatory diagram of the thirty-fifth embodiment.

FIG. 66 is a block diagram showing a state of power supply control for a BDD logic circuit and a D latch logic circuit.

FIG. 67 is an explanatory diagram of a conventional retractile logic circuit and operation waveforms.

FIG. 68 is an explanatory diagram when embodying a retractable logic circuit.

FIG. 69 is a circuit diagram of a conventional BDD logic circuit.

FIG. 70 is a circuit diagram of a conventional D latch logic circuit.

FIG. 71 is a diagram showing a state of a wiring cross-sectional area of a conventional CMOS logic circuit.

[Explanation of symbols]

1, 2 ... Start point, 3, 4 ... End point, 5 ... Node, 6, 7 ... Branch, 8, 28 ... N-channel type MOSFET, 9 ... Wiring, 10, 10A, 10B, 101-10n ... Power reuse type power source 10 '... Power non-reusable power source, 11, 62 ...
Inductors, 12 to 15, 37, 66 ... Capacitors, 1
6 to 23 ... n-channel MOSFET, 24 ... p-channel MOSFET, 25-27, 35, 55-57,
95, 96, 104, 105, 131-133 ... Inverter, 30A, 30B, 63, 110, 120, 301
~ 30n, 140B, 140B '140D, 140D'
... BDD logic circuit, 36 ... Resistor, 41-43 ... T flip-flop circuit, 44-54 ... NAND circuit, 60 ... I
C card, 61 ... Reader / writer, 64 ... Power rectification circuit,
65 ... CMOS logic circuit, 71 ... Substrate, 72
... Insulating film, 73 ... Metal or polysilicon (wiring or gate), 74 ... Gate insulating film, 75 ... N-type region (source or drain), 76 ... P region (channel), 77 ... P
Type region (source or drain), 78 ... N type region (channel), 79 ... Global through hole, 81, 82 ... Transmission gate, 90, 90A, 90B ... D latch logic circuit, 91-94 ... Transmission gate, 130 ... Inverter Circuit, 140 ... 2-bit adder, 140A, 140C ... PMOS latch logic circuit, 1
40A ', 140C' ... NMOS latch logic circuit, 40
0,410 ... CMOS logic circuit wiring, 450 ... Timing control section.

─────────────────────────────────────────────────── ─── Continuation of front page (31) Priority claim number Japanese Patent Application No. 10-89582 (32) Priority date March 19, 1998 (March 19, 1998) (33) Priority claim country Japan (JP) (31) Priority claim number Japanese Patent Application No. 10-96944 (32) Priority date March 26, 1998 (Mar. 26, 1998) (33) Country of priority claim Japan (JP) (31) Priority claim number Japanese Patent Application No. 10-169459 (32) Priority Date June 17, 1998 (June 17, 1998) (33) Priority claiming country Japan (JP) (72) Inventor Ken Takeya Sanjuku Nishi Shinjuku-ku, Tokyo Nihon Telegraph and Telephone Corporation (56) References JP-A-7-15319 (JP, A) JP-A-8-335873 (JP, A) JP-A-7-221631 (JP, A) JP-A-5-268000 (JP, A) JP-A-11-88150 (JP, A) JP-A-10-308662 (JP, A) JP-A-7-168874 (JP A) Patent Akira 61-221685 (JP, A) United States Patent 5493240 (US, A) (58 ) investigated the field (Int.Cl. ^7, DB name) H03K 19/00 G06F 7/50

Claims (3)

(57) [Claims] 1. A logic circuit comprising a plurality of logic elements, and after supplying an input signal to the gate of each logic element, power is supplied to the logic circuit to perform logic processing,
The logic processing and a power supply unit for stopping the supply of the power before a new input signal is supplied to the gate of the finished said logic elements, said logic circuit, one of the starting point, and end point, and above start point The end
Connect the nodes placed between the points and the nodes placed at the nodes
Based on a binary decision graph with branches and
The plurality of logic elements are each branch of the binary decision graph.
It is provided corresponding to and in front of the binary decision graph
A BDD logic circuit in which a portion corresponding to the starting point is grounded,
The output and gate are connected together and the gate is in front
Note: Connected to the output of the BDD logic circuit, and the power source is
Flip-flop circuit or PMOS connected to the source
An adiabatic charging logic circuit characterized by comprising either one of a latch logic circuit. 2. A logic circuit comprising a plurality of logic elements and the above-mentioned theory after an input signal is applied to the gate of each logic element.
While supplying power to the logic circuit to perform logical processing,
After the logic processing is completed, a new input is made to the gate of the logic element.
Power supply to stop the supply of the power supply before the power signal is given
And a section, the logic circuit is a 2-minute with a one start point and end point, and the start point and the positioned between end <br/> point node, the branch connecting the nodes are arranged in the node Configured based on a decision graph,
The plurality of logic elements are provided corresponding to each branch of the binary decision graph, and are provided in front of the binary decision graph.
BDD that portion corresponding to the serial start is connected to the power supply unit
When the logic circuit and the output and gate are connected to each other
Has a gate connected to the output of the BDD logic circuit, and
An adiabatic charging logic circuit comprising an NMOS latch circuit whose source is grounded . 3. A logic circuit comprising a plurality of logic elements, and the above-mentioned theory after an input signal is applied to the gate of each logic element.
While supplying power to the logic circuit to perform logical processing,
After the logic processing is completed, a new input is made to the gate of the logic element.
Power supply to stop the supply of the power supply before the power signal is given
And a section, before Symbol logical circuit has one starting point, and end point, above start point and said end
Connect the nodes placed between the points and the nodes placed at the nodes
Based on a binary decision graph with branches and
The plurality of logic elements are each branch of the binary decision graph.
It is provided corresponding to and in front of the binary decision graph
BDD that portion corresponding to the serial start is connected to the power supply unit
When the logic circuit and the output and gate are connected to each other
Has a gate connected to the output of the BDD logic circuit, and
A PMOS latch circuit whose power source is connected to the power source
Adiabatic charging logic circuit, characterized in that Ranaru.