JP3683888B2 - Adiabatic charging logic circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a logic circuit that performs adiabatic charging logic by using a power supply voltage having a gradually rising and falling waveform, thereby significantly reducing power consumption and circuit scale.
[0002]
[Prior art]
The adiabatic charging logic has been attracting attention as a method that can perform logic processing with low power consumption. A characteristic of this adiabatic charging logic is that the power supply voltage changes gently and periodically (rises gently and falls slowly).
However, when the power supply voltage rises sufficiently slowly from the Low (low voltage level) to the High (high voltage level) than the RC time constant of the inverter that is the logic circuit, the work of the power supply voltage at this time is 1/2.・ CV² It is known that the energy stored in the load capacity matches the energy. Also, when transitioning from High to Low, the energy stored in the load capacity is not released to the ground (GND), but returns to the power supply circuit (charge recycling), and ideally consumes little energy. It is known to perform logic processing of Low → High → Low (Reference 1: David J. Frank and Paul Solomon, Low-power LSI technology white paper, page 105, published by Nikkei BP, edited by Nikkei Microdevices).
[0003]
As an example of a power supply circuit for realizing this, there is an AC circuit using an inductor and a capacitor. Adiabatic charging and charge recycling are possible if an AC voltage is generated by using an inductor and a capacitor to generate an AC voltage and this is used as a power reusable power source.
In addition, a circuit that uses N−1 capacitors to form N stepped voltages (voltages that rise and change in N steps and fall in the same way in N steps). Known (Reference 1). This also enables adiabatic charging and charge recycling.
[0004]
However, when adiabatic charging and charge recycling are performed using a normal CMOS circuit using a power reusable power supply, the rise and fall timings of the output voltage of the power reusable power supply are well controlled for one logic gate. Even if they are combined, it is necessary to newly adjust the timing for the logic gate of the next stage.
Here, as an example where it is difficult to synchronize the timing, a transmission gate type retractile logic circuit which is different from the above-described CMOS circuit but is known to be more likely to realize adiabatic charging and charge recycling will be described. .
[0005]
FIG. 67A is a diagram showing the retractile logic circuit, in which 501 to 504 are logic gates, and 505 and 506 are capacitors. Here, the input signals A and B are inputted, the AND logic (= A · B) is processed, and the OR logic (= A · B + C) of this result and the input signal C is obtained. As a logic gate of this retractile logic circuit, it has been proposed to use a two-wire logic by a transmission gate 507 as shown in FIGS. 68 (b) and 68 (c). Here, complementary input signals A and * A and complementary input signals B and * B are input, and output signals A and B and * (A and B) are output. Note that * indicates an inverted signal.
In this retractile logic circuit, as shown in the time charts of FIGS. 67B to 67F, the waveforms of the power supply voltages V1 and V2 are controlled according to the number of gates. That is, the power supply voltage V1 is controlled to rise gently (at a constant slope) after the input signals A and B rise, and the power supply voltage V1 is controlled to fall gently before the input signals A and B fall. There is a need. The same applies to the relationship between the input signal C and the power supply voltage V2.
[0006]
FIGS. 69A and 69B are diagrams showing an example of a conventional BDD logic circuit. A BDD graph (binary decision diagram) used in this logic circuit is a graph having start points 1, 2 and end points 3, 4 as shown in FIG. Input variables (A, B, C in the figure) correspond. When calculating the value of the logic output under the given input variable value, enter from the start point 1 or 2 of the graph, follow each node 5 downward, and finally reach one of the two end points 3 or 4 To do. Each node 5 follows one of the two branches 6 and 7 corresponding to the input variable value. That is, for example, if the input variable C is C = "0", the 0 branch 6 is followed, and if C = "1", the 1 branch 7 is followed. That is, given an input, one path from the start point to the end point is specified. If the end of the path is the end point “0”, the logical output is “0”, and if the end point is “1”, the logical output is “1”.
[0007]
The BDD logic circuit uses the BDD graph of FIG. 69A to provide logic elements such as an n-channel MOSFET 8 and a wiring 9 that satisfy the above conditions in each branch of the BDD, as shown in FIG. 69B. Make it correspond. Further, the logical output corresponds to the start points 1 and 2 of the BDD graph. Further, this is a circuit in which the ground (GND) is connected to the end point 3 of “0” of the BDD graph, and the constant power supply voltage VDD is connected to the end point 4 of “1” of the BDD graph (Reference 2: Kuroda, Sakurai, Low Power LSI white paper, page 98, published by Nikkei BP, edited by Nikkei Microdevices).
[0008]
Next, FIG. 70 shows a structure of a conventional D latch logic circuit. This logic circuit is composed of two transmission gates 601 and 602 constituting a data fetch circuit, cross-connected transmission gates 603 and 604 and inverters 605 and 606 constituting a memory circuit. A clock signal CK and its inverted signal * CK are input to the transmission gates 601 to 604, and a constant power supply voltage VDD is applied to the power supplies of the inverters 605 and 606.
[0009]
In this D latch logic circuit, when the clock signal CK is High, the signals input to the nodes 607 and 608 pass through the transmission gates 601 and 602 to reach the nodes 609 and 610, respectively, and are inverted by the inverters 605 and 606. To the nodes 611 and 612. Next, when the clock signal CK goes low, the nodes 610 and 611 are connected, the nodes 609 and 612 are connected, and the output signals of the inverters 605 and 606 are given to the input sides of the inverters 606 and 605 on the opposite side. Then, the output signal is held until the clock signal CK becomes High (memory mode).
[0010]
In addition, the wiring 400 of the conventional CMOS logic circuit such as the combinational logic circuit and the D latch logic circuit shown in FIG. 71 has a large wiring cross-sectional area in order to drive the gate of the next stage quickly in a time of about ps. Yes. As shown in FIG. 67, this wiring cross-sectional area is 550 nm (0.55 μm: signal wiring width W) in the 0.25um process of Nippon Telegraph and Telephone Corporation (NTT).₀ ) × 550 nm (0.55 μm: signal wiring thickness H₀ In this case, the CR time constant is about 0.5 ns.
[0011]
[Problems to be solved by the invention]
In the above-described retractile logic circuit, hundreds or thousands of power supply voltage waveforms must be controlled for a circuit having hundreds or thousands of gates. Therefore, when adiabatic charging and charge recycling are performed using a power reusable power source, there is a problem that power is consumed instead.
In the D latch type logic circuit, it is necessary to charge / discharge the gate of the MOSFET constituting the transmission gate and charge / discharge the clock signal line in the transmission gate portion._TGVDD² There was a problem that only excess energy was consumed. Where VDD is the power supply voltage and C_TGIs the sum of the gate capacity of the transmission gate and the capacity of the clock signal line. Also in the memory circuit, C_MEVDD² There was also a problem that extra energy was consumed. C_MEIs the capacity of the memory circuit.
Further, the conventional CMOS logic circuit has a problem that it is difficult to reduce the circuit scale because the wiring cross-sectional area is increased. In addition, there is a problem that the self-capacitance of the wiring and the mutual capacitance between the wirings cannot be reduced.
[0012]
The present invention has been made in view of the above points, and the object of the present invention is to efficiently realize adiabatic charging logic and to reduce the wiring cross-sectional area, thereby reducing the power consumption of the circuit. Another object of the present invention is to provide a logic circuit that can reduce the circuit scale.
[0013]
[Means for Solving the Problems]
In order to solve such a problem, the present invention provides a logic circuit composed of a plurality of logic elements and performs logic processing by supplying power to the logic circuit after an input signal is given to the gate of each logic element. And a power supply unit for stopping the supply of power before the logic processing is completed and a new input signal is applied to the gate of the logic element.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
The present invention will be described below with reference to the drawings.
[First Embodiment]
The content of the first embodiment is that a power reusable power supply is used instead of the constant power supply voltage VDD of the BDD logic circuit shown in FIG. After the logic of the 1000-stage gate is performed by one adiabatic charge, the electric charge stored in the BDD logic circuit is returned to the power supply circuit again.
Here, the BDD graph will be described again with reference to FIG. The BDD graph is a graph having start points 1 and 2 and end points 3 and 4, and each node 5 corresponds to an input variable (A, B, and C in the figure). When calculating the value of the logic output under the given input variable value, enter from the start point 1 or 2 of the graph, follow each node 5 downward, and finally reach one of the two end points 3 or 4 To do. Each node 5 follows one of the two branches 6 and 7 corresponding to the input variable value. That is, for example, if the input variable C is C = "0", the 0 branch 6 is followed, and if C = "1", the 1 branch 7 is followed. That is, given an input, one path from the start point to the end point is specified. If the end of the path is the end point “0”, the logical output is “0”, and if the end point is “1”, the logical output is “1”.
[0015]
The BDD logic circuit according to the first embodiment of the present invention shown in FIG. 1 associates each branch of such a BDD graph with a logic element that satisfies the above conditions, for example, an n-channel MOSFET 8 and a wiring 9. Further, the logical output is associated with the start points 1 and 2 of the BDD graph. Further, the ground (GND) is connected to the end point 3 of “0” of the BDD graph, and the power reusable power source 10 is connected to the end point 4 of “1” of the BDD graph. As the power reusable power source 10, as will be described later, for example, an AC power source circuit using an inductor and a capacitor or a power source circuit that generates an N-stage stepped voltage using N−1 capacitors is used. .
The timing of power supply to the BDD logic circuit of the power reusable power source 10 and a D latch logic circuit to be described later is controlled by a timing controller 450 as shown in FIG. 66 is a BDD logic circuit shown in FIGS. 1 and 2 and the BDD logic circuit 30B in FIG. 66 is a BDD logic circuit shown in each of FIG. Recycling of the gate portion of the BDD logic circuit by the power reusable power source 10 (# 2) will be described in fourth, fifth, sixth, and seventh embodiments described later.
[0016]
FIG. 2 shows an example of an AC power supply circuit 10A using an inductor 11 and a capacitor 12, and FIG. 3 shows an example of a power supply circuit 10B that generates three steps of stepped voltages using three capacitors 13-15.
In FIG. 3, reference numerals 16 to 23 denote n-channel MOSFETs. In these power supply circuits 10A and 10B, an AC waveform (repetitive waveform) in which the output voltage is gently increased and gradually decreased can be obtained. As another example of the AC voltage generated by the power reusable power source, a triangular wave shown in FIG. 4A and a trapezoidal wave shown in FIG. 4B can be used. Furthermore, voltage waveforms generated from the sine waves shown in FIGS. 4C, 4D, and 4E can be used. Note that the triangular wave can be generated approximately by, for example, letting a stepped waveform voltage pass through the integrating circuit.
[0017]
Next, the operation of the BDD logic circuit 30A shown in FIG. 1 will be described. First, at time t = 0, input voltages * A, * B, * C, A, B, and C are input to the gates of the n-channel MOSFETs 8 of the BDD logic circuit, respectively. Next, the output voltage of the power reusable power source 10 is gradually increased. As a result, the BDD logic circuit can be adiabatically charged. By this charging, a logical operation is performed and an output signal is obtained. Then, after this adiabatic charging, the output voltage of the power reusable power source 10 is gently lowered. At this time, the charge stored in the BDD logic circuit is returned to the power reusable power source 10 again. At time t = T after the output potential of the BDD logic circuit becomes low, the next input signal is input to the gate. Hereinafter, by repeating this as the period T, it becomes possible to execute adiabatic charging and charge recycling.
From the above, even when the number of gates is increased to several hundreds or thousands, the common power reusable power source 10 is used, so that the power consumption does not increase and is complicated unlike the conventional retractile logic circuit. Low power consumption can be realized even in a logic circuit having a logic structure.
FIG. 4 (f) is an explanatory diagram showing a comparison of power consumption in the power supply unit between the BDD logic circuit of the present invention and the conventional retractor logic circuit. As is clear from this explanatory diagram, in the conventional retractile logic circuit, the power consumption increases as the number of gates of the logic circuit increases, whereas in the BDD logic circuit of the present invention, the power consumption is always a constant low power. Is maintained.
[0018]
FIG. 5 shows an example when there are a plurality of BDD logic circuits. Here, it is assumed that there are n (n ≧ 4) BDD logic circuits as indicated by reference numerals 301 to 30n, and the i-th and j-th are adjacent (j = i + 1). At this time, each BDD logic circuit is independently operated by the optimum power reusable power source 101 to 10n. For example, as a power source for the kth BDD logic circuit, the frequency f_k , Phase φ_k The power reusable power source is used. For a BDD logic circuit that requires fast logic operation, the frequency f_k In a BDD logic circuit that uses a power reusable power source with a large value and requires a slow logic operation, the frequency f_k Use a power reusable power source with a reduced size. This makes it possible to efficiently perform parallel processing for each BDD logic circuit.
[0019]
In particular, for BDD logic circuits that require only the same frequency and the same phase power supply, a common power reusable power supply is used by connecting the power supply lines, and the number of power supply circuits is reduced to achieve low power consumption. It becomes possible to do.
FIG. 6 is a diagram showing an example using a common power reusable power source. Here, the circuit configuration is such that the first to i-th power sources are common power-reusable power sources 101 and the j-th to n-th power sources are common power-reusable power sources 10n.
[0020]
[Second Embodiment]
FIG. 7 is a diagram illustrating a BDD logic circuit according to the second embodiment.
7, in the BDD logic circuit shown in FIG. 1, among the n-channel MOSFETs 8 as logic elements, elements whose inverted signals * A, * B, and * C are input as input signals to the gates are shown as logic elements. This is an example in which the logic element has a complementary relationship with the element. That is, here, the logic element is replaced with the p-channel MOSFET 24, and the input signals to the gate are non-inverted signals A, B, and C. As a result, only non-inverted signals A, B, and C can be used as input signals, so that one inverter for creating an inverted signal from the non-inverted signal can be omitted. Therefore, power consumption can be reduced as compared with the BDD logic circuit shown in FIG. The same applies to the BDD logic circuits shown in FIGS.
[0021]
Hereinafter, an operation example of the mixed BDD logic circuit including the n-channel MOSFET 8 and the p-channel MOSFET 24 illustrated in FIG. 7 will be described in detail using simulation results. Here, as a power reusable power source, as shown in FIG. 8, a power source 10B of the type that generates three stepped voltages using three capacitors 13 to 15 (the same as that shown in FIG. 3). Is used.
This power reusable power supply 10B is composed of four constant power supply voltages VDD, 3 / 4VDD, 2 / 4VDD, 1 / 4VDD, three capacitors 13-15, and eight n-channel MOSFETs 16-23. The three capacitors 13 to 15 are charged to voltages of 3/4 VDD, 2/4 VDD, and 1/4 VDD, respectively. The input signal Pre is applied to the gates of the three n-channel MOSFETs 16 to 18, the input signals T1 to T4 are applied to the gates of the four n-channel MOSFETs 19 to 22, and the gate of one n-channel MOSFET 23 is applied. An input signal CL is applied. Note that the power supplies of 3 / 4VDD, 2 / 4VDD, and 1 / 4VDD are naturally charged to the 3 / 4VDD, 2 / 4VDD, and 1 / 4VDD, respectively, so that the capacitors 13, 14, and 15 are not stable. Become. However, here, the circuit mechanism as shown in FIG.
[0022]
9A to 9H show detailed time charts of the operation of the power reusable power source 10B. First, the input signal Pre in FIG. 9A is set to High for a predetermined time, the n-channel MOSFETs 16 to 18 are turned on, and the capacitors 13 to 15 are charged to voltages of 3 / 4VDD, 2 / 4VDD, and 1 / 4VDD, respectively. . Next, the input signals T1 to T4 shown in FIGS. 9E to 9H are set to High for a predetermined time in the order of T1, T2, T3, T4, T3, T2, and T1, and the n-channel MOSFETs 19 to 22 are set. Is turned on, and the voltages 3 / 4VDD, 2 / 4VDD, and 1 / 4VDD charged in the capacitors 13 to 15 are output as the output voltage Vout in a time-sharing manner. Finally, when the input signal T1 becomes Low, the input signal CL Is set to High to turn on the n-channel MOSFET 23 for a predetermined time to set the output voltage Vout to the ground potential. By such timing control, the output voltage Vout of the power reusable power source 10B becomes a waveform having four steps on the rising and falling edges as shown in FIG. 9C.
[0023]
The input signals (pulses) CL, T1, T2, T3, and T4 are, for example, three T-type flip-flop circuits 41 to 43, and 11 NAND circuits as shown in FIGS. It can be generated by a circuit using 44 to 54 and three inverters 55 to 57. 10A to 10F, reference numeral 200 is an input terminal for a predetermined clock CK, 211 is an output terminal for a signal T1, 212 is an output terminal for a signal T2, 213 is an output terminal for a signal T3, and 214 is a signal T4. The output terminal 215 is an output terminal for the signal CL. Other codes are nodes, and nodes with the same code are connected in common.
[0024]
In the simulation, the capacitors 13 to 15 of the power reusable power supply 10B have a capacitance of 5000 pF, and the eight n-channel MOSFETs 16 to 23 have a transistor width W of 36 μm. In each 3-input XOR BDD logic circuit of FIG. 8, the transistor width W is 6 μm, and the output load capacitance on the XOR side is 0.5 pF. Here, a simulation was performed on a circuit in which 1000 BDD logic circuits having three inputs XOR were connected in parallel. The frequency of the input clock signal CK was 4 MHz. The simulation results are shown in FIGS.
[0025]
FIG. 11 is a waveform diagram of the signals Pre, CK, CL, T1 to T4, and Vout of the power reusable power source 10B. It can be seen that a desired waveform similar to that shown in FIGS. 9A to 9H is obtained. Since the total output load is 1000 times (= 500 pF) of 0.5 pF, the waveform is a little smooth from a stepped shape.
FIG. 12 is a waveform diagram of the voltages of the input signals A, B, C, the power supply voltage Vout, and the output signals XOR, XNOR. As described above, switching of the input voltage is set to be performed when the power supply voltage Vout is at the low level. When the input signals A, B, and C are all “1”, XOR is “1” and XNOR is “0”. Further, when A = B = “1” and C = “0”, XOR is “0” and XNOR is “1”, which indicates that the logical processing is being performed well. The pulse width (bit width) of the signal C is 2 μs, and the frequency of the output voltage is 500 kHz.
[0026]
The result of power consumption is 4.76 × 10 4 at a frequency of 500 KHz.^-FourW. On the other hand, the power consumption per logical process of one normal CMOS XOR circuit is 1.06 × 10 6.^-6W, and the power consumption per logical process of 1000 XORs is 1.06 × 10^-3W. When the circuit of the present invention is used, it can be seen that the power consumption is about ½ compared with a normal CMOS logic circuit. From the above discussion, it can be confirmed that the BDD logic circuit using the power reusable power source of the present invention has low power consumption.
[0027]
[Third Embodiment]
FIG. 13 shows a BDD logic circuit according to the third embodiment using a power reusable power source. Here, the n-channel MOSFET 8 that is a logic element in the BDD logic circuit shown in FIG. 1 is replaced with a transmission gate 81 in which an n-channel MOSFET and a p-channel MOSFET are connected in parallel. The input signal of the p-channel MOSFET is an inverted signal of the input signal of the n-channel MOSFET. As a result, compared to the circuit shown in FIG. 1, a high level signal obtained as an output signal rises from VDD-Vth (Vth is the threshold voltage of the n-channel MOSFET) to the power supply voltage VDD. There is an advantage that the voltage amplitude of the signal can be increased. In other words, although the propagation characteristics of the low level signal are good in the n-channel MOSFET, the propagation of the high level signal has a voltage drop corresponding to the threshold voltage, but this can be prevented. In addition, although the propagation characteristic of a High level signal is favorable in p channel type MOSFET, propagation of a Low level signal is not good. These can be improved in the transmission gate.
[0028]
[Fourth Embodiment]
FIG. 14 shows a BDD logic circuit according to a fourth embodiment that uses a power reusable power source. An AC power source is used as the power reusable power source, and a logic is used to recycle charges stored in the input gate. AC voltages Aac, Bac, and Cac having the same frequency and phase as the AC power supply voltage V1ac are applied to the input gate of the element.
FIG. 15A to FIG. 15D show a specific circuit combining the circuit of FIG. 14 and the inverters 25 to 27. Here, the power supply voltage of the BDD logic circuit is the AC voltage V1ac. The power supply voltage of the inverter 25 that outputs the non-inverted signal A with the inverted signal * A as an input is also the AC voltage V1ac. The same applies to the other inverters 26 and 27. Here, a sine wave having an offset of 1V (center voltage 1V) and an amplitude of 1V is used as V1ac. Further, as * A, * B, and * C, signals having a low level of 0V and a high level of 2V are used.
[0029]
FIG. 16 shows the result of simulation with the operating speed set to 500 KHz. FIG. 16 shows waveform diagrams of the AC voltage V1ac, the input signals * A, A, * B, B, * C, C, and the output signals XOR, XNOR.
In the input signal A, an alternating voltage having 2V as a peak (peak) corresponds to a high level (“1”), and 0V corresponds to a low level (“0”). It can be seen that A, B, and C are 111100001, 11101001, and 1010101101 from 7 μs to 25 μs, respectively. It can also be seen that when A = B = C = “1”, XOR is “1”, A = B = “1”, and when C = “0”, XOR is “0”. About power consumption, it is 2.71 × 10 in the BDD logic circuit.^-7W. It can be seen that the power consumption of the AC BDD logic circuit shown here is reduced to about ¼ compared to CMOS.
Here, a sine wave is used as the AC voltage, but it is not necessarily a sine wave. For example, the voltage Vlac is generated from the triangular wave, trapezoidal wave, or sine wave shown in FIGS. It may be a voltage waveform. Of course, a step-like voltage waveform (Vout in FIG. 9C) obtained by the power reusable power source 10B shown in FIG. 8 may be used.
[0030]
[Fifth Embodiment]
FIGS. 17A to 17F and FIG. 18 show examples of the BDD logic circuit according to the fifth embodiment using a power reusable power source. Here, when the AC power source V1ac is used as the power reusable power source of the BDD logic circuit shown in FIG. 13, instead of using the inverters 25 to 27 shown in FIGS. 15A to 15C, the transmission gate 81 Use a circuit connected in series. Then, as shown in FIGS. 17A and 17B, logic signals Ain and * Ain are input to generate AC voltage signals A and * A. Further, as shown in FIGS. 17C and 17D, the logic signals Bin and * Bin are inputted to generate the AC voltage signals B and * B. Further, as shown in FIGS. 17E and 17F, the logic signals Cin and * Cin are inputted to generate the AC voltage signals C and * C. The AC voltages A, * A, B, * B, C, * C are input to the BDD logic circuit of FIG. 18 to perform logic processing.
[0031]
[Sixth Embodiment]
FIGS. 19A to 19D are examples of the BDD logic circuit according to the sixth embodiment using the power reusable power source. The AC voltage V1ac is used as the input voltage, and the power reusable power source is used. Uses an alternating voltage V2ac '. The AC voltage V2ac 'has a frequency twice that of the AC voltage V1ac. Further, an n-channel MOSFET 28 having a switching function is connected between the BDD logic circuit and the AC voltage V2ac '. By supplying a clock signal φ (the same frequency as that of the AC signal V1ac) as shown in the figure to the gate of the n-channel MOSFET 28, the AC voltage V2ac obtained by taking every other peak of the AC voltage V2ac 'is used as the power supply voltage.
[0032]
The simulation result is shown in FIG.
Here, waveforms of AC voltage V2ac ', clock signal φ, AC voltage V2ac after passing through n-channel MOSFET 28, AC voltage V1ac, input signal C, and output signals XOR and XNOR are shown. Input signals A and B are the same as the waveforms in FIG. It can be seen that the XOR and XNOR signals are correctly output as in the result shown in FIG.
In this circuit, the power consumption is 3.6 × 10^-8W, which is about 1/30 lower power than CMOS. This is considered to be because the waveform of the AC voltage V2ac of the power supply is contained in the waveform of the AC voltage V1ac that is input, so that there is almost no leakage from the power supply to the ground.
[0033]
[Seventh Embodiment]
FIGS. 21A to 21F and FIG. 22 are examples of the BDD logic circuit of the seventh embodiment using the power reusable power source. The AC voltage V1ac described above is used as the input voltage, and FIG. An AC voltage V2ac ′ is used as a power reusable power source for the BDD logic circuit shown. The AC voltage V2ac 'has a frequency twice that of the AC voltage V1ac. Further, a transmission gate 91 is connected between the BDD logic circuit and the AC voltage V2ac 'as shown in FIG. The transmission gate 91 is supplied with a clock signal φ (same frequency as the AC signal V1ac) and a clock * φ as shown in the figure, and the AC voltage V2ac obtained by taking every other peak of the AC voltage V2ac ′ is used as the power supply voltage.
In the seventh embodiment and the fifth and sixth embodiments described above, as described above, the AC voltage need not be a sine wave, but a trapezoidal wave or a power reusable power source 10B. It may be a stepped waveform or the like. The timing relationship between the AC voltages V1ac and V2ac only has to rise so that V1ac rises faster than V2ac and falls later. Some examples are shown in FIG.
[0034]
[Eighth Embodiment]
FIG. 24A shows a BDD logic circuit according to the eighth embodiment. Here, the power reusable power source 10 of the BDD logic circuit shown in FIG. 1 is replaced with a power non-reusable power source 10 '. The power non-reusable power source 10 ′ is an AC power source that does not reuse power (generates a voltage that changes periodically with a slow rise and fall). The AC power source, the power reusable power source 10, and the power non-reusable power source 10 'have a relationship as shown in FIG.
FIG. 25 is a diagram showing a circuit including a specific example of the power non-reusable power source 10 '. Here, the rectangular wave output from the inverter 35 is integrated by the resistor 36 and the capacitor 37 to create a repetitive voltage with a gentle rise and fall. Such an AC power source that does not reuse power cannot recycle charges, but unlike rectangular waves, it can be adiabatically charged, and has the advantage that power consumption is halved.
[0035]
[Ninth Embodiment]
FIG. 26 is a diagram illustrating an example of the IC card 60 according to the ninth embodiment. Here, when there is an AC voltage that is induced via a inductor (antenna) 62 from a wireless electromagnetic wave such as a reader / writer 61 used for communication (or power transmission), this AC voltage itself is used as the IC card 60. This is used as a power reusable power supply voltage. Here, 63 is a BDD logic circuit, 64 is a rectifying power supply circuit for creating a DC power supply for the CMOS logic circuit 65, and 66 is a capacitor. M is the mutual conductance.
[0036]
[Tenth embodiment]
FIG. 27 is a diagram illustrating a part of the BDD logic circuit according to the tenth embodiment. Here, a complementary TFT (Thin Film Transistor) is used as a logic element instead of a complementary MOSFET. Even with a circuit configuration using such TFTs, adiabatic charging and charge recycling are possible. In the case of a TFT, it operates at a lower speed than a MOSFET, and is considered a device that is extremely suitable for adiabatic charging.
[0037]
A circuit using this TFT can be three-dimensionally highly integrated, whereby elements can be connected in parallel in the thickness direction, and the logic processing speed can be improved. In FIG. 27, 71 is a substrate, 72 is an insulating film, 73 is a metal or polysilicon wiring or gate, 74 is a gate insulating film, 75 is an n-type region serving as a source or drain, and 76 is a p-type region serving as a channel. , 77 is a p-type region serving as a source or drain, 78 is an n-type region serving as a channel, and 79 is a global through hole.
Here, the BDD logic circuits used in the second to seventh embodiments (FIGS. 7, 8, 13, 14, 15 (d), 18, 19 (d), and 22 are used. However, the present invention can also be applied to the non-complementary BDD logic circuit of the first embodiment shown in FIGS. 1 to 3 and FIGS. 5 and 6. .
[0038]
[Eleventh embodiment]
FIG. 28E is a diagram for explaining a BDD graph used in the BDD logic circuit according to the eleventh embodiment of the present invention. The BDD graph shown in FIG. 28E is obtained by sharing the BDD graphs shown in FIGS.
FIGS. 29A and 29B are BDD logic circuits using the shared BDD graph shown in FIG. By sharing each BDD graph in this way, the number of transistors used in the BDD logic circuit can be reduced.
[0039]
[Twelfth embodiment]
FIG. 30 is a diagram showing a configuration of a BDD logic circuit 30B according to the twelfth embodiment of the present invention. Here, a BDD logic circuit for inputting input signals A, * A, B, * B, C, * C and taking out their carry outputs f = (AB + BC + CA) and * f = * (AB + BC + CA). showed that. The BDD logic circuit 30B after the twelfth embodiment is different from the BDD logic circuit 30A shown in the first to eleventh embodiments described above by connecting the power reusable power source 10 to the starting point 1 and supplying the power supply voltage. The output signal f is extracted from “1” at the end point 4, and the output signal * f is extracted from “0” at the end point 3. Note that the waveform of the output voltage of the power reusable power source 10 is a stepped waveform as shown in FIGS. 4A to 4E and FIG. The waveform changes smoothly).
[0040]
31 (a) and 31 (b) show two-bit input signals A0 and A1, two-bit input signals B0 and B1, and one-bit carry C0 in the 2-bit adder 140 shown in FIG. 31 (c). Is input to output sum output signals S1 and * S1. Here, FIG. 31A shows the BDD graph, FIG. 31B shows the logic circuit, and FIG. 31C shows the input / output relationship of the adder 140.
32 (a) and 32 (b) show two-bit input signals A0 and A1, two-bit input signals B0 and B1, and one pit in the 2-bit adder 140 shown in FIG. It is explanatory drawing when carrying C0 is input and the output signals C2 and * C2 of carry are output. 32A shows the BDD graph, FIG. 32B shows the logic circuit, and FIG. 32C shows the input / output relationship of the adder 140.
[0041]
Here, as the power reusable power supply 10, an AC power supply circuit using an inductor and a capacitor, or a power supply circuit that generates an N-stage stepped voltage using N−1 capacitors can be used.
FIG. 33 shows an example of an AC power supply circuit 10 </ b> A using the inductor 11 and the capacitor 12.
FIG. 34 shows an example of a power supply circuit 10B that generates four steps of stepped voltages using three capacitors 13-15. In FIG. 34, reference numerals 16 to 23 denote n-channel MOSFETs. In these power supply circuits 10A and 10B, the output voltage can be gradually increased and gradually decreased.
[0042]
Next, the operation of the BDD logic circuit shown in FIG. 34 will be described.
First, at time t = 0, input signals * A, * B, * C, A, B, and C are input to the gates of the n-channel MOSFETs 8 of the BDD logic circuit. Next, the output voltage of the power reusable power source 10B is gradually increased. As a result, the BDD logic circuit can be adiabatically charged. By this charging, a logical operation is performed and an output signal is obtained. Then, after this adiabatic charging, the output voltage of the power reusable power source 10B is gently lowered. At this time, the electric charge stored in the BDD logic circuit is returned to the power reusable power source 10B. After the potential of the BDD logic circuit becomes low, the next input signal is input to the gate at time t = T. Hereinafter, by repeating this as the period T, it becomes possible to execute adiabatic charging and charge recycling.
[0043]
From the above, even when the number of gates increases to several hundreds or thousands, a common power reusable power source is used, so power consumption does not increase and even logic circuits with complex logic structures consume less power. Electric power can be realized.
The specific operation of the power reusable power source 10B shown in FIG. 34 is the same as that already described with reference to the time chart of FIG.
Further, the circuit for generating each input signal supplied to the power reusable power source 10B is also equivalent to the circuit of FIG.
Further, in the power reusable power source 10B, a voltage waveform equivalent to Vout in FIG. 9C described above is generated and applied to the BDD logic circuit.
[0044]
FIG. 35 shows an example where there are a plurality of BDD logic circuits. Here, it is assumed that there are n (n ≧ 4) BDD logic circuits as indicated by 301 to 30n, and the i-th and j-th are adjacent (j = i + 1). At this time, each BDD logic circuit is independently operated by the optimum power reusable power source 101 to 10n. For example, as a power source for the kth BDD logic circuit, the frequency f_k , Phase φ_k The power reusable power source is used. In a BDD logic circuit that requires fast logic operation, f_k In a BDD logic circuit that uses a power reusable power source with a larger value and that requires slower logic operation, f_k Use a power reusable power source with a reduced size. This makes it possible to efficiently perform parallel processing for each BDD logic circuit.
In particular, for BDD logic circuits that require only the same frequency and the same phase power supply, a common power reusable power supply is used by connecting the power supply lines, and the number of power supply circuits is reduced to achieve low power consumption. It becomes possible to do.
FIG. 36 is a diagram illustrating an example in which a common power reuse type power source is used. The first to i th power sources are common power reuse type power sources 101 and the j th to n th power sources are common. The circuit configuration is a power reusable power source 10n.
[0045]
[Thirteenth embodiment]
FIG. 37 shows a BDD logic circuit according to the thirteenth embodiment. Here, in the BDD logic circuit shown in FIG. 30, among the n-channel MOSFET 8 as the logic element, an element in which the inverted signals * A, * B, * C of FIG. The logic element is replaced with a logic element having a complementary relationship. That is, here, it is replaced with the p-channel type MOSFET 24, and the input signals to the gate thereof are non-inverted signals A, B, C. As a result, only non-inverted signals A, B, and C can be used as input signals, so that one inverter for creating an inverted signal from the non-inverted signal can be omitted. Therefore, the circuit scale and power consumption can be reduced compared to the circuit shown in FIG. The same applies to the BDD logic circuits shown in FIGS. 31B, 32B, 33, 34, 35, and 36.
[0046]
[Fourteenth embodiment]
FIG. 38 shows a BDD logic circuit according to a fourteenth embodiment using a power reusable power source. Here, each n-channel MOSFET 8 that is a logic element in the BDD logic circuit shown in FIG. 30 is replaced with a transmission gate 81 in which an n-channel MOSFET and a p-channel MOSFET are connected in parallel. The input signal of the p-channel MOSFET is an inverted signal of the input signal of the n-channel MOSFET. Thus, compared to the circuit shown in FIG. 30, the high level signal obtained as the output signal rises from VDD-Vth (Vth is the threshold voltage of the n-channel MOSFET) to the power supply voltage VDD. There is an advantage that the voltage amplitude can be increased. That is, in the n-channel MOSFET, the propagation characteristic of the low level signal is good, but the propagation of the high level signal has a voltage drop corresponding to the threshold voltage, but this can be prevented. In addition, although the propagation characteristic of a High level signal is favorable in p channel type MOSFET, propagation of a Low level signal is not good. These can be improved in the transmission gate.
[0047]
[Fifteenth embodiment]
FIG. 39 shows a BDD logic circuit according to a fifteenth embodiment using a power reusable power source. In order to recycle the charge stored in the input gate using an AC power source as the power reusable power source. The AC voltages Aac, Bac, and Cac having the same frequency and phase as the AC voltage V1ac of the power supply are applied to the input gates of the logic elements.
FIG. 40A to FIG. 40D show a specific circuit combining the circuit of FIG. 39 and the inverters 25 to 27. The power supply voltage of the BDD logic circuit is an alternating voltage V1ac. The power supply voltage of the inverter 25 that receives the inverted signal * A and outputs the non-inverted signal A is also the AC voltage V1ac. The same applies to the power supply voltages of the other inverters 26 and 27. Here, for example, a sine wave having an offset of 1V (center voltage 1V) and an amplitude of 1V is used as V1ac. Further, as * A, * B, and * C, signals having a low level of 0V and a high level of 2V are used.
Here, a sine wave is used as the AC voltage, but it is not necessarily a sine wave. For example, the voltage V1ac may be a voltage waveform generated from the triangular wave, trapezoidal wave, or sine wave shown in FIGS. 4 (a) to 4 (e). Of course, a step-like voltage waveform (Vout in FIG. 9C) obtained by the power reusable power source 10B shown in FIG. 8 may be used.
[0048]
[Sixteenth embodiment]
FIGS. 41A to 41F and FIG. 42 are examples of the BDD logic circuit according to the sixteenth embodiment using the power reusable power source. Here, when the AC power source V1ac is used as the power reusable power source of the BDD logic circuit shown in FIG. 39, instead of using the inverters 25 to 27 as shown in FIGS. 40 (a) to (c), A circuit in which transmission gates 81 are connected in series is used. Then, as shown in FIGS. 41A and 41B, the logic signals Ain and * Ain are input to generate the AC voltage signals A and * A. Further, as shown in FIGS. 41C and 41D, the logic signals Bin and * Bin are inputted to generate the AC voltage signals B and * B. Further, as shown in FIGS. 41 (e) and (f), the logic signals Cin and * Cin are inputted to generate the AC voltage signals C and * C. Then, the generated AC voltages A, * A, B, * B, C, * C are input to the BDD logic circuit of FIG. 42 to perform logic processing.
[0049]
[Seventeenth embodiment]
FIGS. 43A to 43D show examples of the BDD logic circuit according to the seventeenth embodiment using a power reusable power source. The AC voltage V1ac is used as the input voltage, and the power source of the BDD logic circuit is shown in FIGS. For this, an alternating voltage V2ac 'is used. The AC voltage V2ac 'has a frequency twice that of the AC voltage V1ac. Further, an n-channel MOSFET 28 having a switching function is connected between the BDD logic circuit and the AC voltage V2ac '. By applying a clock signal φ (same frequency as the AC signal V1ac) as shown in the figure to the gate of the n-channel MOSFET 28, the AC voltage V2ac obtained by extracting every other beak of the AC voltage V2ac ′ is used as the power supply voltage. To do.
[0050]
[Eighteenth embodiment]
44 (a) to 44 (f) and FIG. 45 are examples of the BDD logic circuit according to the eighteenth embodiment using a power reusable power source, and the above-described AC voltage V1ac is used as an input voltage. The AC voltage V2ac ′ is used as the power reusable power source of the BDD logic circuit shown in FIG. 4B, and every other beak of the AC voltage V2ac ′ is taken out like the BDD logic circuit of FIG. The voltage V2ac is the power supply voltage.
In the eighteenth embodiment and the sixteenth and seventeenth embodiments described above, the AC voltage need not be a sine wave, as shown in FIGS. 23 (a) to 23 (h). Alternatively, an AC voltage based on a trapezoidal wave, a triangular wave, and a sine wave, or a stepped waveform by the power reusable power source 10B may be used. In addition, the timing relationship between the alternating voltages V1ac and V2ac only needs to rise faster than V1ac and fall later.
[0051]
[Nineteenth embodiment]
FIG. 46A shows a BDD logic circuit according to the nineteenth embodiment. Here, the power reusable power source 10 of the BDD logic circuit shown in FIG. 30 is replaced with a power non-reusable power source 10 '. This power non-reusable power source 10 'is an AC power source that does not reuse power. The AC power source, the power reusable power source 10, and the power non-reusable power source 10 'have a relationship as shown in FIG.
FIG. 47 is a diagram showing a specific example of this non-reusable power source 10 '. Here, the rectangular wave output from the inverter 35 is integrated by the resistor 36 and the capacitor 37 to create an alternating voltage with a slow rise and fall. Even if such an AC power source that does not reuse power is different from a rectangular wave, it can be charged adiabatically, so that there is an advantage that power consumption is halved.
Note that TFTs that are extremely suitable for adiabatic charging can be used as the elements of the logic circuits of the twelfth to nineteenth embodiments as described above. Further, as shown in FIG. 27, it is possible to integrate three-dimensionally.
Further, the logic circuits of the twelfth to nineteenth embodiments described above can be similarly applied to the IC card 60 already described in the ninth embodiment of FIG.
[0052]
[20th embodiment]
FIG. 48A shows a D latch logic circuit 90 which is a logic circuit according to the twentieth embodiment of the present invention. The circuit 90 includes two transmission gates 91 and 92 constituting a data fetch circuit, cross-connected transmission gates 93 and 94 and inverters 95 and 96 constituting a storage circuit.
[0053]
Here, as the power supply voltage of the inverters 95 and 96, as shown in FIG. 48B, a voltage V3ac having a waveform with a gradual rise and fall is used. Further, as shown in FIG. 48C, the clock signal rises after the voltage V3ac falls, falls before the voltage V3ac rises, and has a waveform with a small duty and a slow rise and fall. And its inverted voltage * V4ac. The voltages V3ac and V4ac are generated by switching and charging / discharging the oscillation type power supply circuit 10A shown in FIG. Stepped power supply circuit 10B shown in FIGS. 3 and 8, a power reusable power supply such as a power supply circuit generated as shown in FIGS. 4 (a) to 4 (e) using one or a plurality of sine waves, The alternating current obtained by the inductor for inducing wireless electromagnetic waves described in FIG. 26 is used. Also, a waveform similar to that shown in FIGS. 23A to 23H (a waveform obtained by shifting the phase of V2ac by 180 degrees with respect to V1ac) can be used. Further, the non-reusable power source 10 '(FIG. 24 (a), FIG. 25) can be used to generate the voltages V3ac and V4ac.
[0054]
In the D latch logic circuit 90, first, in the process in which the voltage V4ac changes from Low → High → Low, the transmission gates 91 and 92 are temporarily turned on, and the signal input to the nodes 97 and 98 at this time is the node 99. , 100. When the voltage V4ac changes from High to Low, the transmission gates 91 and 92 are cut off and the transmission gates 93 and 94 are turned on to enter the storage mode. When this storage mode is entered, V3ac = 0 is initially set, so that the node 102 or 103 has the voltage Vth (inverters 95, 96) even when the output signal at that time should be in a high state. (Threshold voltage of the p-channel MOSFET constituting). If it is a Low state, it remains at 0V.
[0055]
Next, when the voltage V3ac rises from 0V toward the power supply voltage VDD, the potential of the node 102 or 103 that is the threshold value Vth slowly rises to the power supply voltage VDD. Thereafter, when the voltage V3ac is changed from VDD to 0V, the potential of the node 102 or 103 which has been the power supply voltage VDD is lowered to the threshold voltage Vth.
By such a series of processes, charging is performed almost adiabatically in the process of increasing from the threshold voltage Vth to the power supply voltage VDD. Furthermore, when a power reusable power source is used for the voltage V3ac, the charge is adiabatically recycled to the power source side of V3ac in the process of dropping from the power source voltage VDD to the threshold value Vth. Such adiabatic charging and charge recycling are similarly performed in the transmission gate portion driven by the voltages V4ac and * V4ac.
[0056]
From the above, in the portion driven by the clock signal (transmission gates 91 to 94), the charge / discharge energy is C as described above in the conventional circuit (FIG. 70)._TGVDD² However, in the circuit of the present invention, C_TGVDD² ・ It becomes 2τ / T times like 2τ / T. Here, τ is the CR time constant of the circuit when charging with the voltage V4ac, and T is the rise time (fall time) of the voltage V4ac. Therefore, by setting τ << T, if the battery is charged and discharged sufficiently slowly, as shown in FIG. 49A, the energy can be sufficiently reduced, and the power consumption can be reduced.
On the other hand, in the portion related to the memory circuit, in the circuit of the present invention, since the information is stored in Vth instead of VDD, the charging energy is 1/2 · C of the conventional circuit._MEVDD² To 1/2 · C_MEVth² Can be reduced. Therefore, the energy required for charging / discharging of this portion is C in the conventional circuit as described above._MEVDD² What was was C_MEVth² + C_MEVDD² 2τ / T (FIG. 49 (b)). Note that T and τ are the same as those for driving the clock signal portion.
Thus, it can be seen that the D latch logic circuit 90 of the present invention can reduce power consumption in both the transmission gate portion and the storage circuit portion.
[0057]
[Twenty-first embodiment]
FIG. 50 is a diagram showing a D latch logic circuit according to a twenty-first embodiment of the present invention. Each of the power latches 97 and 98 on the input side of the D latch logic circuit 90 shown in FIG. The outputs of the use-type BDD logic circuits 110 and 120 are connected.
The BDD logic circuits 110 and 120 are composed of a combination of an n-channel MOSFET 8 and a p-channel MOSFET 24. The signals A, B, and C applied to the gates of the MOSFETs are converted into rectangular wave input signals * by inverters 131 to 133 using the voltage V3ac as a power supply voltage, as shown in FIGS. Waveforms of a, * b, and * c are converted (inverted and rising and falling slopes correspond to rising and falling of the voltage V3ac).
[0058]
Also, here, the p-channel MOSFET 24 is connected to the path for transmitting the outputs of the BDD logic circuits 110 and 120 of FIG. 50 to the nodes 97 and 98 of the D latch logic circuit 90, and the gate of FIG. The inverted voltage * V5ac of the voltage V5ac having a waveform as shown in FIG. This voltage V5ac is also a voltage generated by the power reusable power source or the power non-reusable power source described above, and has a waveform that rises later and falls faster than the voltage V3ac in FIG. It is also applied to one end point of the BDD logic circuit 110 and the other end point of the BDD logic circuit 120.
[0059]
Next, the operation of the BDD logic circuit of FIG. 50 will be described.
First, the input signals A, B, and C are input to the BDD logic circuits 110 and 120 while changing to High and Low in synchronization with the voltage V3ac. Next, when the voltage V5ac rises, a power supply voltage is applied to the BDD logic circuits 110 and 120. Therefore, logical processing (in the BDD circuit 110, processing of exclusive OR (XOR) of signals A, B, and C, in BDD logic circuit 120, processing of inverted exclusive OR (XNOR) of signals A, B, and C). The result of this logic processing (Low or High signal) is transmitted to the nodes 97 and 98 in synchronization with the rise of the voltage V5ac, and then the voltage V5ac falls. At this time, the signals are stored in the nodes 97 and 98. Further, after the voltage V5ac falls, the voltage V3ac also falls, and the input signals A, B, C of the BDD logic circuits 110, 120 fall.
[0060]
Next, when voltage V4ac rises, transmission gates 91 and 92 become conductive, and the signals at nodes 97 and 98 are transferred to nodes 99 and 100. Thereafter, an operation similar to the operation described with respect to the circuit of FIG. 48A is performed in the D latch logic circuit 90, and a signal obtained by inverting the signals input to the nodes 97 and 98 is synchronized with the voltage V3ac. , 103. The signal Q output to the nodes 102 and 103 or its inverted signal * Q is used as an input signal of a D latch logic circuit having the same configuration in the next stage, or input signals A, B and C of the BDD logic circuits 110 and 120. Any one of them can be used.
52D to 52H are explanatory diagrams when the output of the D latch logic circuit 90 is input to the BDD logic circuits 110 and 120. FIG.
As described above, in the logic circuit of the twenty-first embodiment, logical processing is performed by adiabatic charging and charge recycling in the BDD logic circuits 110 and 120, and the processing result is input to the D latch logic circuit 90. Since logic processing can be performed by adiabatic charging and charge recycling and sent to another circuit in the next stage or the input side of the BDD logic circuits 110 and 120, low power consumption can be realized.
[0061]
[Twenty-second embodiment]
FIG. 53A is a diagram showing a D latch logic circuit according to a twenty-second embodiment of the present invention. In the nodes 102 and 103 on the output side of the D latch logic circuit 90 shown in FIG. An inverter circuit 130 composed of a pair of inverters 104 and 105 is connected. In the figure, 106 and 107 are output nodes.
Here, as shown in FIG. 53C, the power supply voltage V6ac of the inverters 104 and 105 rises and falls slowly and rises later than the rise of the voltage V3ac shown in FIG. Voltage. The power source V6ac is also a voltage generated by the power reusable power source or the power non-reusable power source described above.
[0062]
When the inverter circuit 130 is not provided and a load having a very large capacity is connected to the output nodes 102 and 103 of the D latch logic circuit 90, the signal transmitted from the node 102 or 103 to the transmission gates 93 and 94 Even when it should become high (at this time, since V3ac = 0V, it becomes the threshold value Vth as described above), it instantaneously becomes 0V, and this is transmitted to the load side to hold data. An error may occur.
In this regard, as in this embodiment, by connecting an inverter circuit 130 to the nodes 102 and 103 and connecting a large capacity load to the nodes 106 and 107 of the inverter circuit 130, the nodes 106 and 107 are Since the signal transmitted by the transmission gates 93 and 94 is no longer received directly, the data can be held correctly.
[0063]
[Twenty-third embodiment]
54 is a diagram showing a D latch logic circuit according to a twenty-third embodiment of the present invention. In FIG. 54, the nodes 97 and 98 on the input side of the D latch logic circuit 90 shown in FIG. The BDD logic circuits 110 and 120 shown are connected.
In this embodiment, timing and waveform voltages as shown in FIGS. 55A to 55D are used as the voltages V3ac, V4ac, V5ac, and V6ac. In particular, the voltage V5ac has a waveform that rises late and falls faster than the voltage V6ac, and the voltage V6ac has a waveform that rises late and falls faster than the voltage V3ac.
As a result, the processing contents (XOR, XNOR) of the signals A, B, C input to the MOSFETs of the BDD logic circuits 110, 120 are output to the nodes 97, 98 in synchronization with the voltage V5ac, and then to the voltage V4ac. The data is transferred to the nodes 99 and 100 in synchronization, subsequently transferred to the nodes 102 and 103 in synchronization with the voltage V3ac, and further transferred to the nodes 106 and 107 in synchronization with the voltage V6ac. The signals obtained at the nodes 106 and 107 can be input signals to the BDD logic circuits 110 and 120.
[0064]
[Twenty-fourth embodiment]
FIG. 56A shows a D latch logic circuit 90A according to the twenty-fourth embodiment of the present invention. The transmission gates 91 and 92 of the D latch logic circuit 90 shown in FIG. The type MOSFET 8 is used instead. In this case, a non-inverted voltage V4ac is applied to the gate of the MOSFET 8. The transmission gates 91 and 92 can be replaced with a p-channel MOSFET 24 as shown in the D latch logic circuit 90B of FIG. At this time, a voltage * V4ac obtained by inverting the voltage V4ac is applied to the gate of the MOSFET 24.
By using a single MOSFET as the transfer gate as described above, the number of transistors can be reduced.
[0065]
[Twenty-fifth embodiment]
FIGS. 57A to 57C show a logic circuit according to the twenty-fifth embodiment. Here, in the 2-bit adder 140 shown in FIG. 57 (c), a circuit portion for outputting the sum S1 and the inverted signal * S1 thereof from 2-bit data A1, A0, B1, B0 and 1-bit carry C0. As shown in FIG. 57 (b), this is composed of a PMOS latch logic circuit 140A and a BDD logic circuit 140B.
First, in the PMOS latch logic circuit 140A, two p-channel MOSFETs 24 are used without using a transmission gate or an inverter, and the voltage V3ac is connected to the source. The BDD logic circuit 140B is obtained by realizing the BDD graph shown in FIG. 57A by a plurality of n-channel MOSFETs 8, and the output signal S1 of the BDD logic circuit 140B appearing at nodes 141 and 142 and its inversion. The signal * S1 is held by the PMOS latch logic circuit 140A and transferred to the next stage (not shown). The starting point of the BDD logic circuit 140B is grounded.
[0066]
In this embodiment, after the input signals A1, A0, B1, B0, and C0 are input, the power supply voltage V3ac rises, thereby performing logic processing, after which the voltage V3ac falls, and then the input signals A1, A0, B1, B0, and C0 fall. The output nodes 141 and 142 of the PMOS latch logic circuit 140A have their High side lowered to the threshold voltage Vth of the p-channel MOSFET when the voltage V3ac = 0, and adiabatic when the voltage V3ac rises to the power supply voltage VDD. Since charging is performed when the battery is charged and then the voltage V3ac drops to 0V, power consumption can be reduced.
[0067]
That is, by combining the PMOS latch logic circuit and the BDD logic circuit, the output signal S1 and its inverted signal * S1 can be correctly brought to the peak value of V3ac and the signal voltage value of Low to 0V. In addition, if a BDD logic circuit is used, it becomes possible to incorporate the circuit efficiently by reducing the number of transistors, and the design and configuration is easy even for a large-scale BDD logic circuit by design using a computer. There is an advantage that can be done.
In addition to the above-described gate input and power supply voltage control method, it is needless to say that control by a four-phase clock method is possible (Reference 3: Y. Moon and DK Jeong “An Effective Charge Recovery Logic Circuit”). (IEEE Journal of Solid-state circuits p.514)
[0068]
[Twenty-sixth embodiment]
FIGS. 58A to 58C are diagrams showing a logic circuit according to the twenty-sixth embodiment. Here, in 2-bit adder 140 shown in FIG. 58 (c) (same as the circuit of FIG. 57 (c)), 2-bit data A1, A0 and B1, B0, 1-bit carry C0, carry C2 and The circuit portion for outputting the inverted signal is composed of a PMOS latch logic circuit 140C and a BDD logic circuit 140D as shown in FIG. 58 (b).
[0069]
Similarly to the PMOS latch logic circuit 140A, the PMOS latch logic circuit 140C uses two p-channel MOSFETs 24, and the voltage V3ac is connected to the source. The BDD logic circuit 140D is obtained by realizing the BDD graph shown in FIG. 58 (a) with a plurality of n-channel MOSFETs 8. The output signal C2 of the BDD logic circuit 140D appearing at nodes 143 and 144 and its inverse. The signal * C2 is latched by the PMOS latch logic circuit 140C and transferred to the next stage (not shown).
The operation of this embodiment is almost the same as that of the circuit shown in FIG. 57B, and the output nodes 143 and 144 have the High side set to the threshold Vth of the p-channel MOSFET when the voltage V3ac = 0. Since the charge is adiabatically charged when the voltage V3ac rises to VDD and then the charge is recycled when the voltage V3ac falls to 0V, the power consumption can be reduced.
[0070]
[Twenty Seventh Embodiment]
FIG. 59 is a diagram showing a logic circuit according to a twenty-seventh embodiment. This logic circuit is constituted by an NMOS BDD logic circuit 140B (or 140D) and a flip-flop circuit composed of inverters 140G1 and 140G2. is there.
60A and 60B show connection examples of the flip-flop circuit 140G including the inverters 140G1 and 140G2 and the NMOS BDD logic circuit 140B (or 140D).
[0071]
[Twenty-eighth embodiment]
FIG. 61A shows a logic circuit according to the twenty-eighth embodiment, which is a modification of the logic circuit shown in FIG. Here, the NMOS latch logic circuit is composed of an n-channel MOSFET 8 as shown by 140A ′ and the source thereof is grounded, and the BDD logic circuit is composed of a p-channel MOSFET 24 as shown by 140B ′. The voltage V3ac is connected to the starting point.
Here, the logical processing result of the BDD logic circuit 140B 'appears at the nodes 141 and 142 when the voltage V3ac rises and is latched by the NMOS latch logic circuit 140A'. In other words, adiabatic charging and charge recycling are also performed here.
[0072]
[Twenty-ninth embodiment]
FIG. 61B is a diagram showing a logic circuit according to the 29th embodiment, which is a modification of the circuit shown in FIG. Here, the NMOS latch logic circuit is composed of an n-channel MOSFET 8 as shown by 140C ′ and the source thereof is grounded, and the BDD logic circuit is composed of a p-channel MOSFET 24 as shown by 140D ′. The starting point is connected to the voltage V3ac.
Again, the logical processing result of the BDD logic circuit 140D 'appears at the nodes 143 and 144 when the voltage V3ac rises, and adiabatic charging and charge recycling are performed.
[0073]
[Thirty Embodiment]
FIG. 62A shows a logic circuit according to the thirtieth embodiment, which is a modification of the circuit shown in FIG. Here, the voltage V3ac is connected to the source of the p-channel MOSFET 24 of the PMOS latch logic circuit 140A, and the same voltage V3ac is also connected to the starting point of the BDD logic circuit 140B.
Here, the side of the nodes 141 and 142 where the low signal appears is floating, but it is not high impedance and has a potential close to the ground potential. This was confirmed by simulation. On the side where the high signal appears, adiabatic charging and charge recycling are performed.
[0074]
[Thirty-first embodiment]
FIG. 62B shows a logic circuit according to the thirty-first embodiment, which is a modification of the circuit shown in FIG. Here, the voltage V3ac is connected to the source of the p-channel MOSFET 24 of the PMOS latch logic circuit 140C, and the same power supply V3ac is also connected to the starting point of the BDD logic circuit 140D.
Again, the side of the nodes 143 and 144 where the Low signal appears is floating, but it is not high impedance and has a potential close to the ground potential. On the side where the High signal appears, adiabatic charging and charge recycling are performed.
[0075]
[Thirty-second embodiment]
FIGS. 63A and 63B are diagrams showing the logic circuit of the thirty-second embodiment. Each of the BDD logic circuits 140E and 140F connected to the PMOS latch logic circuit 140C and the NMOS latch logic circuit 140A ′, respectively. The MOSFET is a mixed type of N-channel MOSFET and P-channel MOSFET. Thereby, the inverter connected to each input gate can be omitted.
Note that TFTs that are extremely suitable for adiabatic charging as described in FIG. 27 can be used for the elements of the logic circuits of the twentieth to thirty-second embodiments.
[0076]
[Thirty-third embodiment]
By the way, in the conventional CMOS logic circuit, the current density is set to a certain upper limit value J in order to avoid disconnection due to electromigration.₀ The following are set. In general, the life τ of wiring due to electromigration is
τ = KST / {J² Dexp (−ΔE / kT)} (1)
(Reference 4: CMOS VLSI design, page 87, supervised by Takuo Kanno, edited by Tetsuya Iizuka, published by Baifukan). Here, K is a proportional constant, S is a wiring cross-sectional area, T is an absolute temperature, J is a current density, D is a diffusion coefficient of aluminum atoms, and k is a Boltzmann constant.
[0077]
Thus, it can be seen that when the wiring width is shortened and the current density J is increased, the time τ until disconnection is shortened. Therefore, it can be seen that there is a lower limit for the wiring cross-sectional area in the case of a CMOS logic circuit. In other words, the current density has an upper limit value.
For example, in an actual CMOS logic LSI, when the power supply voltage is 2 V, a current of about 8 mA flows in the signal line, and the current density is 2.7 × 10.⁶ A / cm² Degree. The cross-sectional area of the signal line at this time is (0.55 μm)² = 0.30 μm² (See FIGS. 64B and 71).
[0078]
On the other hand, in a BDD logic circuit, a D latch logic circuit, or the like using the adiabatic charging logic, the current density flowing through the metal wiring or the transistor becomes very small because charging and discharging are performed adiabatically. Therefore, the electromigration effect in the wiring is also reduced. Therefore, compared with the conventional case, the wiring cross-sectional area is described above (0.55 μm).² = 0.30 μm² Can be made smaller.
Therefore, in the thirty-third embodiment, in the logic circuit that performs adiabatic charging logic, the wiring cross-sectional area is reduced while keeping the lifetime due to electromigration at the same level as that in the conventional CMOS logic circuit, The reduction of power consumption was further improved.
[0079]
In the above formula (1), since the current I is I = SJ,
τ = KTS^Three / {I² Dexp (−ΔE / kT)} (2)
Can be rewritten as As a result, the lifetime of the wiring due to electromigration is S^Three / I² It turns out that it is proportional to.
In the case of a CMOS logic circuit, the average life of the wiring, the wiring cross-sectional area, and the current flowing through the wiring₀ , S₀ , I₀ Then, their relationship is
τ₀ = AS₀ ^Three / I₀ ²                                       (3)
become that way. Here, a is a proportionality constant.
[0080]
On the other hand, when the average life of the wiring, the cross-sectional area of the wiring, and the current flowing through the wiring are τ, S, and I in the case of the logic circuit that performs adiabatic charging, their relationship is
τ = aS^Three / I²                                           (4)
become that way.
Therefore,
τ / τ₀ = (S / S₀ )^Three(I₀ / I)²                      (5)
And the average life of both is equal, that is, τ₀= Τ
S = S₀ (I / I₀ )^2/3                                   (6)
The following relational expression holds.
[0081]
In the case of adiabatic charging, since the operation is performed slowly, the current value can be reduced to, for example, 1/1000 times that of CMOS logic. Therefore, when the current becomes 1/1000 times, the cross-sectional area becomes 1 Even if it is reduced to / 100 times, the wiring life is exactly the same.
From the above, for example, as shown in FIG. 64A, the wiring width is 0.15 μm and the thickness is 0.02 μm (cross-sectional area: 0.0030 μm).² ) Can be used. Thickness 0.2 μm (cross-sectional area = 0.030 μm² ) Even with normal wiring cross-sectional area (0.30 μm)² 1/10 of the above) and is sufficiently effective.
As described above, the wiring capacity can be reduced to 1/10 to 1/100 times, and as shown in FIG. 64 (c), the power consumption during charging can be reduced to 1/10 to 1/100 times. Is possible.
Further, as a development form, not only the wiring but also the transistor does not require a large current driving capability, so the transistor width (channel width) is reduced from about 10 μm to about 0.1 μm, which is 1/100 times the conventional one. It is possible. Thereby, the capacity of the transistor can also be reduced.
[0082]
[Thirty-fourth embodiment]
Next, it will be described that the wiring cross-sectional area can be reduced from the viewpoint that the electrical signal transmission is adiabatic charging logic and may be slow and slow.
First, when the cross-sectional area A of the wiring is reduced, it is assumed that it is reduced to 1 / k times. At this time, the resistance value R is k times. Also, the capacitance of the wiring is usually sufficiently smaller than the capacitance of the load of the next stage gate. Therefore, the capacitance C may be considered constant. From the above
Approximately
A x CR = constant (constant) (7)
It becomes.
[0083]
Here, the cross-sectional area of the wiring of the CMOS logic circuit is S₀ When the cross-sectional area of the wiring of the adiabatic charging logic circuit is S,
S₀(CR)_CMOS= S (CR)_adiabatic                      (8)
Is established.
During adiabatic charging, the transmission of electrical signals may be slow. Therefore, 10 x (CR)_CMOS≦ (CR)_adiabaticIt can be. Therefore, the following equation is established.
S = S₀(CR)_CMOS/ (CR)_adiabatic≦ 1/10 × S₀     (9)
In addition, since the time T required to increase the power supply of the adiabatic charging circuit needs to be larger than the CR time constant of the adiabatic charging circuit,
(CR)_adiabatic. ≦ T (10)
Is established. Therefore, the following equation is established.
S₀(CR)_CMOS= S (CR)_adiabatic≦ ST (11)
[0084]
Where (CR)_CMOS= Τ
τ / T × S₀ ≦ S (12)
Is obtained. From equations (9) and (12),
τ / T × S₀ ≦ S ≦ 1/10 × S₀                          (13)
Is obtained.
[0085]
That is, the signal wiring width W of the wiring 400 of the CMOS logic circuit shown in FIG.₀ 550 nm (0.55 μm) and signal wiring thickness H₀ When reducing the cross-sectional area of the 550 nm (0.55 μm) wiring, when τ / T is 1/100, the cross-sectional area S is 0.003 μm.²  ≦ S ≦ 0.03μm² Within the range.
From the above, it is possible to use an ultra-thin film wiring as shown in FIG.
[0086]
[Thirty-fifth embodiment]
FIG. 65 is an explanatory view showing a thirty-fifth embodiment of the present invention. The cross-sectional area of the signal wiring of the CMOS logic circuit shown in FIG. 71 can be reduced to 1/10 to 1/100 as described above. However, the power supply line and the ground line of such a logic circuit can be similarly reduced. is there.
That is, the cross-sectional area of the power supply line or ground line 410 of the logic circuit having a width of 30 μm and a thickness of 3 μm shown in FIG.₀ , The adiabatic charging logic shows 1/10 cross-sectional area (1/10 × S) as shown in FIG.₀ Furthermore, as shown in FIG. 65 (c), the cross-sectional area of 1/100 (1/100 × S₀ ).
That is, for the power supply line and the ground line of the logic circuit, the cross-sectional area can be reduced to 1/10 to 1/100 similarly to the signal line by the adiabatic charging logic.
[0087]
In each of the thirty-third to thirty-fifth embodiments, it is of course possible to reduce each cross-sectional area of the signal line, power supply line, and ground line to 1/1000 times by performing adiabatic charging more gently.
In this way, in the adiabatic charging logic, the wiring cross-sectional area can be reduced, and the logic processing can be efficiently realized by a small number of electron transports, thereby making it possible to reduce the energy of logic processing per time compared with the conventional CMOS logic circuit. It can be greatly reduced.
[0088]
【The invention's effect】
As described above, according to the present invention, adiabatic charging and charge recycling can be realized very easily in BDD logic circuits and D latch logic circuits having hundreds or thousands of gates. Compared with a logic circuit and a D latch logic circuit, power consumption can be reduced and the circuit scale can be reduced.
In addition, since the present invention performs adiabatic charging and discharging, the current density flowing through the metal wiring and the transistor is very small, so the electromigration effect in the wiring is small, and the cross-sectional area of the wiring is reduced to that of the CMOS logic circuit. Compared with the cross-sectional area of the wiring, the wiring area can be greatly reduced and the wiring capacity can be greatly reduced.
As described above, according to the present invention, logic processing can be efficiently realized by transporting a small number of electrons, and thus it is possible to greatly reduce the energy of logic processing per time as compared with a conventional CMOS logic circuit. To do.
[Brief description of the drawings]
FIG. 1 is a circuit diagram of a BDD logic circuit according to a first embodiment.
2 is a diagram illustrating an example in which an AC power supply circuit is used as a power reusable power supply of the BDD logic circuit of FIG. 1;
3 is a diagram illustrating an example in which a power supply circuit that generates a step-like voltage is used as a power reusable power supply of the BDD logic circuit of FIG. 1;
FIG. 4 is a diagram showing another voltage waveform or the like as a power reusable power source.
FIG. 5 is a diagram showing an example in which individual power reusable power supplies are used in a power supply circuit of a plurality of BDD logic circuits.
FIG. 6 is a diagram showing an example in which a plurality of BDD logic circuits are divided into two groups and a common power reuse type power supply is used for each group.
FIG. 7 is a circuit diagram of a BDD logic circuit according to a second embodiment.
8 is a diagram illustrating an example in which a power supply circuit that generates a step-like voltage is used as a power reusable power supply of the BDD logic circuit of FIG. 7;
9 is a waveform diagram of the operation of the power supply circuit of FIG.
10 is a circuit diagram for generating timing signals of each of the power supply circuits of FIG. 8. FIG.
11 is a waveform diagram showing a simulation result of the power supply circuit of FIG. 8. FIG.
12 is a waveform diagram showing a simulation result of the BDD logic circuit of FIG.
FIG. 13 is a circuit diagram of a BDD logic circuit according to a third embodiment.
FIG. 14 is a circuit diagram of a BDD logic circuit according to a fourth embodiment.
15 is a more specific circuit diagram of FIG.
16 is a waveform diagram showing a simulation result of the BDD logic circuit of FIG.
FIG. 17 is a circuit diagram of a BDD logic circuit according to a fifth embodiment.
FIG. 18 is a circuit diagram of a BDD logic circuit according to a fifth embodiment.
FIG. 19 is a circuit diagram of a BDD logic circuit according to a sixth embodiment.
20 is a waveform diagram showing a simulation result of the BDD logic circuit of FIG.
FIG. 21 is a circuit diagram of a BDD logic circuit according to a seventh embodiment.
FIG. 22 is a circuit diagram of a BDD logic circuit according to a seventh embodiment.
FIG. 23 is an explanatory diagram of another waveform of the AC power supply.
FIG. 24 is a circuit diagram of a BDD logic circuit according to an eighth embodiment.
FIG. 25 is a circuit diagram of a BDD logic circuit connected with a specific non-reusable power source.
FIG. 26 is an explanatory diagram of an IC card according to a ninth embodiment.
FIG. 27 is a cross-sectional view of a part of the BDD logic circuit according to the tenth embodiment;
FIG. 28 is an explanatory diagram illustrating an example of sharing a BDD graph applied to the BDD logic circuit according to the eleventh embodiment;
FIG. 29 is a circuit diagram of a BDD logic circuit according to an eleventh embodiment.
FIG. 30 is a circuit diagram of a BDD logic circuit according to a twelfth embodiment.
FIG. 31 is a diagram showing a BDD graph and a BDD logic circuit in an example in which the BDD logic circuit of FIG. 30 is applied to the calculation of the sum of a 2-bit adder.
32 is a diagram showing a BDD graph and a BDD logic circuit in an example in which the BDD logic circuit of FIG. 30 is applied to carry operation of a 2-pit adder.
33 is a diagram illustrating an example in which a power supply circuit using an inductor is used as the power reusable power supply of the BDD logic circuit of FIG.
34 is a diagram illustrating an example in which a power supply circuit that generates a step-like voltage is used as a power reusable power supply of the BDD logic circuit of FIG. 30;
FIG. 35 is a diagram illustrating an example in which individual power reusable power supplies are used in a power supply circuit of a plurality of BDD logic circuits.
FIG. 36 is a diagram showing an example in which a plurality of BDD logic circuits are divided into two groups and a common power reuse type power supply is used for each group.
FIG. 37 is a circuit diagram of a BDD logic circuit according to a thirteenth embodiment.
FIG. 38 is a circuit diagram of a BDD logic circuit according to a fourteenth embodiment.
FIG. 39 is a circuit diagram of a BDD logic circuit according to a fifteenth embodiment.
40 is a diagram showing a circuit that embodies the circuit of FIG. 39. FIG.
41 is a circuit diagram of a BDD logic circuit according to a sixteenth embodiment. FIG.
FIG. 42 is a circuit diagram of a BDD logic circuit according to a sixteenth embodiment.
FIG. 43 is a circuit diagram of a BDD logic circuit according to a seventeenth embodiment.
FIG. 44 is a circuit diagram of a BDD logic circuit according to an eighteenth embodiment.
FIG. 45 is a circuit diagram of a BDD logic circuit according to an eighteenth embodiment.
FIG. 46 is an explanatory diagram of the BDD logic circuit according to the nineteenth embodiment.
47 is a diagram showing a power non-reusable power supply circuit of the BDD logic circuit of FIG. 46. FIG.
FIG. 48 is an explanatory diagram of a D latch logic circuit and a power supply voltage waveform according to the twentieth embodiment;
FIG. 49 is a comparative explanatory diagram of charge / discharge energy of a clock portion and a memory circuit portion.
50 is a circuit diagram of a D latch logic circuit according to a twenty-first embodiment. FIG.
51 is a circuit diagram for generating signals A, B, and C in the circuit of FIG. 50. FIG.
52 is a voltage waveform diagram of the circuit of FIG. 50. FIG.
53 is an explanatory diagram of a D latch logic circuit and power supply voltage waveforms according to a twenty-second embodiment; FIG.
FIG. 54 is a circuit diagram of a D latch logic circuit according to a twenty-third embodiment.
55 is a voltage waveform diagram of the circuit of FIG. 54. FIG.
FIG. 56 is a circuit diagram of a D latch logic circuit according to a twenty-fourth embodiment.
FIG. 57 is a circuit diagram of a PMOS latch logic circuit according to a twenty-fifth embodiment.
FIG. 58 is a circuit diagram of a PMOS latch logic circuit according to a twenty-sixth embodiment.
FIG. 59 is a block diagram of a logic circuit showing a twenty-seventh embodiment.
FIG. 60 is a circuit diagram of a logic circuit showing a twenty-seventh embodiment.
FIG. 61 is a circuit diagram of an NMOS latch logic circuit according to 28th and 29th embodiments;
FIG. 62 is a circuit diagram of a PMOS latch logic circuit according to 30th and 31st embodiments;
FIG. 63 is a circuit diagram of the thirty-second embodiment.
FIG. 64 is an explanatory diagram of the thirty-third embodiment.
FIG. 65 is an explanatory diagram of the thirty-fifth embodiment.
FIG. 66 is a block diagram showing a state of power supply control for a BDD logic circuit and a D latch logic circuit.
FIG. 67 is an explanatory diagram of a conventional retractile logic circuit and operation waveforms;
FIG. 68 is an explanatory diagram for embodying a retractile logic circuit;
FIG. 69 is a circuit diagram of a conventional BDD logic circuit.
FIG. 70 is a circuit diagram of a conventional D latch logic circuit.
FIG. 71 is a diagram showing a state of a wiring cross-sectional area of a conventional CMOS logic circuit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1, 2 ... Start point, 3, 4 ... End point, 5 ... Node, 6, 7 ... Branch, 8, 28 ... N channel type MOSFET, 9 ... Wiring 10, 10A, 10B, 101-10n ... Power reuse type power supply DESCRIPTION OF SYMBOLS 10 '... Power non-reuse type power supply, 11, 62 ... Inductor, 12-15, 37, 66 ... Capacitor, 16-23 ... N channel type MOSFET, 24 ... P channel type MOSFET, 25-27, 35, 55-57, 95, 96, 104, 105, 131-133... Inverter, 30A, 30B, 63, 110, 120, 301-30n, 140B, 140B'140D, 140D '... BDD logic circuit, 36 ... resistor, 41 ... 43 ... T flip-flop circuit, 44-54 ... NAND circuit, 60 ... IC card, 61 ... Reader / writer, 64 ... Power supply rectifier circuit, 65 ... CMOS logic Path 71 71 substrate 72 insulating film 73 metal or polysilicon (wiring or gate) 74 gate insulating film 75 n-type region (source or drain) 76 p region (channel) 77 ... p-type region (source or drain), 78 ... n-type region (channel), 79 ... global through hole, 81,82 ... transmission gate, 90, 90A, 90B ... D latch logic circuit, 91-94 ... transmission gate, 130 ... inverter circuit, 140 ... 2-bit adder, 140A, 140C ... PMOS latch logic circuit, 140A ', 140C' ... NMOS latch logic circuit, 400,410 ... CMOS logic circuit wiring, 450 ... timing controller.

Claims (5)

A logic circuit composed of a plurality of logic elements;
After an input signal is given to the gate of each logic element, power is supplied to the logic circuit to perform logic processing, and before the logic process is finished and a new input signal is given to the gate of the logic element. A power supply unit for stopping supply of the power,
The upper limit value of the wiring current obtained from the lifetime of electromigration from the wiring cross-sectional area of the logic circuit using the wiring having the same cross-sectional area S ₀ as that of the CMOS logic circuit as the signal wiring of the logic circuit is defined as I _O. When the current value flowing during the adiabatic charging logic operation is I,
The wiring cross-sectional area S is (I / I _O ) ^2/3 × S ₀ ≦ S ≦ 1/10 × S ₀
An adiabatic charging logic circuit, characterized in that A logic circuit composed of a plurality of logic elements;
After an input signal is given to the gate of each logic element, power is supplied to the logic circuit to perform logic processing, and before the logic process is finished and a new input signal is given to the gate of the logic element. A power supply unit for stopping supply of the power,
The CR time constant of the signal wiring of the logic circuit using the wiring having the same cross-sectional area S ₀ as the CMOS logic circuit as the signal wiring of the logic circuit is τ, and power is supplied to the logic circuit by adiabatic charging logic. When the time until the supply voltage reaches the peak value is T,
The cross-sectional area S of the signal wiring is
τ / T × S ₀ ≦ S ≦ 1/10 × S ₀
An adiabatic charging logic circuit, characterized in that In claim 1 or claim 2,
When the cross-sectional area S ₀ of the signal lines and 0.3 [mu] m ^2, the cross-sectional area S is adiabatic charging logic circuit, characterized in that to 0.003 .mu.m ² without a 0.03 .mu.m ^2. In claim 1 or claim 2,
An adiabatic charging logic circuit, wherein a cross-sectional area of a power supply line and a cross-sectional area of a ground line of the logic circuit are reduced. In claim 4,
Adiabatic charging logic circuit, wherein the cross-sectional area of the power line and the ground line of the logic circuit are reduced to 1/10 to 1/100, respectively.

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