JP3486882B2 - Power supply device, discharge lamp lighting device and lighting device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply device whose output can be adjusted, a discharge lamp lighting device, and a lighting device.

[0002]

2. Description of the Related Art Conventionally, a discharge lamp lighting device for dimming and lighting a discharge lamp is disclosed in Japanese Patent Publication No. 3-78759. This device performs dimming by asymmetrically controlling the ON widths of two switching means at a constant frequency.

FIG. 20 is a circuit diagram showing a conventional discharge lamp lighting device for performing dimming by asymmetrically controlling the ON widths of such two switching means.

In FIG. 20, reference numeral 81 is a DC power supply that outputs a DC power supply voltage by rectifying and smoothing a commercial AC power supply voltage.

The positive output terminal of the DC power supply 81 is connected to the positive input terminal of the inverter section 90, and the negative output terminal of the DC power supply 81 is connected to the negative input terminal of the inverter section 90. It

The inverter section 90 will be described in more detail. An input terminal on the positive side of the inverter section 90 is an NPN.
Via a series connection of the collector-emitter path及collector-emitter path and the NPN transistor 92 of the transistor 91 is connected to an input terminal of the negative electrode side of the inverter unit 90. The emitters of the NPN transistors 91 and 92 are connected to the collectors of the NPN transistors 91 and 92 via the anode / cathode paths of the feedback diodes D91 and D92, respectively.

The NPN transistors 91 and 92 are alternately turned on and off by drive signals a8 and b8 from the drive circuit 93.

The connection point of the NPN transistors 91 and 92 is connected to the collector of the NPN transistor 91 through a series connection of an inductor 94 such as a primary winding L91 of an inverter transformer and a capacitor C91 for removing direct current.

One input terminal of the discharge lamp 95 is connected to one end of the secondary winding L92 of the inductor 94. The other input terminal of the discharge lamp 95 is connected to the other end of the secondary winding L92 of the inductor 94. A capacitor C93 is connected between both terminals of the discharge lamp 95. With such a connection, the discharge lamp 95 and the capacitor C93 are connected to the output circuit 96.
Are configured.

The details of the operation of such a conventional discharge lamp lighting device will be described with reference to FIGS. 21 to 23.

FIG. 21 is a timing chart showing the operation of the discharge lamp lighting device of FIG. 20 at full light, and FIG.
21B shows the voltage VDC9 applied between the input terminals of the inverter 90, FIG. 21B shows the current I91 flowing through the NPN transistor 91, and FIG. 21C shows the NPN transistor 92.
21D shows a current I92 flowing through the DC power supply 81.
21E shows the voltage V9 applied to the connection point of the NPN transistors 91 and 92 when the output terminal on the negative electrode side is 0V, and FIG.

The circuit operation in this case starts from timing t90.
One cycle is t92. The width of the period is the same between the timing t90 to t91 and the timing t91 to t92.

During the period from timing t90 to timing t91, the NPN
The transistor 91 is turned on, and the NPN transistor 92
Is turned off, the capacitor C91 and the NPN transistor 9 are turned on.
A closed circuit is formed by the primary winding L91 and the primary winding L91.

In this case, the voltage VDC9 applied between the input terminals of the inverter 90 shown in FIG.
The current I91 flowing through the NPN transistor 91 shown in FIG. 21 (b) while maintaining Rec9 is the current flowing through the feedback diode D91 {shown by the broken line in FIG. 21 (b). 21 rises to the positive side from the time when it becomes zero, the current I92 flowing through the NPN transistor 92 shown in FIG.
The voltage V9 shown in (d) shows a constant positive value VRec9, and the voltage VL9 shown in FIG. 21 (e) shows a constant positive + Va9.

During the period from timing t91 to timing t92, the NPN
The transistor 91 is turned off, and the NPN transistor 92
Is turned on, and a closed circuit is formed by the DC power supply 81, the capacitor C91, the primary winding L91, and the NPN transistor 92.

In this case, the voltage VDC9 shown in FIG. 21 (a) maintains a constant value VRec9, the current I91 flowing through the NPN transistor 91 shown in FIG. 21 (b) maintains 0 A, and the voltage VDC9 shown in FIG. ), The current I92 flowing through the NPN transistor 92 is the current flowing through the feedback diode D92 (FIG. 2).
It is indicated by a broken line in 1 (c). } Rises to the positive side from the time when it becomes zero, the voltage V9 shown in FIG. 21 (d) shows 0, and the voltage VL9 shown in FIG. 21 (e) shows a constant negative value -Va9.

FIG. 22 is a timing chart showing the operation of the discharge lamp lighting device of FIG. 20 during dimming, and FIG.
22B shows the voltage VDC9 applied between the input terminals of the inverter 90, FIG. 22B shows the current I91 flowing through the NPN transistor 91, and FIG. 22C shows the NPN transistor 92.
22D shows a current I92 flowing through the DC power supply 81.
22E shows the voltage V9 applied to the connection point of the NPN transistors 91 and 92 when the output terminal on the negative electrode side is 0V, and FIG. 22E shows the voltage VL9 applied to the primary winding L91.

The circuit operation in this case starts from timing t93.
t95 is one cycle. From timing t93 to t95,
The width of the period is the same as the timing t90 to t92 in FIG. That is, one cycle is the same for all light and dimming.

At the timings t93 to t94, the width of the period is longer than the timings t94 to t95.

During the period from timing t93 to t94, the NPN
The transistor 91 is turned on, and the NPN transistor 92
Is turned off, the capacitor C91 and the NPN transistor 9 are turned on.
A closed circuit is formed by the primary winding L91 and the primary winding L91.

In this case, the voltage V shown in FIG.
DC9 maintains a constant value VRec9, and N shown in FIG.
A current I91 flowing through the PN transistor 91 is a current flowing through the feedback diode D91 {shown by a broken line in FIG. 22 (b). 22 rises to the positive side from the time when it becomes zero, reaches the maximum value, and then decreases, and the current I92 flowing through the NPN transistor 92 shown in FIG. 22 (c) maintains 0 A, and the voltage shown in FIG. V9 shows a positive constant value VRec9, and FIG.
The voltage VL9 shown in (e) shows a constant positive + Vb9.

During the period from timing t94 to t95, the NPN
The transistor 91 is turned off, and the NPN transistor 92
Is turned on, and a closed circuit is formed by the DC power supply 81, the capacitor C91, the primary winding L91, and the NPN transistor 92.

In this case, the voltage V shown in FIG.
DC9 maintains a constant value VRec9, and N shown in FIG.
The current I91 flowing in the PN transistor 91 maintains 0 A, and the current I92 flowing in the NPN transistor 92 shown in FIG. 22C is the current flowing in the feedback diode D92 {FIG.
It is indicated by a broken line in 2 (c). } Rises to the positive side from the time when it becomes zero, and the voltage V9 shown in FIG.
The voltage VL9 shown in FIG. 22 (e) shows a constant negative −Vc9.

The voltage VL9 applied to the primary winding L91 shown in FIGS. 21 (e) and 22 (e) is the capacitor C
By means of 91, the voltage V9 applied to the connection point of the NPN transistors 91 and 92 shown in FIGS. 21 (d) and 22 (d) is a voltage obtained by removing the DC component.

Therefore, the NPN transistors 91 and 92
When the on / off period of is unbalanced, as shown in FIG.
The voltage VL9 shown in (e) becomes lower than the absolute value of the voltage applied to the primary winding L91 × time, the energy applied to the primary winding L91 decreases, and the output supplied from the inverter 90 to the output circuit 96 decreases. To do.

FIG. 23 is a graph showing the relationship between the on-duty ratio of the NPN transistor 91 and the output of the inverter 90. The abscissa represents the on-duty ratio of the NPN transistor 91, and the ordinate represents the inverter 90 in the output circuit 96. Taking output to supply.

In FIG. 23, the NPN transistor 91
The output of the inverter 90 becomes maximum when the on-duty ratio is 50%, and the output of the inverter 90 decreases as the on-duty ratio of the NPN transistor 91 deviates from 50%.

[0028]

According to such a conventional discharge lamp lighting device, the dimming is performed by shifting the on-duty ratio of the switching means (NPN transistors 91, 92) which are alternately turned on and off from 50%. However, to widen the dimming range, the on-duty ratio must be changed significantly. Further, the capacity of the DC removing capacitor C91 has to be increased.

[0029] The present invention has an object to provide a range of output adjustment in the case of using the discharge lamp output circuit power supply that can and expand a large child, the discharge lamp lighting device and a lighting device.

[0030]

According to a first aspect of the present invention, there is provided a power supply device including a direct current power source for outputting a direct current voltage; first and second switching devices provided in series between output terminals of the direct current power source. Means; a relatively large-capacity first capacitor provided in parallel with the first switching means; an inductor interposed between the first switching means and the first capacitor; A second capacitor having a capacitance smaller than that of the first capacitor and forming a resonance circuit with the second switching means and the inductor during an ON period of the second switching means; output circuit and obtaining a high-frequency output based on resonance; together alternately turned on and off said first and second switching means decreases the output of said output circuit The case and the drive circuit to reduce the on-duty ratio of the second switching means; characterized by comprising a.

A power supply device according to a second aspect of the present invention is a rectifier circuit that rectifies an output voltage of an AC power source to output an unsmoothed DC voltage; and a rectifier circuit that is provided in series between output terminals of the rectifier circuit. First and second switching means; a relatively large-capacity first capacitor provided in parallel with the first switching means; and interposed between the first switching means and the first capacitor An inductor that has a capacitance smaller than that of the first capacitor,
A second capacitor that forms a resonance circuit with the second switching means and the inductor during the ON period of the second switching means; and an output circuit that obtains a high frequency output based on the resonance of the inductor and the second capacitor. ; with alternately turned on and off said first and second switching means, controlled on the basis of the on-duty ratio of the switching means to the output voltage of the rectifier circuit, to vary the output of the output <br/> force circuit it characterized by comprising a; and a drive circuit, characterized in that changing the period of the on-off of the first and second switching means when.

According to a third aspect of the present invention, there is provided the power supply device according to any one of the first and second aspects, wherein the second capacitor is provided in parallel with the second switching means.

According to a fourth aspect of the present invention, there is provided the power supply device according to any one of the first and second aspects, wherein the second capacitor is provided in parallel with the series connection of the first and second switching means. The power supply described.

A power supply device according to a fifth aspect of the present invention is characterized in that a discharge lamp is provided in the output circuit of the power supply device according to any one of the first to fourth aspects.

According to a sixth aspect of the present invention, there is provided a power supply device comprising: the discharge lamp lighting device according to the fifth aspect; and a lighting fixture main body that houses the discharge lamp lighting device.

In the above invention, the first and second switching means allow NPN transistors, MOSFETs and the like.

[0037]

According to the invention of claim 1, the second capacitor forms a resonance circuit with the second switching means and the inductor during the ON period of the second switching means, and the drive circuit outputs the output of the output circuit. When decreasing, the on-duty ratio of the second switching means is decreased to reduce the charge amount of the first capacitor, and the resonance circuit is formed by the second capacitor, the second switching means and the inductor. Therefore, the range of output adjustment can be expanded when a discharge lamp is used in the output circuit.

According to the second aspect of the present invention, the second capacitor forms a resonance circuit with the second switching means and the inductor during the on period of the second switching means, and the drive circuit turns on the switching means. When the duty ratio is controlled based on the output voltage of the rectifier circuit and the output of the output circuit is changed, the on / off cycle of the first and second switching means is changed, so that a discharge lamp is used for the output circuit. In this case, the range of output adjustment can be expanded, and the constriction of the output current generated by the unsmoothed DC voltage of the rectifier circuit can be suppressed.

According to the invention of claim 3, the power supply device according to any one of claims 1 and 2 can be realized by disposing the second capacitor in parallel with the second switching means.

According to the invention of claim 4, by providing the second capacitor in parallel with the series connection of the first and second switching means, the power supply according to any one of claims 1 and 2. The device can be realized.

According to the invention of claim 5, claims 1 to 4
The power supply device according to any one of 1 to 3 can be applied to the discharge lamp lighting device.

According to the invention of claim 6, the discharge lamp lighting device according to claim 5 can be applied to a lighting device.

[0043]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a case where an embodiment of a power supply circuit according to the present invention is applied to a discharge lamp lighting device.

In FIG. 1, the output terminal on the positive side of the DC power supply 11 is connected to the input terminal on the positive side of the inverter section 20, and the output terminal on the negative side of the DC power supply 11 is the input on the negative side of the inverter section 20. Connected to the terminal.

The inverter 20 includes a first switching means 21 such as an NPN transistor, a second switching means 22 such as an NPN transistor, and a drive circuit 23.
, A diode D11, D21, D22, a first capacitor C1 such as an electrolytic capacitor, a second capacitor C2, and an inductor 24 such as an inverter transformer.

Explaining the inverter section 20 in more detail, the input terminal on the positive side of the inverter section 20 includes the anode / cathode path of the diode D11 and the switching means 2.
The collector-emitter path of 1 and the collector-emitter path of the switching means 22 are connected in series to the negative input terminal of the inverter unit 20. Diode D
The cathode of 11 is connected to the negative input terminal of the inverter 20 through the parallel connection of the capacitors C1 and C2. The emitters of the switching means 21, 22 are connected to the collectors of the switching means 21, 22 via the anode / cathode paths of the diodes D21, D22, respectively. In this case, the diodes D21 and D22
Has a function of guiding the currents introduced to the emitter side of the switching means 21 and 22 to the collector side of the switching means 21 and 22 when the voltage on the collector side of the switching means 21 and 22 becomes lower than that on the emitter side. Have.

The connection point of the switching means 21 and 22 is
The capacitor C is connected through the primary winding L21 of the inductor 24.
1 and the capacitor C2. With this connection, the capacitors C1 and C2 are
They are provided in parallel with the switching means 21 and 22, respectively.

With the capacitors C1 and C2,
The capacitance of the capacitor C1 provided in parallel with the switching means 21 is larger.

The drive circuit 23 creates control signals a1 and b1 for alternately turning on / off the switching means 21 and 22 in a state where the on-duty ratio is set based on the dimming data from the dimming control means (not shown). To the bases of the switching means 21 and 22, respectively. In this case, the drive circuit 23 increases the on-duty ratio of the switching means 21 when decreasing the output of the inverter 20, reduces the on-duty ratio of the switching means 22 and increases the output of the inverter 20, The on-duty ratio of the switching means 21 is reduced and the on-duty ratio of the switching means 22 is increased.

On the other hand, one input terminal of the discharge lamp 25 is connected to one end of the secondary winding L22 of the inductor 24. The other input terminal of the discharge lamp 25 is connected to the other end of the secondary winding L22 of the inductor 24. A capacitor C3 is connected between both terminals of the discharge lamp 25. With such a connection, the discharge lamp 25 and the capacitor are connected to the output circuit 26.
Are configured.

Details of the operation of this embodiment will be described with reference to FIGS.

FIG. 2 is a timing chart showing the operation when the output of the embodiment of FIG. 1 is set to a relatively large value.
2A shows a voltage VDC applied to the series connection of the switching means 21 and 22, FIG. 2B shows a current I21 flowing through the switching means 21, and FIG. 2C shows a current I22 flowing through the switching means 22. 2 (d) shows the voltage VC1 applied to the capacitor C1, and FIG. 2 (e) shows the voltage VL applied to the winding L21.

FIG. 3 is a timing chart showing the operation when the output of the embodiment of FIG. 1 is set to be relatively small,
3A shows the voltage VDC applied to the series connection of the switching means 21 and 22, FIG. 3B shows the current I21 flowing through the switching means 21, and FIG. 3C shows the current I22 flowing through the switching means 22. 3 (d) shows the voltage VC1 applied to the capacitor C1 and FIG. 3 (e) shows the voltage VL applied to the winding L21.

4 and 5 are explanatory views showing the operation of the embodiment of FIG. 1, and FIG. 4 (a) is a timing t in FIG.
2 shows the period from 0 to t1, and FIG. 4B shows t1 in FIG.
.About.t2, FIG. 4 (c) shows the period from t2 in FIG.
FIG. 5A shows the period of t3, and t3 to t in FIG.
4 shows the period of time 4 and FIG. 5B shows t4 to t5 in FIG.
Shows the period of. In FIGS. 4 and 5, a combination of the switching means 21 and the diode D21 in FIG. 1 is shown by a switching means (switch symbol) 21, and a combination of the switching means 22 and the diode D22 in FIG. Is indicated by switching means (switch symbol) 22.

First, the operation when the output is set relatively large will be described. In the circuit operation in this case, t0 to t5 is one cycle.

In the period from timing t0 to t1, as shown in FIG.
As shown in (a), since a closed circuit is formed by the capacitor C1, the switching means 21, and the primary winding L21, the electric charge stored in the capacitor C1 is released, and the primary winding L21 of the inductor 24 is switched to the switching means 21. The current I1 from

In this case, the voltage VDC of the switching means 21, 22 shown in FIG. 2 (a) maintains a constant value VRec, and the current I21 flowing in the switching means 21 shown in FIG. 2 (b) rises, Switching means 2 shown in FIG.
The current I22 flowing in 2 maintains 0 A, the voltage VC1 applied to the capacitor C1 shown in FIG. 2 (d) gradually decreases, and the voltage VL applied to the winding L21 shown in FIG. 2 (e) is a constant negative value. To maintain.

In the period from timing t1 to t2, as shown in FIG.
As shown in (b), the switching means 21 is turned off,
The switching means 22 is turned on, the inductor 24 and the capacitor C2 resonate in series, and the resonance current I2 flows from the inductor 24 toward the capacitor C2.

In this case, the voltage VDC shown in FIG.
2A, the current I21 flowing through the switching means 21 shown in FIG. 2B becomes 0A, and the current I22 flowing through the switching means 22 shown in FIG. 2C rapidly decreases from 0A to the − side and then increases. Then, the voltage returns to 0A, and the voltage VC1 applied to the capacitor C1 shown in FIG. Figure 2
The voltage VL applied to the winding L21 shown in (e) increases from a constant negative value.

In the period from the timing t2 to t3, as shown in FIG.
As shown in (c), the switching means 21 is turned off,
With the switching means 22 turned on, the inductor 2
4 and the resonance current I3 due to the series resonance of the capacitor C2 flows in the opposite direction to the case of the timings t1 to t2.

In this case, the rectifying circuit 12 shown in FIG.
Voltage VDC decreases, the current I21 flowing in the switching means 21 shown in FIG. 2 (b) maintains 0A, and the current I22 flowing in the switching means 22 shown in FIG. 2 (c) increases from 0A to the + side, The voltage VC1 applied to the capacitor C1 shown in FIG. 2D is almost maintained. Winding L2 shown in FIG. 2 (e)
The voltage VL applied to 1 decreases.

In the period from timing t3 to t4, as shown in FIG.
As shown in (a), the resonance voltage decreases and the capacitor C
1 and the voltage across the capacitor C2 also try to drop, the rectifier circuit 12 to the capacitor C1, the inductor 24
And the current I4 flows through the switching means 22.

In this case, the voltage VDC of the rectifier circuit 12 shown in FIG. 2 (a) becomes a constant value VRec, and FIG.
The current I21 flowing in the switching means 21 shown in FIG. 2 maintains 0 A, the current I22 flowing in the switching means 22 shown in FIG. 2C gradually decreases, and the voltage VC1 applied to the capacitor C1 shown in FIG. Figure 2
The voltage VL applied to the winding L21 shown in (e) gradually decreases.

In the period of timings t4 to t5, as shown in FIG.
As shown in (b), the switching means 21 is turned on,
The switching means 22 is turned off, and the current I5 flows from the first switching means 21 to the capacitor C1 due to the energy stored in the inductor 24.

In this case, the voltage VDC of the rectifier circuit 12 shown in FIG. 2A maintains a constant value VRec, and FIG.
2A, the current I21 flowing through the switching means 21 sharply decreases and then increases, and the current I22 flowing through the switching means 22 shown in FIG. 2C sharply decreases to 0 A,
The voltage VC1 applied to the capacitor C1 shown in FIG. 2 (d) gradually increases, and the voltage VL applied to the winding L21 shown in FIG. 2 (e) sharply decreases to the negative side and becomes a constant negative value.

First, the operation at full light will be described. In the circuit operation in this case, t0 to t5 is one cycle.

Here, in the operation for setting the output shown in FIG. 2 to be relatively large, the period {timing t1 to t4} during which the drive circuit 23 turns on the switching means 22 is changed to the period {timing t1 during which the switching means 21 is turned on. t4 ~
It is set larger than t6}. In the operation for setting the output shown in FIG. 3 to be relatively small, the period during which the drive circuit 23 turns on the switching means 22 (timing t1 to
t4} is set shorter than the period {timing t4 to t6} during which the switching means 21 is turned on.

In FIG. 3, periods t0 to t1 and t1 to t.
2 ... The direction of current flow during t4 to t5 is as shown in FIGS.

Period during which the drive circuit 23 turns on the switching means 22 {timing t1 to t4 (t5) to t1}
Is set to be smaller than the period {timing t4 to t6} during which the switching means 21 is turned on.
The maximum value of the voltage VDC during the period in which the switching means 22 shown in (a) is turned on is lower than that in FIG. 2 (a), and the current I21 flowing through the switching means 21 shown in FIG.
The ratio of the period in which is 0A is decreased compared to FIG. 2 (b),
A current I flowing through the switching means 22 shown in FIG.
The ratio of the period in which 22 is 0 A increases as compared with that in FIG. 2C, and the voltage VC1 applied to the capacitor C1 shown in FIG.
Is smaller than that in FIG. 2 (d), and the winding L shown in FIG. 3 (e) is
The absolute value of the voltage of the voltage VL applied to 21 × time is reduced, and the energy applied to the primary winding L21 is reduced,
The output supplied from the inverter 20 to the output circuit 26 decreases.

FIG. 6 is a graph showing the relationship between the on-duty ratio of the switching means 21 and the output of the inverter 20. The horizontal axis represents the on-duty ratio of the switching means 21 and the vertical axis represents the output of the inverter 20. There is.

In FIG. 6, the lower the on-duty ratio of the switching means 21 (in this embodiment, the range of the on-duty ratio is from about 8% to about 92%), the larger the output of the inverter 20.

[0073] According to such an embodiment, the first switching means 21 is turned off, the second switching hands stage
22 is turned on, the second capacitor C2
Since the resonance voltage is generated by the inductor 24 and the inductor 24, the output can be adjusted to a larger value by setting the ratio of this period to be large in the drive circuit 23. Therefore, the output adjustment when the discharge lamp 25 is used in the output circuit 26 The range of can be expanded, and in the case of the discharge lamp 25, 1
Dimming is possible up to 0% or less. In addition to this, due to the action of such a resonance voltage, the switching means 21, 2
The switching loss of 2 can be improved.

FIG. 7 is an explanatory diagram showing a first control example of the switching means 21, 22 by the drive circuit 23.
(A) is a control signal a when the output is set relatively large
7 (b) shows the control signal b1 when the output is set relatively high, FIG. 7 (c) shows the control signal a1 when the output is set relatively low, and FIG. ) Indicates the control signal b1 when the output is set to be relatively small.

The control signals a1 and b1 of the drive circuit 23 have constant frequencies regardless of the output of the inverter 20, as shown in FIGS. 7 (a) to 7 (d).

When the output of the inverter 20 is set relatively high, the control signal a1 is set to have a high level for a short period and the switching means 21 has a small on-duty ratio, as shown in FIG. 7A. , Fig. 7
The control signal b1 shown in (b) is a state in which the high level (H) and the low level (L) in the control signal a1 shown in FIG. 7 (a) are inverted, and the on-duty ratio of the switching means 22 is large. Is set.

When the output of the inverter 20 is set to be relatively small, the control signal a1 is set to a high level for a long time and the on-duty ratio of the switching means 21 is set to be large, as shown in FIG. 7C. , Fig. 7
The control signal b1 shown in (d) is a state in which the high level (H) and the low level (L) in the control signal a1 shown in FIG. 7A are inverted, and the on-duty ratio of the switching means 22 is small. Is set.

FIG. 8 is an explanatory diagram showing a second control example of the switching means 21 and 22 by the drive circuit 23, and FIG. 8A shows a control signal a1 when the output is set relatively large. 8 (b) shows the control signal b1 when the output is set relatively large, and FIG. 8 (c) shows the control signal a1 when the output is set relatively small, and FIG.
Indicates the control signal b1 when the output is set relatively small.

As for the control signals a1 and b1 of the drive circuit 23, as shown in FIGS. 8A to 8D, the control signal a1 is low level (L), that is, the switching means 21 regardless of the output of the inverter 20. The off period is constant.

When the output of the inverter 20 is set relatively high, the control signal a1 is set to a high level for a short period and the switching means 21 has a small on-duty ratio, as shown in FIG. 8 (a). , Fig. 8
The control signal b1 shown in (b) is a state in which the high level (H) and the low level (L) in the control signal a1 shown in FIG. 8A are inverted, and the on-duty ratio of the switching means 21 is large. Is set.

When the output of the inverter 20 is set to a relatively small value, the control signal a1 is set to a high level for a long period and the on-duty ratio of the switching means 21 is set to a large value, as shown in FIG. 8C. , Fig. 8
The control signal b1 shown in (d) is a state in which the high level (H) and the low level (L) in the control signal a1 shown in FIG. 8A are inverted, and the on-duty ratio of the switching means 22 is small. Is set.

The example of FIG. 1 can be realized by such a control example.

FIG. 9 is a circuit diagram showing a case where an embodiment of the power supply circuit according to the present invention is applied to a discharge lamp lighting device, and the same components as those of the embodiment of FIG. Is omitted.

The difference in the embodiment of FIG. 9 is that the inverter 3
0, the capacitor C5 for resonance is connected to the positive electrode side of the rectifier circuit 12, and the capacitor C6 having a relatively large capacity is connected to the negative electrode side of the rectifier circuit 12.

When setting the output of the inverter 30 to be relatively large, the drive circuit 33 switches the switching means 21.
Of the switching means 22 is made small and the on-duty ratio of the switching means 22 is made small. In addition, the drive circuit 33
, When a relatively small rather sets the output of the inverter 30, to reduce the Ondeyutei ratio of the switching means 21, to increase the on-duty ratio of the switching means 22.

According to such an embodiment, the same effect as that of the embodiment of FIG. 1 can be obtained.

FIG. 10 is a circuit diagram showing a case where another embodiment of the power supply circuit according to the present invention is applied to a discharge lamp lighting device, and the same components as those of the embodiment of FIG. The description is omitted.

10 differs from the embodiment of FIG. 10 in that in the inverter 40, the resonance capacitor C42 is connected in parallel to the series connection of the switching means 21 and 22.

According to this embodiment, since the inductor 24 and the capacitor C42 resonate in series while the switching means 21 is turned off and the switching means 22 is turned on, the same effect as that of the embodiment of FIG. 1 is obtained. can get.

FIG. 11 is a circuit diagram showing a case where still another embodiment of the power supply circuit according to the present invention is applied to a discharge lamp lighting device.

In FIG. 11, one of the output terminals of an AC power supply 51, for example, a commercial AC power supply, is a choke coil L51.
It is connected to one input terminal of that by the rectifying circuit 52 such as a diode bridge <br/> full wave rectifier via the AC power source 51
The other output terminal of is connected to the other input terminal of the rectifier circuit 52 via the choke coil L52. The choke coil L51 and the choke coil L52 are magnetically coupled.

A capacitor C51 is connected between the input terminals of the rectifier circuit 52.

The positive output terminal of the rectifier circuit 52 is connected to the positive input terminal of the inverter 60. The negative output terminal of the rectifier circuit 52 is connected to the negative input terminal of the inverter 60.

The inverter 60 includes a first switching means 61 such as a MOSFET, a second switching means 62 such as a MOSFET, a diode D51, an output control circuit 63, a first capacitor C11 such as an electrolytic capacitor, and a second capacitor. C12 and inductor 64
For example, it is composed of an inverter transformer.

The inverter 60 will be described in detail below.

The positive input terminal of the inverter 60 is connected to the positive input terminal of the output control circuit 63. The negative input terminal of the inverter 60 is connected to the negative input terminal of the output control circuit 63.

The input terminal on the positive electrode side of the inverter 60 is connected to the inverter 60 via the series connection of the anode / cathode path of the diode D51, the drain / source path of the switching means 61, and the drain / source path of the switching means 62. Of the inverter 60, and is connected to the input terminal on the negative side of the inverter 60 through the series connection of the capacitor C11 and the capacitor C12.

The connection point of the switching means 61, 62 is
A capacitor C is provided through the primary winding L61 of the inductor 64.
11 and the capacitor C12. By such connection, the capacitors C11 and C
12 are provided in parallel with the switching means 61 and 62, respectively.

The output control circuit 63 outputs the oscillation signal a.
5, b5 to the first and second switching means 61, 62
To the first and second switching means 61, 62
Are alternately turned on and off, the on-duty ratios of the first and second switching means 61, 62 are controlled based on the output voltage of the rectifier circuit 52, and the first duty control is performed based on a dimming operation such as a key input operation. Also, the on / off cycle of the second switching means 61, 62 is changed.

One input terminal of the discharge lamp 65 is connected to one end of the secondary winding L62 of the inductor 64. The other input terminal of the discharge lamp 65 is connected to the other end of the secondary winding L62 of the inductor 64. A capacitor C13 is connected between both terminals of the discharge lamp 65. With such a connection, the discharge lamp 65 and the capacitor C13 are connected to the output circuit 66.
Are configured.

Of the capacitors C11 and C12, the capacitor C11 provided in parallel with the switching means 61 has a larger capacity.

Next, the output control circuit 63 will be described in detail.

The output control circuit 63 comprises an on-duty variable circuit 71, a dimming signal generation circuit 72, a frequency variable circuit 73, and a drive circuit 74.

The on-duty variable circuit 71 detects the output voltage from the rectifier circuit 52 and performs variable control of the duty ratio of the oscillation signals a5 and b5 output from the drive circuit 74 based on the detection result. There is. More specifically, when the voltage VDC5 has a large peak value, the duty ratio with which the oscillation signal b5 is at a high level is reduced, and the duty ratio with which the oscillation signal a5 is at a high level is increased.
The on-duty ratio of the second switching means 62 is reduced and the on-duty ratio of the first switching means 61 is increased. When the voltage VDC5 has a small peak value, the duty ratio with which the oscillation signal b5 is at a high level is increased, the duty ratio with which the oscillation signal a5 is at a high level is decreased, and the on-duty ratio of the second switching means 62 is increased. Then, the on-duty ratio of the first switching means 61 is reduced.

The dimming signal generating circuit 72 creates a dimming signal c5 based on a dimming operation such as a key input operation and supplies it to the frequency varying circuit 73. The frequency variable circuit 73 performs variable control of the frequencies of the oscillation signals a5 and b5 output from the drive circuit 74 based on the supplied dimming signal c5.

Specifically, in this case, the frequency when the dimming is the deepest (the frequency that can be controlled by the drive circuit 74) from the frequency of the oscillation signals a5, b5 output by the drive circuit 74 at the time of full light is: Inductor 64, output circuit 6
6, the capacitor C11 and the capacitor C12 are selected to be higher than the natural vibration frequency, and it is shown that the output of the dimming signal c5 from the dimming signal generating circuit 72 to the output circuit 66 is increased. In this case, the frequency variable circuit 73 outputs the oscillation signals a5 and b output by the drive circuit 74.
5 is controlled so as to lower the frequency, and the output of the dimming signal c5 from the dimming signal generating circuit 72 to the output circuit 66 is reduced, the frequency variable circuit 73 uses the driving circuit. The frequency of the oscillation signals a5 and b5 output by 74 is controlled to increase.

The operation of such an embodiment will be described with reference to FIGS.
This will be described with reference to FIG.

FIG. 12 shows the output voltage of the rectifier circuit 52 and the switching means 61, 62 by the output control circuit 63 of FIG.
2A is a timing chart showing the relationship of the ON time of the rectifier circuit 52. FIG. 2A shows the output voltage of the rectifier circuit 52, and FIG.
Indicates the ON time of the switching means 61, 62.

In FIG. 12, the output control circuit 63 reduces the ON period of the second switching means 62 when the peak value of the output voltage of the rectifier circuit 52 (the output voltage of the AC power supply 51) is large, and The ON period of the switching means 61 is increased. Further, the output control circuit 63 increases the ON period of the switching means 62 when the peak value of the output voltage of the rectifier circuit 52 is small, and the switching means 6
The ON period of 1 is reduced. Therefore, during the ON period of the first switching means 61, the second switching 62
Changes to the opposite relationship.

Next, the overall operation of this embodiment will be described.

First, the voltage of the AC power supply 51 is subjected to full-wave rectification by the rectifier circuit 52 by removing noise with the filter circuit including the choke coils L51 and L52 and the capacitor C51.
On the other hand, the output control circuit 63 includes switching means 61, 6
2 is alternately switched at a frequency higher than that of the AC power supply 51 to induce a high frequency AC voltage in the secondary winding L61 of the inductor 64, and the discharge lamp 65 is lit at a high frequency. Further, a resonance voltage is generated by the capacitor C12 and the inductor 64, and the action of this resonance voltage causes the capacitor C1 to
The voltage of 1 is made to be lower than the unsmoothed DC voltage rectified by the rectifying circuit 52 during one cycle of switching of the switching means 61, 62. As a result, the power factor correction current is caused to flow even during a period when the peak value of the voltage rectified by the rectifier circuit 52 is low, so that the distortion is reduced.

FIG. 13 is a timing chart showing the operation of the embodiment of FIG. 11 under full light, FIG. 13 (a) shows the voltage VDC5 applied to the series connection of the switching means 61, 62, and FIG. 13 (b). Shows the current I61 flowing through the switching means 61, FIG. 13 (c) shows the current I62 flowing through the switching means 62, and FIG. 13 (d) shows the capacitor C1.
13 shows the voltage VC5 applied to the winding 1, and FIG.
Shows the voltage VL5 applied to the.

FIG. 14 is a timing chart showing the operation during dimming of the embodiment of FIG. 11, FIG. 14 (a) shows the voltage VDC5 applied to the series connection of the switching means 61, 62, and FIG. 14 (b). Shows the current I61 flowing through the switching means 61, FIG. 14 (c) shows the current I62 flowing through the switching means 62, and FIG. 14 (d) shows the capacitor C1.
14 shows the voltage VC5 applied to the winding 1, and FIG.
Shows the voltage VL5 applied to the.

First, the operation at full light will be described. The circuit operation in this case has one cycle from t50 to t55. Since the drive circuit 74 sets the frequencies of the oscillation signals a5 and b5 to be output low, t50 to t55 are in the longest state.

During the period from timing t50 to timing t51, the capacitor C11 , the switching means 61 and the primary winding L6.
Since the closed circuit of 1 is formed, the electric charge stored in the capacitor C11 is discharged, and the current from the switching means 61 flows through the primary winding L61 of the inductor 64.

In this case, the voltage VDC5 applied to the series connection of the switching means 61 and 62 shown in FIG.
Is a substantially constant value (VRec5 in this case changes depending on the phase of the output voltage of the AC power supply 51, but the switching means 6
Since there is almost no change in one cycle of turning on and off of Nos. 1 and 62, it is set to be substantially constant. ) Is maintained, the current I61 flowing through the switching means 61 shown in FIG. 13 (b) rises, and the current I61 flowing through the switching means 62 shown in FIG. 13 (c).
62 maintains 0 A, and the capacitor C1 shown in FIG.
The voltage VC5 applied to 1 gradually decreases, and the voltage VL5 applied to the winding L61 shown in FIG. 13 (e) maintains a constant negative value.

During the period from timing t51 to t52, the switching means 61 is turned off, the switching means 62 is turned on, the inductor 64 and the capacitor C12 resonate in series, and the resonance current changes from the inductor 64 to the capacitor C12.
Flow toward.

In this case, the voltage V shown in FIG.
DC5 increases due to the resonance voltage, and the current I61 flowing through the switching means 61 shown in FIG.
Current I62 flowing through the switching means 62 shown in FIG.
Rapidly decreases from 0A to the negative side, then increases and returns to 0A, and the voltage VC5 applied to the capacitor C11 shown in FIG. 13D is substantially maintained. The voltage VL5 applied to the winding L61 shown in FIG. 13 (e) increases from a constant negative value.

During the period from timing t52 to t53, with the switching means 61 turned off and the switching means 62 turned on, the resonance current due to the series resonance of the inductor 64 and the capacitor C12 is in the opposite direction from the timing t51 to t52. Flow to.

In this case, the voltage VDC5 shown in FIG.
13B, the current I61 flowing through the switching means 61 shown in FIG. 13B is maintained at 0A, and the current I62 flowing through the switching means 62 shown in FIG. 13C increases from 0A to the + side. The voltage VC5 applied to the capacitor C11 shown in d) is almost maintained. Winding L6 shown in FIG. 13 (e)
The voltage VL5 applied to 1 decreases.

During the period from timing t53 to t54, the resonance voltage decreases and the voltage across the capacitors C11 and C12 also tries to decrease. Therefore, the rectifier circuit 52 causes the capacitor C11, the inductor 64, and the switching means 6 to operate.
A current I4 flows through 2.

In this case, the voltage V shown in FIG.
DC5 becomes a substantially constant value VRec5, the current I61 flowing through the switching means 61 shown in FIG. 13 (b) maintains 0 A, and the current I62 flowing through the switching means 62 shown in FIG. 13 (c) gradually decreases, The voltage VC5 applied to the capacitor C11 shown in FIG.
The voltage VL5 applied to the winding L61 shown in (e) gradually decreases.

During the period from timing t54 to timing t55, the switching means 61 is turned on and the switching means 62 is turned off, and a current flows from the first switching means 61 to the capacitor C11 due to the energy stored in the inductor 64.

In this case, the voltage V shown in FIG.
DC5 maintains a substantially constant value VRec5, the current I61 flowing through the switching means 61 shown in FIG. 13 (b) sharply decreases and then increases, and the switching means 6 shown in FIG. 13 (c).
The current I62 flowing through 2 drops sharply to 0 A,
The voltage VC5 applied to the capacitor C11 shown in 3 (d) gradually increases, and the voltage VL5 applied to the winding L61 shown in FIG. 13 (e) sharply decreases to the negative side and becomes a constant negative value.

Next, the operation during dimming will be described. The circuit operation in this case has one cycle from t50 to t55.

Here, the ON / OFF period t50 to t55 of the switching means 61, 62 by the drive circuit 63 is set to be shorter as the dimming becomes deeper.

In FIG. 14, periods t50 to t51 and t51 to
The direction of current flow at t52 ... t54 to t55 is shown in FIG.
It is similar to the case of.

The drive circuit 63 has switching means 61, 6
Since the on / off cycle t50 to t55 of No. 2 is set shorter than that in FIG. 13, the maximum value of the voltage VDC5 during the period in which the switching means 62 shown in FIG.
The cycle and amplitude of the current I61 flowing through the switching means 61 shown in FIG.
The period and the amplitude of the current I62 flowing through the switching means 62 shown in FIG.
The voltage VC5 applied to the capacitor C11 shown in FIG. 14 (d) is decreased compared to that shown in FIG. 13 (d), and the voltage VC5 applied to the winding L61 shown in FIG. Absolute value x time, the amount of energy applied to the primary winding L61 decreases, and the output supplied from the inverter 60 to the output circuit 66 decreases.

FIG. 15 is a timing chart showing the operation of the embodiment of FIG. 11 under full light at the cycle level of the AC power supply 51. FIG. 15A shows the voltage VDC5 applied to the series connection of the switching means 61 and 62. FIG. 15B shows the lamp current IL0 flowing through the discharge lamp 65.

As shown in FIG. 15A, the voltage VDC5 at full light is a state in which the resonance voltage is added to the voltage VRec5 in the state in which the AC voltage from the rectifier circuit 52 is full-wave rectified. The resonance voltage in this case increases in accordance with the decrease in the voltage VRec5.

The lamp current IL0 at full light has an amplitude corresponding to the voltage VDC5, and the constriction rate A / B is 80%.

FIG. 16 is a timing chart showing the operation at the time of dimming of the embodiment of FIG. 11 at the cycle level of the AC power supply 51. FIG. 16A shows the voltage VDC5 applied to the series connection of the switching means 61 and 62. shown, FIG. 16 (b) shows the lamp current IL0 flowing to the discharge lamp 65.

As shown in FIG. 16A, the voltage VDC5 at the time of dimming is set to the voltage VRec5 because the capacitor C11 does not discharge the electric charge even at the timing t61 when the main voltage of the rectifier circuit 52 becomes 0V. The state is smoothed to some extent and the resonance voltage is lowered.

The lamp current IL0 during dimming is the voltage VDC5
And the constriction ratio A / B is lower than 80% (about 50% in this case).

For comparison with the present embodiment, the case where the dimming is performed with the on-duty ratio instead of the on / off cycle of the switching means 61 and 62 will be described below with reference to FIGS. 17 and 18.

FIG. 17 is a timing chart showing the operation at the time of dimming when the dimming of the embodiment of FIG. 11 is performed by the on-duty ratio of the switching means 61, 62, and FIG. 17 (a) shows the switching means 61. 17 and 62 show a voltage VDC5 applied to a series connection of the switching means 62, 62, FIG. 17B shows a current I61 flowing through the switching means 61, FIG. 17C shows a current I62 flowing through the switching means 62, and FIG.
17D shows the voltage VC5 applied to the capacitor C11, and FIG. 17E shows the voltage VL5 applied to the winding L61.

Here, the operation at full light is the same as in FIG.

In the dimming operation, one cycle (period t50 to t
55) is the same as FIG. 13, but the period (timing t54 to t50 during which the drive circuit 63 turns on the switching means 61).
By increasing (t55) to t51} and decreasing the period {timing t51 to t54} during which the switching means 62 is turned on, the on-duty ratio of the switching means 61 is set larger than that in FIG. The dimming level in this case is the same as in FIGS. 14 and 16.

In FIG. 17, periods t50 to t51 and t51 to
The direction of current flow at t52 ... t54 to t55 is shown in FIG.
It is the same as the case.

In the dimming operation, the period during which the output control circuit 63 turns on the switching means 61 (timing t54-
t50 (t55) to t51} is increased and the switching means 6
2 is reduced, the maximum value of the voltage of the rectifier circuit 52 during the period during which the switching means 62 shown in FIG.
3 (a), the ratio of the period in which the current I61 flowing through the switching means 61 shown in FIG. 17 (b) is 0 A is smaller than that in FIG. 13 (b), and is shown in FIG. 17 (c). The ratio of the period in which the current I62 flowing through the switching means 62 is 0 A is increased as compared with FIG. 13 (c), and the voltage VC5 applied to the capacitor C11 shown in FIG. 17 (d) is shown in FIG. 13 (d).
13E, the absolute value of the voltage VL5 applied to the winding L61 shown in FIG. 13 (e) × time is reduced, and the energy applied to the primary winding L51 is reduced, and the inverter 6
The output of 0 supplied to the output circuit 66 decreases.

[0141] Figure 18 is a timing chart showing the operation at the time of dimming case of performing the dimming of the embodiment of FIG. 11 in the on-duty ratio of the switching means 61 and 62 at a cycle level of ac power supply 51, FIG. 18 (a) shows a voltage VDC5 applied to the series connection of the switching means 61 and 62,
FIG. 18 (b) a lamp current IL0 flowing through the discharge lamp 65 indicates <br/>.

Since the voltage VDC5 during dimming reduces the on-duty ratio of the switching means 62 as shown in FIG. 18A, the resonance voltage is lower than that in FIG. 16A, and Since the voltage VC5 of the smoothing capacitor C11 decreases, the lamp current IL0 becomes more narrowed. The constriction rate A / B is lower than that in the case of FIG. 16B (about 30% in this case).

The case where the dimming is performed by the on-duty ratio instead of the on / off cycle of the switching means 61, 62 will be specifically described using the following table.

[0144]

[Table 1] According to such an embodiment, the same effect as the embodiment of FIG. 1 is obtained, and the constriction rate A of the lamp current IL0 at the time of dimming.
Since / B becomes higher when dimming is performed at the frequencies of the switching means 61 and 62, the flicker of the light emission of the discharge lamp 65 occurs when dimming while maintaining high input / output efficiency of the inverter 60. Can be suppressed.

FIG. 19 is a perspective view showing a lighting device to which any one of the discharge lamp lighting devices of the embodiments shown in FIGS. 1 to 11 is applied.

In FIG. 19, a lighting device 101 has discharge lamps 105 and 106 mounted in sockets 103 and 104 of a lighting fixture main body 102, a discharge lamp lighting device 107 is housed therein, and a discharge lamp lighting device 107 is used to discharge the lamp. 1
The lights 05 and 106 are turned on.

With such a structure, the embodiment shown in FIGS. 1 to 11 can be applied to the lighting device.

[0148]

According to the first aspect of the present invention, the range of output adjustment when a discharge lamp is used in the output circuit can be expanded, so that the dimming range of the discharge lamp can be expanded.

According to the second aspect of the present invention, the range of output adjustment can be expanded when a discharge lamp is used in the output circuit, and the constriction of the output current generated by the non-smoothed DC voltage of the rectifier circuit can be suppressed. Therefore, it is possible to expand the dimming range of the discharge lamp, and it is possible to suppress the flicker of light emission of the discharge lamp when dimming while maintaining high input / output efficiency.

According to the invention of claim 3, the power supply device according to any one of claims 1 and 2 can be realized by providing the second capacitor in parallel with the second switching means.

According to the invention of claim 4, by providing the second capacitor in parallel with the series connection of the first and second switching means, the power supply according to any one of claims 1 and 2. The device can be realized.

According to the invention of claim 5, claims 1 to 4
The power supply device according to any one of 1 to 3 can be applied to the discharge lamp lighting device.

According to the invention of claim 6, the discharge lamp lighting device according to claim 5 can be applied to a lighting device.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a case where an embodiment of a power supply circuit according to the present invention is applied to a discharge lamp lighting device.

FIG. 2 is a timing chart showing an operation when the output of the embodiment of FIG. 1 is set to be relatively large.

FIG. 3 is a timing chart showing an operation when the output of the embodiment of FIG. 1 is set to be relatively small.

4 is a first explanatory diagram showing the operation of the embodiment of FIG. 1. FIG.

FIG. 5 is a second explanatory diagram showing the operation of the embodiment of FIG.

6 is a graph showing the relationship between the on-duty ratio of the switching means of FIG. 1 and the output of the inverter.

7 is a first switching means of the drive circuit of FIG.
Explanatory diagram showing an example of control of FIG.

FIG. 8 is a second switching means of the driving circuit of FIG.
Explanatory diagram showing an example of control of FIG.

FIG. 9 is a circuit diagram showing a case where another embodiment of the power supply circuit according to the present invention is applied to a discharge lamp lighting device.

FIG. 10 is a circuit diagram showing a case where another embodiment of the power supply circuit according to the present invention is applied to a discharge lamp lighting device.

FIG. 11 is a circuit diagram showing a case where yet another embodiment of the power supply circuit according to the present invention is applied to a discharge lamp lighting device.

12 is a timing chart showing the relationship between the output voltage of the rectifier circuit by the output control circuit of FIG. 11 and the on time of the switching means.

13 is a timing chart showing the operation of the embodiment of FIG. 11 under full light.

14 is a timing chart showing an operation during dimming of the embodiment of FIG.

FIG. 15 is a timing chart showing the operation of the embodiment of FIG. 11 under full light at the cycle level of the AC power supply.

16 is a timing chart showing the operation during dimming of the embodiment of FIG. 11 at the cycle level of the AC power supply.

FIG. 17 is a timing chart showing an operation at the time of dimming when the dimming of the embodiment of FIG. 11 is performed by the on-duty ratio of the switching means.

FIG. 18 is a timing chart showing the operation at the time of dimming when the dimming of the embodiment of FIG. 11 is performed with the on-duty ratio of the switching means, by the cycle level of the AC power supply.

FIG. 19 is a perspective view showing a lighting device to which any one of the discharge lamp lighting devices of the embodiments shown in FIGS. 1 to 11 is applied.

FIG. 20 is a circuit diagram showing a conventional discharge lamp lighting device.

FIG. 21 is a timing chart showing the operation of the discharge lamp lighting device of FIG. 20 at full light.

22 is a timing chart showing the operation of the discharge lamp lighting device of FIG. 20 during dimming.

23 is a graph showing the relationship between the on-duty ratio of the NPN transistor of FIG. 20 and the output of the inverter.

[Explanation of symbols]

11: DC power supply 20: Inverter 21, 22: First and second switching means 23: Drive circuit 24: Inductor 26: Output circuit C1, C2: first and second capacitors

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Keiichi Shimizu Inventor Keiichi Shimizu 4-3-1, Higashishinagawa, Shinagawa-ku, Tokyo Inside Toshiba Lighting & Technology Co., Ltd. (56) HEI 6-163166 (JP, A) JP HEI 6-283286 (JP, A) JP S61-218095 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) H02M 7 / 48 H05B 41/24 H05B 41/392

Claims (6)

(57) [Claims] 1. A direct current power source for outputting a direct current voltage; first and second switching means provided in series between output terminals of the direct current power source; and provided in parallel with the first switching means. A relatively large-capacity first capacitor; an inductor interposed between the first switching means and the first capacitor; a capacity smaller than that of the first capacitor; A second capacitor forming a resonance circuit with the second switching means and the inductor during the ON period of the switching means;
Output circuit and obtaining a high-frequency output based on the resonance of the inductor and the second capacitor; together alternately turned on and off said first and second switching means, when reducing the output of the output circuit is the second And a drive circuit for reducing the on-duty ratio of the switching means. 2. A rectifying circuit for rectifying an output voltage of an AC power source to output a non-smoothed DC voltage; first and second switching means provided in series between output terminals of the rectifying circuit. A relatively large-capacity first capacitor provided in parallel with the first switching means; an inductor interposed between the first switching means and the first capacitor; A capacitor having a capacitance smaller than that of the second switching means and forming a resonance circuit with the second switching means and the inductor during the ON period of the second switching means; An output circuit for obtaining a high-frequency output based on the above; and an on-duty of these switching means while alternately turning on and off the first and second switching means. Controlled based on the ratio of the output voltage of the rectifier circuit, when changing the output of said output circuit includes a driving circuit, characterized in that to change the period of the on-off of the first and second switching means; A power supply device comprising: 3. The power supply device according to claim 1, wherein the second capacitor is provided in parallel with the second switching means. 4. The power supply device according to claim 1, wherein the second capacitor is provided in parallel with the series connection of the first and second switching means. 5. A discharge lamp lighting device, wherein a discharge lamp is provided in the output circuit of the power supply device according to any one of claims 1 to 4. 6. A lighting device comprising: the discharge lamp lighting device according to claim 5; and a lighting fixture main body that houses the discharge lamp lighting device.