JP3488105B2 - Logic circuit and logic circuit device for preventing operation analysis - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit capable of preventing an internal operation from being illegally analyzed.

[0002]

2. Description of the Related Art I used for identification, electronic money, etc.
In C, it is necessary to conceal the internal operation itself in order to protect the confidential information handled internally. Conventionally, it is considered that confidential information can be protected by a strong cryptographic method. However, this idea presupposes that the encryption key and the encryption method are not explicitly intercepted. Also, in order to protect confidential information regarding encryption,
It is necessary to protect the internal operation itself in which the confidential information may explicitly appear.

Complex encryption methods are often realized by modular processing. Cryptographic circuit designers who are familiar with cryptographic processing means assign meaningful circuit functions to each module, so significant information such as cryptographic key data is generated at the input / output terminals of each module at a predetermined timing. To do.

[0004]

By the way, in the above conventional example, a third party can easily intercept the significant information generated at the input / output terminals of each module. Therefore, if a third party illegally analyzes the internal operation and the third party attempts to illegally use confidential data, the above significant information generated at the input / output terminals of each module is There is a drawback that it becomes a useful hint and that the useful hint can be easily obtained.

In order to overcome this drawback, it is necessary to protect the internal operation, and more specifically, there has been a conventional method of randomizing secret information communicated inside a circuit based on a certain rule. Has been adopted. Although this conventional method is effective in protecting the bus connecting the processor and the memory, which are likely to be targets of fraud analysis, in general logic circuits, it is not possible to apply the method of randomizing secret information as described above. There is a problem that it is difficult.

That is, the logic circuit is a circuit that is expected to deterministically realize a specific logic function.
If a method for randomizing the above information is brought into the communication paths of these logic circuits, the number of circuits that are originally useless, such as the encryption circuit and the decryption circuit, increases, so the overhead becomes extremely large. Become. Therefore, there is a problem that it is difficult to apply the above method to randomization of secret information communicated inside the circuit.

According to the present invention, it is difficult to illegally analyze the operation of the logic circuit based on the analysis of the signal pattern at the specific terminal, and the anti-corruption analysis method can be easily applied to the general logic circuit. The purpose of the present invention is to provide a logic circuit.

[0008]

SUMMARY OF THE INVENTION According to the present invention, the internal logic configuration of a predetermined logic circuit is changed in accordance with a control signal external to the logic circuit to intercept the internal operation of the logic circuit.
It makes analysis difficult.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing a logic circuit 101 which is a first embodiment of the present invention.

The logic circuit 101 is a full adder, and can change the logic configuration of the logic circuit 101 by a control signal C.

The logic circuit 101 includes logic gates G1 and G1.
2, G3, G4, G10, G11, EXNOR gates G5, G6, G7, G8, G9, and NOT gate G12
And have. Also, the logic gates G1, G3,
The white circles above the F4 represent NOT gates.

The logic gates G1, G2, G3 and G4 are controlled by the control signal C to have a 2-input NAND function and a 2-input NOR function.
It is a logic gate that can switch between functions. The logic gates G10 and G11 are logic gates that can be switched between a 2-input EXNOR function and a 2-input EXOR function.

When the control signal C = 0, the logic gates G1, G3 and G4 realize the 2-input NOR function and the logic gate G2 realizes the 2-input NAND function.
The logic gates G10 and G11 realize the 2-input EXNOR function. On the other hand, when the control signal C = 1, the logic gates G1, G3, and G4 realize the 2-input NAND function,
The logic gate G2 realizes a 2-input NOR function, and the logic gates G10 and G11 realize a 2-input EXOR function.

C is a control signal, and A1, A2
Is an addition input in the adder, Ci is a carry input in the adder, N1 is an output signal of the logic gate G1, S is an output signal of the sum, and Co is an output signal of the carry. Is.

Further, the input stage 101 _{I of the} logic circuit 101
Is constituted by EXNOR gates G5, G6, G7, and the output stage 101 _O of the logic circuit 101 is constituted by EXNOR gates G8, G9.

FIG. 2 shows the logic gate G in the above embodiment.
It is a figure which shows the structural example of 1. Further, the logic gates G2 and G
The configurations of 3 and G4 are the same as the configuration of the logic gate G1 shown in FIG.

The logic gate G1 is a logic gate composed of a CMOS circuit that realizes a 2-input logic function, and includes a PMOS pull-up network and P
A PMOS transistor which is provided in the MOS pull-up network and whose conduction and non-conduction are determined by a control signal; an NMOS pull-down network;
A logic gate having an NMOS transistor which is provided in a pull-down network and whose conduction and non-conduction are determined by a control signal. The PMOS pull-up network is a PM that receives the input signals A1 and A2 at its gate.
The network is a network of OS transistors, and the NMOS pull-down network is a network of NMOS transistors that receives the input signals A1 and A2 at their gates.

When the control signal is C, the above PM
The OS pull-up network has a conduction condition of C ^* ^
The PMOS transistors are arranged such that (A1 + A2) + ^ (C) ^* ^ (A1 ^* A2) = 1. However, " ^* " is AND in Boolean algebra, "+" is OR in Boolean algebra, and "^"
Is NOT in Boolean algebra. In addition, the NM
The conduction condition of the OS pull-down network is C ^* (A1 +
The NMOS transistors are arranged such that A2) + ^ (C) ^* (A1 ^* A2) = 1.

When the control signal C has a logic value of 1, the logic gate G1 realizes ^ (A1 + A2), and when the control signal C has a logic value of 0, the logic gate has: It is a circuit that realizes ^ (A1 + A2).

FIG. 3 shows the logic gate G in the above embodiment.
It is a figure which shows the truth table of 1.

The truth table of the logic gates G2, G3 and G4 is the same as the truth table of the logic gate G1.

FIG. 4A is a diagram showing a specific circuit diagram of the logic gate G10 in the above embodiment. Figure 4
(2) is a diagram showing an inverting circuit that generates an inverted signal of the control signal C in the logic gate G10.

The specific circuit of the logic gate G11 is the same as the specific circuit of the logic gate G10.

FIG. 5 is a diagram showing a correspondence relationship between the logic value of the control signal C and the realized logic function in the logic gate G10.

In the logic gate G11, the correspondence between the logic value of the control signal C and the realized logic function is the same as that of the logic gate G10 shown in FIG.

Since the NOT gate G12 realizes a self-dual function (the input signal is inverted and output),
It is not necessary to change the logic with the control signal C. Also,
EXNOR gates G5, G6, G7, G8, and G9 are gates added so that the input / output signals of the adder can be inverted.

FIG. 6 is a diagram showing a first logic circuit 101 _A of the two logic configurations that can be realized by the logic circuit 101 shown in FIG.

The first logic circuit 101 _A has the configuration of the logic circuit 101 when the control signal C is set high. By setting the control signal C high, the logic gates G1, G2, G3, G4 are respectively set to NAN.
A D gate, a NOR gate, a NAND gate, and a NAND gate are realized, and the logic gates G10 and G11 are EXOR.
Realize the gate. In addition, the input stage 10 of the logic circuit 101
The EXNOR gates G5, G6, and G7 forming 1 _I are
An input signal input from the outside of the logic circuit 101 is passed as it is. The EXNOR gates G8 and G9 forming the output stage 101 _O of the logic circuit 101 allow the output signal output from the logic circuit 101 to the outside to pass therethrough.

FIG. 7 is a diagram showing a second logic circuit 101 _B of the two logic configurations that can be realized by the logic circuit 101 shown in FIG.

The second logic circuit 101 _B has the structure of the logic circuit 101 when the control signal C is set low. By setting the control signal C low, the logic gates G1, G2, G3, and G4 are respectively set to NOR.
The gates, NAND gates, NOR gates, and NOR gates are realized, and the logic gates G10 and G11 are EXNOR gates. In addition, the input stage 101 of the logic circuit 101
_The EXNOR gates G5, G6, and G7 forming _I invert an input signal input from the outside of the logic circuit 101,
EXNOR constituting the output stage 101 _O of the logic circuit 101
The gates G8 and G9 invert the output signal output from the logic circuit 101 to the outside.

The logic circuit 101 _A shown in FIG. 6 and the logic circuit 101 _B shown in FIG. 7 have the following relationship. That is, a logic function representing an arbitrary internal node in the logic circuit 101 _A is defined as f _i (A1, A2, Ci, C = 1), and a logic function representing the internal node in the logic circuit 101 _B is defined as g _i (A1, A2, Ci, C = 0), a function obtained by inverting the logical function g _i (A1, A2, Ci, C = 0) is
It is a logical function f _i (A1, A2, Ci, C = 1). That is, in the logic circuit 101 _A and the logic circuit 101 _B , the signals of the respective internal nodes are in an inverse relationship with each other.

Logical function g _i (A1, A2, Ci, C =
0) and the logical function f _i (A1, A2, Ci, C = 1) have a simple correspondence, but by switching between these logical functions randomly in time,
It is possible to prevent a fixed signal pattern from being generated on a specific internal node.

By switching the logical configuration as described above,
Even when the same input signal pattern is added, the signal pattern at a predetermined internal node changes. If the switching of the logical configuration is controlled based on the random number signal synchronized with the input signal, the internal node signal can be changed randomly. That is, even if the signal pattern on this internal node is observed for a predetermined fixed time, a fixed pattern cannot be obtained, and it is difficult to analyze the operation of the logic circuit by using the information intercepted by a third party as a clue.

The above embodiment was realized by a CMOS structure, and its operation was confirmed by circuit simulation.

FIG. 8 is a diagram showing a signal waveform in a main part of the logic circuit 101, in which the input signals A1, A2 and Ci are:
FIG. 7 is a diagram showing output signals S and Co and a signal N1 at an internal node N1 when a pattern that changes sequentially is repeatedly applied twice.

In the above embodiment, the input signals A1, A
2, Ci is (A1, A2, Ci) = (0, 0, 0)
(0,1,0) (1,0,0) (1,1,0) (0,
0,1) (0,1,1) (1,0,1) (1,1,1)
FIG. 8 shows the output signals S and Co and the signal N1 of the internal node signal N1 in the case where the sequentially changing pattern is repeatedly applied twice as described above.

The control signal C is switched from 1 to 0 in the vicinity of 26 ns shown in FIG. The output signals S and Co repeat the same pattern before and after the switching point of the control signal C, but the signal N1 at the internal node N1 is repeated.
Are different patterns having an inversion relation before and after the switching point. By frequently changing the control signal C, the signal N1 at the internal node N1 can be changed more complicatedly. Therefore, in the above embodiment, the randomness of the control signal C is changed to the randomness of the signal level of the internal node without imposing such a heavy circuit load.
Can be transcribed.

In the above embodiment, the logic gate G1 shown in FIG. 2 is used as a logic gate capable of switching between a 2-input NAND gate and a 2-input NOR gate so that the two logic configurations can be changed at high speed. I'm using it.

FIG. 9 is a diagram showing another configuration example of the logic gate G1.

The configuration example shown in FIG. 9 is an example configured by a multi-stage logic gate. Instead of the logic gate G1 shown in FIG. 2, a multi-stage logic gate shown in FIG. 9 can be used. However, when the multi-stage logic gate shown in FIG. 9 is used as described above, a new circuit problem arises such that the circuit scale becomes large and the speed performance is deteriorated. From the viewpoint of circuit scale and speed performance, a logic gate having a composite gate structure as shown in FIG. 2 is desirable.

In the above embodiment, the logic gates G5, G
Reference numerals 6 and G7 are examples of first logic gates capable of inverting an input signal input by the logic circuit in accordance with an external control signal, and logic gates G8 and G9 output signals output by the logic circuit. It is an example of a second logic gate that can be inverted according to an external control signal, and includes logic gates G1, G2, G3, G4,
G10, G11, and G12 are examples of a third logic gate that is connected between an input stage and an output stage of a logic circuit and that can switch two types of logic functions in a dual relationship by an external control signal. Is.

That is, in the above embodiment, in the logic circuit composed of a plurality of logic gates, the input signal inputted by the logic circuit is invertible in accordance with the external control signal, and the first logic gate is provided. A signal output from the logic circuit is connected between a second logic gate that can be inverted according to an external control signal and an input stage and an output stage of the logic circuit, and has two types of dual relationship. And a third logic gate switchable by an external control signal,
It is an example of a logic circuit in which the internal logical configuration of the logic circuit can be changed by the external control signal while maintaining the logical relationship between the input signal and the output signal of the logic circuit.

That is, in the above-described embodiment, the logical function which is in a dual relationship with the logical function realized by the initial logical circuit is used, and the logical configuration inside the logical circuit is changed in two ways.
The function of each logic gate that makes up the logic circuit is changed between two logic functions that are in a dual relationship, and the input / output signals are corrected by inversion operation, and the internal logic function is maintained. It is an example of changing the logical configuration of.

FIG. 10 is a circuit diagram showing a logic circuit device 102 according to a second embodiment of the present invention.

The logic circuit device 102 is a device using n logic circuits 101 such as the logic circuit 101. That is,
The logic circuit device 102 includes n logic circuits 101 ₁ , 10
1 ₂ , ..., 101 _n-1 , 101 _n .

Logic circuits 101 ₁ , 101 ₂ , ..., 10
1 _n-1 , 101 _n are control signals C ₁ , C ₂ ,
......, C _n-1 and C _n can be switched to two kinds of logical configurations, respectively.
Can realize 2 ⁿ different logical configurations as a whole.

That is, in the logic circuit device 102, the first logic gate which can invert an input signal inputted by the logic circuit composed of a plurality of logic gates in accordance with an external control signal, and the logic circuit A signal to be output is connected between a second logic gate that can be inverted and an input stage and an output stage of the logic circuit according to an external control signal, and two logic functions in a dual relationship are provided. A third logic gate that can be switched by an external control signal, and the third control circuit of the logic circuit is controlled by the external control signal while maintaining the logical relationship between the input signal and the output signal of the logic circuit. Having a plurality of logic circuits that can change the internal logic configuration, the external control signals are different from each other for each of the logic circuits, and according to a predetermined combination of the set of external control signals,
It is an example of a logic circuit device capable of changing the internal logical configuration and preventing operation analysis.

In this case, by using a plurality of control signals, it is possible to further increase the variation of the logical configuration of the entire logic circuit device.

FIG. 11 is a circuit diagram showing a logic circuit 103 which is a third embodiment of the present invention. The logic circuit 103 is
It is a full adder that uses a pseudo-random number as a control signal for controlling (changing) the internal logic configuration that constitutes the logic circuit. That is, the logic circuit 103 is the logic circuit 101 provided with the registers G12 and G14 and the pseudo random number generation circuit G13. The registers G12 and G14 are for temporarily holding a predetermined signal and are for synchronizing by using the clock CK. However, if the timing can be adjusted by another method, the register G12, G
14 may be deleted.

FIG. 12 is a circuit diagram showing a specific example of the pseudo random number generation circuit G13 in the above embodiment.

The pseudo random number generation circuit G13 includes an EXNOR gate G13 ₁ and D flip-flops G13 ₂ and G13.
₃ and G13 ₄ . By using this pseudo random number generation circuit G13, the control signal C can be changed at random. The operation of the logic circuit 103 was confirmed by circuit simulation.

FIG. 13 is a diagram showing an example of the operation of the logic circuit 103.

Input signals to the logic circuit 103 (A1, A
2, Ci) is (0,0,0) (0,1,0) (1,
0,0) (1,1,0) (0,0,1) (0,1,1)
The output signal S when an input pattern is added so as to sequentially change as (1, 0, 1) (1, 1, 1),
Changes in Co, the control signal C, and changes in the signal on the internal node N1 are shown in FIG.

In FIG. 13, the input pattern to the logic circuit 103 has the same pattern repeated twice around 28 ns. Focusing on the output signals S and Co, the same pattern is repeated twice corresponding to the repetition of the input sequence. However, the signal on internal node N1
The repeating pattern does not appear and the pattern is random. This corresponds to that the control signal C for changing the logical configuration changes randomly, and indicates that the randomness of the pseudo-random number can be transferred to the randomness of the logical configuration.

That is, the logic circuit 103 uses a logic function that is in a dual relationship with the logic function realized by the initial logic circuit, changes the logic configuration inside the logic circuit in two ways, and The function of each logic gate to be configured is changed between two logic functions having a dual relationship, and the correction of the inverting operation is added to the input / output signal, and the internal logic configuration is maintained while maintaining the entire logic function. This is an example in which the logical configuration itself is randomly changed with time by using a control signal to perform this operation randomly.

FIG. 14 is a circuit diagram showing a logic circuit device 104 which is a fourth embodiment of the present invention.

The logic circuit device 104 uses n logic circuits excluding the pseudo random number generating circuit G13 from the logic circuit 103, and uses n separate pseudo random number generating circuits R similar to the pseudo random number generating circuit G13. is there. That is, the logic circuit device 104 includes n logic circuits 103 ₁ , 103 ₂ , ...
, 103 _n-1 , 103 _n , and n pseudo random number generation circuits R ₁ , R ₂ , ..., R _n-1 , R _n . Therefore, the logic circuits 103 ₁ , 103 ₂ , ..., 103 _n-1 ,
103 _n is a pseudo random number generation circuit G1 from the logic circuit 103.
It is a logic circuit excluding 3.

In addition, n logic circuits 103 ₁ and 103
_2, ..., as the control signal C ₁ -C _n for 103 _n, are respectively using the output signal of the pseudo-random number generation circuit R ₁ to R _n. In addition, these pseudo random number generation circuits R ₁ to
The R _n, may be prepared independently for all n logic circuits 103 ₁ 10 @ 2 to 10 @ 3 _n, or may be shared by several units. Control signals C ₁ , C ₂ , ...
The random number signal added to C _n is generated in synchronization with the clock signal applied to each logic circuit.

Logic circuits 103 ₁ , 103 ₂ , ..., 10
3 _n-1 , 103 _n are control signals C ₁ , C ₂ ,
......, C _n-1 and C _n can be switched to two kinds of logical configurations, respectively, and 2 ⁿ logical configurations can be realized as a whole, and 2 ⁿ logical configuration combinations are possible. In particular, since the switching of the combination is random, it becomes more difficult to perform an illegal operation analysis based on the analysis of the signal pattern of a specific terminal.

FIG. 15A is a diagram showing a circuit diagram of the logic circuit 105 according to the fifth embodiment of the present invention.
(2) is a diagram showing an inverting circuit that generates an inverted signal of the control signal C in the logic circuit 105.

The logic circuit 105 has three input signals A1,
A2 and A3 are input, and depending on the control signal C, 3-input AN
It is a logic circuit that can be switched between a D-NOR gate and a 3-input OR-NAND gate. Also, the logic circuit 1
Reference numeral 05 is an example realized by a CMOS composite gate structure, which is composed of 28 MOSFETs.

FIG. 16 is a diagram showing a correspondence relationship between the logical value of the control signal C and the realized logical function in the logic circuit 105.

FIG. 17 is a diagram showing a circuit diagram of the logic circuit 106 according to the sixth embodiment of the present invention.

The logic circuit 106 has three input signals A1,
A2 and A3 are input, and depending on the control signal C, 3-input AN
It is a logic circuit that can be switched between a D-NOR gate and a 3-input OR-NAND gate. In addition, the logic circuit 10
6 is another example realized by a CMOS composite gate structure, which is composed of 20 MOSFETs. The correspondence between the logic value of the control signal C and the realized logic function in the logic circuit 106 is the same as the correspondence shown in FIG.

FIG. 18 is a diagram showing a circuit diagram of the logic circuit 107 according to the seventh embodiment of the present invention.

The logic circuit 107 has three input signals A1,
A2 and A3 are input, and depending on the control signal C, 3-input AN
It is a logic circuit that can be switched between a D-NOR gate and a 3-input OR-NAND gate. In addition, the logic circuit 10
Reference numeral 7 is another example realized by a CMOS composite gate structure, which is composed of 16 MOSFETs. Note that the correspondence between the logic value of the control signal C and the realized logic function in the logic circuit 107 is the same as the correspondence shown in FIG.

FIG. 19 is a diagram showing a circuit diagram of the logic circuit 108 according to the eighth embodiment of the present invention.

The logic circuit 108 has four input signals A1,
It is a logic circuit that inputs A2, A3, and A4 and can switch between a 4-input AND-NOR gate and a 4-input OR-NAND gate according to a control signal C. Logic circuit 10
Reference numeral 8 is an example realized by a CMOS composite gate structure, which is composed of 28 MOSFETs.

FIG. 20 is a diagram showing the correspondence between the logic value of the control signal C and the logic function to be realized in the logic circuit 108.

FIG. 21 is a diagram showing a circuit diagram of the logic circuit 109 according to the ninth embodiment of the present invention.

The logic circuit 109 has four input signals A1,
It is a logic circuit that inputs A2, A3, and A4 and can switch between a 4-input AND-NOR gate and a 4-input OR-NAND gate according to a control signal C. The logic circuit 109 is another example realized by a CMOS composite gate structure, and is composed of 20 MOSFETs. The correspondence relationship between the logic value of the control signal C and the realized logic function in the logic circuit 109 is the same as the correspondence relationship shown in FIG.

[0072]

According to the present invention, since the internal logical configuration of the logic circuit changes with time while maintaining a predetermined function, an illegal operation analysis based on the analysis of the signal pattern of a specific terminal can be performed. It has the effect of being difficult.

[Brief description of drawings]

FIG. 1 is a diagram showing a logic circuit 101 which is a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a logic gate G1 in the above embodiment.

FIG. 3 is a diagram showing a truth table of a logic gate G1 in the above embodiment.

FIG. 4 is a diagram showing a specific circuit diagram of a logic gate G10 in the embodiment.

FIG. 5 is a diagram showing a correspondence relationship between a logic value of a control signal C and a realized logic function in a logic gate G1.

FIG. 6 shows a first logic circuit 101 _{A of} two logic configurations that can be realized by the logic circuit 101 shown in FIG.
FIG.

FIG. 7 shows a second logic circuit 101 _{B of} two logic configurations that can be realized by the logic circuit 101 shown in FIG.
FIG.

FIG. 8 shows the input signals A1, A2, C in the above embodiment.
The output signals S and Co and the internal node signal N1 in the case where i is applied twice in a pattern that changes sequentially
6 is a diagram showing a signal waveform of a signal N1 in FIG.

FIG. 9 is a diagram showing another configuration example of the logic gate G1.

FIG. 10 is a logic circuit device 1 according to a second embodiment of the present invention.
It is a circuit diagram showing 02.

FIG. 11 is a logic circuit 103 according to a third embodiment of the present invention.
It is a circuit diagram showing.

FIG. 12 is a pseudo random number generation circuit G13 in the above embodiment.
3 is a circuit diagram showing a specific example of FIG.

13 is a diagram showing an example of operation of the logic circuit 103. FIG.

FIG. 14 is a logic circuit device 1 according to a fourth embodiment of the present invention.
It is a circuit diagram which shows 04.

FIG. 15 is a logic circuit 105 according to a fifth embodiment of the present invention.
FIG.

16 is a diagram showing a correspondence relationship between a logical value of a control signal C and a realized logical function in the logic circuit 105. FIG.

FIG. 17 is a logic circuit 106 according to a sixth embodiment of the present invention.
FIG.

FIG. 18 is a logic circuit 107 according to a seventh embodiment of the present invention.
FIG.

FIG. 19 is a logic circuit according to an eighth embodiment of the present invention.
FIG.

20 is a diagram showing a correspondence relationship between a logic value of a control signal C and a logic function to be realized in the logic circuit 108. FIG.

FIG. 21 is a logic circuit 109 according to a ninth embodiment of the present invention.
FIG.

[Explanation of symbols]

101-109 ... logic, Al to A4, Ci ... input signal, S, Co, Y ... output signal, C, C ₁ ~C _n ... control signal, CK ... clock signal, G1 to G12 ... logic gate, G13, R _{1 to} R _n ... Pseudo random number generation circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03K 19/20 G06F 7/58 H04L 9/10 G06F 7/50

Claims (6)

(57) [Claims] 1. A logic circuit comprising a plurality of logic gates, wherein a first logic gate capable of inverting an input signal input by the logic circuit in response to an external control signal; A second logic gate capable of inverting a signal corresponding to an external control signal; two logic functions connected in a dual relationship, connected between an input stage and an output stage of the logic circuit, A third logic gate that can be switched by an external control signal; and while maintaining the logical relationship between the input signal and the output signal of the logic circuit, the third control circuit is controlled by the external control signal. A logic circuit that prevents operation analysis, characterized in that the internal logic configuration can be changed. 2. The logic circuit according to claim 1, wherein the external control signal is a random number signal generated by a random number generator. 3. The logic gate according to claim 1 or 2, wherein the third logic gate is a logic gate configured by a CMOS circuit that realizes a logic function of n inputs, and a PMOS pull-up network; A PMOS transistor which is provided in the PMOS pull-up network and whose conduction and non-conduction are determined by a control signal; NM
An OS pull-down network; an NMOS transistor which is provided in the NMOS pull-down network and whose conduction and non-conduction are determined by a control signal; and the control signal C, which is realized by the CMOS logic circuit. When the logical function of the input is f (x ₀ , x ₁ , ..., X _n-1 ), the conduction condition of the PMOS pull-up network is C ^* f (x ₀ , x ₁ , ..., X _n-1). ) + ^ C ^* ^
_{f (^ x 0, ^ x} 1, ..., ^ x n-1) = to be a 1, the PMOS transistor is located (however, ^*
Is AND in Boolean algebra, + is OR in Boolean algebra, and ^ is NOT in Boolean algebra),
In addition, the conduction conditions of the NMOS pull-down _{^{network, C * ^ f (x 0}} , x 1, ..., x n-1) + ^ C * f
As (^ x ₀ , ^ x ₁ , ..., ^ x _n-1 ) = 1,
When the NMOS transistor is arranged and the control signal C has a logical value of 1, the CMOS
The logic circuit realizes f (x ₀ , x ₁ , ..., X _n−1 ),
When the control signal C has a logical value of 0, the CMOS
The logic circuit is a circuit that realizes ^ f (^ x ₀ , ^ x ₁ , ..., ^ x _n-1 ) and is a logic circuit that prevents operation analysis. 4. A first logic gate capable of inverting an input signal input by a logic circuit composed of a plurality of logic gates in accordance with an external control signal, and a signal output by the logic circuit, A second logic gate that is invertible in accordance with the control signal of 1), and is connected between the input stage and the output stage of the logic circuit,
A third logic gate that can be switched by an external control signal, and the internal of the logic circuit is controlled by the external control signal while maintaining the logical relationship between the input signal and the output signal of the logic circuit. A plurality of logic circuits whose logic configuration can be changed, the external control signals are different from each other for each logic circuit, and the internal logical configuration depends on a predetermined combination of the set of external control signals. A logic circuit device for preventing operation analysis characterized by being capable of changing. 5. The logic circuit device according to claim 4, wherein the combination of different control signals is a combination determined by a random number signal generated by a random number generator. 6. The logic gate according to claim 4, wherein the third logic gate is a logic gate configured by a CMOS circuit that realizes a logic function of n inputs, and a PMOS pull-up network; A PMOS transistor which is provided in the PMOS pull-up network and whose conduction and non-conduction are determined by a control signal; NM
An OS pull-down network; and an NMOS transistor provided in the NMOS pull-down network, the conduction and non-conduction of which are determined by a control signal; and the control signal C, which is realized by the CMOS logic circuit. When the logical function of the input is f (x ₀ , x ₁ , ..., X _n-1 ), the conduction condition of the PMOS pull-up network is C ^* f (x ₀ , x ₁ , ..., X _n-1). ) + ^ C ^* ^
_{f (^ x 0, ^ x} 1, ..., ^ x n-1) = to be a 1, the PMOS transistor is located (however, ^*
Is AND in Boolean algebra, + is OR in Boolean algebra, and ^ is NOT in Boolean algebra),
In addition, the conduction conditions of the NMOS pull-down _{^{network, C * ^ f (x 0}} , x 1, ..., x n-1) + ^ C * f
As (^ x ₀ , ^ x ₁ , ..., ^ x _n-1 ) = 1,
When the NMOS transistor is arranged and the control signal C has a logical value of 1, the CMOS
The logic circuit realizes f (x ₀ , x ₁ , ..., X _n−1 ),
When the control signal C has a logical value of 0, the CMOS
A logic circuit device for preventing operation analysis, wherein the logic circuit is a circuit that realizes ^ f (^ x ₀ , ^ x ₁ , ..., ^ x _n-1 ).