JP3491561B2 - Frequency multiplier - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency multiplier, and more particularly to a frequency multiplier incorporated and used in mobile communication equipment.

[0002]

2. Description of the Related Art Generally, in a mobile phone, a local oscillator circuit having a crystal oscillator generates a reference signal. The reference signal is frequency-multiplied by a frequency multiplier and used as a local oscillation frequency signal for obtaining an intermediate frequency signal from the input signal. The local oscillation frequency signal is supplied to a mixer circuit together with an input signal of a mobile phone, and an intermediate frequency signal having a frequency equal to the difference between the input signal and the local oscillation frequency signal is taken out from the mixer circuit. FIG. 7 shows an example of the circuit configuration of such a frequency multiplier.

The frequency multiplier shown in FIG. 7 is an example of a circuit adopted when a high multiplication order (5 times or more) is required, and is composed of two class C amplifier circuits Ap1 and Ap2. A reference signal generated by a local oscillator circuit (not shown) is supplied to the input terminals 1 and 2. The first-stage class C amplifier circuit Ap1 of the frequency multiplier includes a transistor Q1, two tuning circuits 11 and 12, a bias resistor R1.
1, R12, a bypass capacitor Cs1 for grounding one end of the tuning circuit 11 in an AC manner, and a coupling capacitor C3.
And a bias cut capacitor C1 for blocking direct current
It consists of

The second-stage class C amplifier circuit Ap2 also has exactly the same circuit configuration as the first-stage class C amplifier circuit Ap1.
It is composed of a transistor Q2, two tuning circuits 21 and 22, bias resistors R21 and R22, a bypass capacitor Cs2 that grounds one end of the tuning circuit 21 in an AC manner, a coupling capacitor C5, and a bias cut capacitor C2 that blocks direct current. There is. The output of the second-stage class C amplifier circuit Ap2 is a DC bias cut capacitor C4.
Through the output terminals 3 and 4.

A constant voltage is applied from the power supply terminal 5 through the power supply line 6 to the first-stage class C amplifier circuit Ap1 and the second-stage class C amplifier circuit Ap2. In addition, a capacitor C connected between the power line 6 and the ground
Reference numeral s3 is a decoupling capacitor for preventing the signal on the side of the second-stage class C amplifier circuit Ap2 from feeding back to the side of the first-stage class C amplifier circuit Ap1 through the power supply line 6.

In the class C amplifier circuit Ap1 in the first stage, the bias resistor R12 is adjusted to operate the transistor Q1 in class C, thereby generating harmonics of the reference signal supplied from the input terminals 1 and 2. By adjusting the resistance value of the bias resistor R11, the amplification degree and current consumption of the transistor Q1 are adjusted. The tuning circuit 11 is electrically connected to the collector of the transistor Q1. The tuning circuit 11 is composed of a parallel circuit of an inductor L11 and a capacitor C11. The tuning frequency of the tuning circuit 11 is tuned to a desired harmonic wave (m-order harmonic wave) of the harmonics of the reference signal amplified by the transistor Q1 in class C. As a result, only the m-order multiplied wave of the reference signal is selectively amplified, and the other frequency multiplied waves are bypassed by the bypass capacitor Cs.
It is grounded via 1 and is not amplified.

The tuning circuit 12 is coupled to the tuning circuit 11 via a coupling capacitor C3 and functions as a filter for selecting only the m-order multiplied wave. Tuning circuit 12
Is composed of a parallel circuit of an inductor L12 and a capacitor C12. The coupling capacitor C3 adjusts its capacitance value to adjust the coupling degree of the tuning circuits 11 and 12, thereby adjusting the amplification degree and spurious suppression of the class C amplifier circuit Ap1. As a result, the m-th harmonic wave signal obtained by multiplying the frequency of the reference signal by m is input from the first-stage class C amplifier circuit Ap1 to the next second-class class C amplifier circuit Ap2.

In the second-stage class C amplifier circuit Ap2, the bias resistor R22 is adjusted to operate the transistor Q2 in the class C operation, so that the mth-order multiplied signal input from the first-stage class C amplifier circuit Ap1 is input. Generate harmonics. The tuning circuit 21 is electrically connected to the collector of the transistor Q2. The tuning circuit 21 is composed of a parallel circuit of an inductor L21 and a capacitor C21. The tuning frequency of the tuning circuit 21 is C by the transistor Q2.
Of the harmonics of the m-order multiplied wave signal that has been class-amplified, the desired harmonic wave (m × n-order multiplication number) is tuned. As a result, only the nth-order multiplied wave of the mth-order multiplied wave signal is selectively amplified, and the multiplied waves of other frequencies are grounded to the ground via the bypass capacitor Cs2 and are not amplified.

The tuning circuit 22 is coupled to the tuning circuit 21 via the coupling capacitor C5 and functions as a filter for selecting only the m × n-order multiplied wave. The tuning circuit 22 is composed of a parallel circuit of an inductor L22 and a capacitor C22. As a result, a signal obtained by multiplying the frequency of the reference signal by m × n is output from the second-stage class C amplifier circuit Ap2.

By the way, when the reference signal supplied to the input terminals 1 and 2 has a frequency of 10 to 100 MHz, the DC bias cut capacitor C1 is conventionally several hundred to several.
A large capacity of about several thousand pF was used. This is because it is considered that the impedance becomes sufficiently small and the level of the input reference signal can be kept large.

[0011]

However, a capacitor having a capacitance of several thousand pF is too large in size, and it is difficult to form a frequency doubler by mounting it on one printed board together with other components Q1 and Q2. there were. Therefore, the DC bias cutting capacitor C1 must be an external component, and there is a problem that the size of the frequency multiplier becomes large.

A DC bias cut capacitor C
If a large-capacity capacitor of several hundreds to several thousands pF is used as 1, the noise blocking capability is lowered, and for example, noise to be cut, such as static electricity, passes and the class C amplifier circuit Ap is used.
The transistor Q1 of 1 may be destroyed. For this reason, it is necessary to take measures such as providing a noise cut circuit separately.

Further, recent research by the applicant has revealed that the level of the output reference signal can be kept large without increasing the capacitance of the DC bias cutting capacitor C1.

Therefore, an object of the present invention is to provide a small frequency multiplier that keeps the level of the output reference signal at a high level and is strong against the destruction of the active element due to noise.

[0015]

In order to achieve the above object, the frequency multiplier according to the present invention has a tuning circuit connected to an amplifier circuit composed of active elements, and a frequency of a signal input to the amplifier circuit. Of the multiplied wave signal
A frequency multiplier output from the amplifier circuit, wherein a DC bias cut capacitor connected to the input side of the amplifier circuit is built in a multilayer substrate on which the active element is mounted . The capacitance of the DC bias cutting capacitor is set to 100 pF or less, for example.

[0016]

With the above construction, since the capacity of the DC bias cutting capacitor connected to the input side of the amplifier circuit is small, the noise blocking ability of the DC bias cutting capacitor is enhanced. Therefore, the destruction of the active element due to noise can be suppressed. Moreover, the level of the output reference signal is also kept high.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a frequency multiplier according to the present invention will be described below with reference to the accompanying drawings.

[First Embodiment, FIGS. 1 to 3]
One embodiment applied to the frequency multiplier having the circuit configuration described in FIG. 7 is shown in FIGS. 1 and 2 are exploded perspective views conceptually showing the configuration of the frequency multiplier having the electric circuit described in FIG. Further, FIG. 3 is a perspective view showing an appearance of the first embodiment. 1 and 2, only a part of the via hole for electrically connecting the layers is shown, and only a part of the extraction electrode for electrically connecting the internal electrode and the external terminal. Not listed.

The frequency multiplier has an insulating sheet 31 provided with an internal connection pattern 33 and capacitor electrodes 35a, 3a.
5b etc. provided insulating sheet 31, inductor patterns 38a, 38b etc. provided insulating sheet 31, wide area ground electrode 42 provided insulating sheet 31, and power supply pattern 43 provided insulating sheet 31 and pad 3
2 is provided on the insulating sheet 31 and the like.

The internal connection pattern 33 electrically connects the respective parts in order to realize the electric circuit shown in FIG.
Capacitor electrodes 35a and 35b, capacitor electrode 36a
And 36b and the capacitor electrodes 36a and 36c face each other with the sheet 31 interposed therebetween, and the coupling capacitors C3 and C5 and the tuning capacitor C21 are provided.
To form.

The inductor patterns 38a to 38c are electrically connected in series via a via hole 45 provided in the sheet 31, and the tuning circuit 2 of the second-stage class C amplifier circuit Ap2.
1 tuning inductor L21 is formed. The inductor patterns 39a to 39c are electrically connected in series via a via hole 45 provided in the sheet 31, and the tuning circuit 22a.
The tuning inductor L22 is formed. The inductor patterns 40a to 40c are electrically connected in series via the via hole 45 provided in the sheet 31, and the tuning inductor L11 of the tuning circuit 11 of the first-stage class C amplifier circuit Ap1.
To form. The inductor patterns 41a to 41c are electrically connected in series via a via hole 45 provided in the sheet 31, and form the tuning inductor L12 of the tuning circuit 12.

Further, the power supply pattern 43 is formed on the sheet 31.
The decoupling capacitor Cs3 is formed together with the ground electrode 42 so as to face the ground electrode 42.

The sheets 31 having the above-mentioned structure are stacked and integrally fired to form a multi-layer substrate 51 as shown in FIG. In the multilayer substrate 51,
Four spiral tuning inductors L11, L12, L2
1, L22 are formed at the same position in the plate thickness direction. Input terminals 1 and 2, output terminals 3 and 4, a power supply terminal 5 and a ground terminal G are formed on the side surface of the multilayer substrate 51. Further, the pads 32 on the upper surface of the multi-layer substrate 51 have transistors Q1 and Q2, capacitors C1 and C, respectively.
2, C4, C11, C12, C22, Cs1, Cs2 and resistors R11, R12, R21, R22 are soldered.

In this way, the frequency multiplier having the electric circuit shown in FIG. 7 is obtained. In this frequency multiplier, the capacity of the DC bias cut capacitor C1 connected to the input side of the first-stage class C amplifier circuit Ap1 is set to 100 pF or less. Therefore, the DC bias cut capacitor C1 has a high noise blocking capability, and the transistor Q1 can be prevented from being damaged by noise. Moreover, the level of the output reference signal is also kept high. Also, the capacitance of the DC bias cutting capacitor C1 is 100 pF.
Since it is smaller than the following, the size is also small, and it can be mounted on the multilayer substrate 51 as a discrete component. As a result, a small frequency multiplier can be obtained.

[Second Embodiment, FIGS. 4 to 6]
Another embodiment applied to the frequency multiplier having the circuit configuration described in FIG. 7 is shown in FIGS. In the second embodiment, the DC bias cut capacitor C1 connected to the input side of the first-stage class C amplifier circuit Ap1 is built in the multilayer substrate 51. By providing the capacitor electrodes 34a and 34b of the DC bias cutting capacitor C1 having a capacitance of 100 pF or less in a wide space of the multilayer substrate 51, the size of the frequency multiplier can be further reduced. In addition, by incorporating the device in a large element pattern with a large area and a large area, it is possible to secure a large withstand voltage against noise such as static electricity.

Further, two class C amplifier circuits Ap1 and Ap are provided.
Of the two, the tuning inductors L11 and L12 of the first-stage class C amplifier circuit Ap1 have a low frequency (100 MHz or less).
The tuning inductors L11 and L1 to handle the signal of
No. 2 requires a large inductance value. Therefore, the wide space of the multi-layer substrate 51 is set to the tuning inductor L1.
Inductor patterns 61 that respectively configure 1 and L12
The use of a to 61c and 62a to 62c increases the cross-sectional area of the inductors L11 and L12.
As a result, while maintaining a large inductance value,
The number of windings of the inductors L11 and L12, in other words, the number of layers of the inductor pattern can be reduced and the multilayer substrate 51 can be thinned. 4 to 6, parts corresponding to those in FIGS. 1 to 3 are designated by the same reference numerals,
A duplicate description will be omitted.

[Other Embodiments] The present invention is not limited to the above embodiments, but can be variously modified within the scope of the gist thereof. For example, the capacitors such as the coupling capacitors C3 and C5, the bypass capacitors Cs1 and Cs2, and the decoupling capacitor Cs3 may be built in the multilayer substrate 51, or may be mounted as discrete components on the multilayer substrate 51. Alternatively, instead of mounting these capacitors on the multilayer substrate 51, they may be mounted on another circuit board. The tuning inductor built in the multilayer substrate may be at least one tuning inductor of the frequency multiplier. In addition to the npn-type transistor, a pnp-type transistor, a field effect transistor (FET), or the like may be used as the active element. Further, the amplifier circuit may have three or more stages.

[0028]

As is apparent from the above description, according to the present invention, the DC bias cutting capacitor connected to the input side of the amplifier circuit is built in the substrate on which the active element of the amplifier circuit is mounted. Therefore, the frequency multiplier can be downsized. Further, by setting the capacitance of the DC bias cutting capacitor to 100 pF or less, the noise blocking ability of the DC bias cutting capacitor can be enhanced, and the destruction of the active element due to noise can be prevented. Moreover, the level of the output reference signal can be kept high.

[Brief description of drawings]

FIG. 1 is an exploded perspective view showing a partial configuration of a first embodiment of a frequency multiplier according to the present invention.

FIG. 2 is an exploded perspective view showing the configuration of the remaining part of the frequency multiplier shown in FIG.

FIG. 3 is a perspective view showing an overall appearance of the frequency multiplier shown in FIGS. 1 and 2.

FIG. 4 is an exploded perspective view showing a partial configuration of a second embodiment of the frequency multiplier according to the present invention.

5 is an exploded perspective view showing the configuration of the remaining part of the frequency multiplier shown in FIG.

6 is a perspective view showing an external appearance of the entire frequency doubler shown in FIGS. 4 and 5. FIG.

FIG. 7 is an electric circuit diagram showing a circuit configuration of a frequency multiplier.

[Explanation of symbols]

31 ... Insulating sheet 51 ... Multilayer substrate Ap1, Ap2 ... Class C amplifier circuit 11, 12, 21, 22, ... Tuning circuit Q1, Q2 ... Transistor (active element) C1 ... DC bias cut capacitor 34a, 34b ... Capacitor electrodes

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H03B 19/14

Claims (2)

(57) [Claims] 1. A frequency multiplier in which a tuning circuit is connected to an amplifier circuit composed of active elements, and a multiplied wave signal in which the frequency of a signal input to the amplifier circuit is multiplied is output from the amplifier circuit. A frequency multiplier, wherein a DC bias cut capacitor connected to the input side of the amplifier circuit is built in a multilayer substrate on which the active element is mounted. 2. A method according to claim 1, wherein the capacitance of the capacitor for the DC bias cut is less than 100pF
The frequency multiplier as claimed in.