JP3494083B2 - Method for manufacturing semiconductor device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device suitable for a system LSI or the like.

[0002]

2. Description of the Related Art Conventionally, a so-called system LSI (Large-Scale-In) in which a plurality of functions are integrated on one chip
integrated circuit: large-scale integrated circuit) exists.

In the conventional method of manufacturing a system LSI, a plurality of functional block circuits, which are units of specific circuit functions, are manufactured on a silicon chip, and then circuit wirings electrically connected to the functional block circuits are formed on the surface of the silicon chip. It is formed by metal deposition or metal plating on the above, an insulating layer is formed on this, and these circuit wiring layers and insulating layers are sequentially laminated to form a global wiring layer which is a multilayer wiring layer on the silicon chip. Then, finally, a pad serving as a connection terminal to an external circuit is formed on the global wiring layer, a bump made of a solder ball or the like is formed on this pad, or a thin metal wire is wire-bonded.

The bumps were directly formed on the pads by a method such as metal plating, solder ball mounting, and transfer.

[0005]

However, the conventional system LSI has the following problems.

First, in the method of forming bumps on pads, the bumps are formed by metal plating, solder ball mounting, etc.
There is a problem that it is difficult to process minutely and with high precision to the following and it is impossible to realize higher density mounting of the system LSI.

As a second point, the wire bonding method has a problem that the wire cannot be bonded unless the size of the pad is large to a certain extent, and similarly, higher density mounting of the system LSI cannot be realized.

An object of the present invention is to provide a method of manufacturing a semiconductor device, which can form external connection terminals with a fine pitch and high precision.

[0009]

In order to solve the above problems, the present invention adopts the following novel characteristic methods.

The features of the semiconductor device manufacturing method of the present invention are as follows:
A groove (11a in FIG. 2B) having a specific pattern is formed on the surface of the first semiconductor wafer (11 in FIG. 2B), and the first groove is formed.
Forming a conductor layer (9 in FIG. 2B) in the concave groove (11a) of the semiconductor wafer (11) of FIG.
A wiring layer (14 in FIG. 2B) is formed on the surface of 1) to form a global wiring layer (8 in FIG. 2B), and a second semiconductor wafer (1 in FIG. 3B) is produced. A semiconductor circuit (Fig. 3
2 to 6) of (b) are formed to form an LSI cell portion (FIG. 3B).
7) is manufactured and a global wiring layer (8 in FIG. 6A) is manufactured.
Wiring layer (14 in FIG. 6A) and the LSI cell portion (FIG. 6A).
The semiconductor circuit (7) in (a) and the semiconductor circuit (2 to 6 in FIG. 6A) are made to face each other and bonded to each other to form a global wiring layer (FIG. 6B).
8), the first semiconductor wafer (11 in FIG. 6B) is removed to remove the conductor layer (FIG. 6B) in the groove (11a in FIG. 6B).
The purpose is to expose 9) in (b) and use it as an external connection terminal (9a in FIG. 6D) of the LSI cell portion (7 in FIG. 6D).

By adopting such a method, according to the method of manufacturing a semiconductor device of the present invention, the external connection terminals can be formed with a fine pitch and high precision.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. Hereinafter, it is assumed that each cross-sectional view is a cross-sectional view seen from the same position as the line I-I in FIG. In addition, since the structure of each cross-sectional view is quite fine, to avoid making it difficult to read,
Hatching is not intentionally added to each sectional view.

FIG. 1A is a plan view of a system LSI 10 according to an embodiment of the present invention, and FIG. 1B is a sectional view taken along line I-I.

FIG. 2A is a plan view of the global wiring layer 8 in the system LSI 10 according to the embodiment of the present invention, and FIG. 2B is a sectional view taken along the line II-II.

FIG. 3A is a plan view of the system LSI cell portion 7 in the system LSI 10 according to the embodiment of the present invention, and FIG. 3B is a sectional view taken along line III-III.

System LSI shown in FIGS. 1 (a) and 1 (b)
10 is the global wiring layer 8 shown in FIGS.
3A and 3B, the system LSI cell unit 7 shown in FIGS.
It is composed by turning over and pasting.

The global wiring layer 8 shown in FIGS. 2A and 2B includes a conductor layer 9 that will eventually become the external connection terminal 9a.
Silicon wafer 11, first insulating layer 13, first wiring layer 14, second insulating layer 15, and first bonding pad 1
6 to electrically connect the functional block circuits 2 to 6 on the system LSI cell section 7 to an external circuit via the external connection terminal 9a.

The silicon wafer 11 is a wafer made of semiconductor silicon. Although the silicon wafer 1 is realized by silicon, any semiconductor material other than this may be used.

The first insulating layer 13 is a silicon wafer 11
Is formed by depositing an insulating material on the surface of the pad 2a.
To 6a are electrically insulated from the first wiring layer 14. Vias 13a for electrically connecting the pads 2a to 6a and the first wiring layer 14 are formed at specific positions of the first insulating layer 13 by a selective CVD method, metal plating, a conductive paste, or the like.

The first wiring layer 14 is formed by depositing a conductive material such as various metals in a specific pattern on the surface of the first insulating layer 13 by sputtering.
a and the via 15a are electrically connected.

The second insulating layer 15 is formed by depositing an insulating material on the surface of the first wiring layer 14, and electrically connects the first wiring layer 14 and the first bonding pad 16 to each other. Insulate to. The first wiring layer 14 is provided at a specific position of the second insulating layer 15.
15a for electrically connecting the first bonding pad 16 and the first bonding pad 16
Are formed by a selective CVD method, metal plating, conductive paste, or the like.

The first bonding pad 16 is the second insulating layer 1
The surface of the via 5 is formed by sputtering a conductive material such as various metals in a specific pattern shape.
a is physically and electrically connected to the second bonding pad 26 of the system LSI cell section 7 (FIG. 3).

System LSI shown in FIGS. 3A and 3B
The cell unit 7 includes a silicon wafer 1 and functional blocks 2 to 6.
And a third insulating layer 23, a second wiring layer 24, a fourth insulating layer 25, and a second bonding pad 26.

The silicon wafer 1 is a wafer made of semiconductor silicon. Although the silicon wafer 1 is realized by silicon, any semiconductor material other than this may be used.

Each of the functional block circuits 2 to 6 is a unit circuit that realizes a specific function as a memory, a microcomputer, or the like, and undergoes pattern formation, ion implantation, stepper processing, etc. on the surface of the silicon wafer 1. After being respectively formed, the pads 2a to 6 to be electrodes are formed by sputtering metal such as Au at specific positions on the surface thereof.
a is formed.

The third insulating layer 23 is formed by depositing an insulating material on regions other than the pads 2a to 6a on the surface of the silicon wafer 1, and the pads 2a to 6a and the second wiring layer 24 are formed.
To electrically insulate.

The second wiring layer 24 is formed by depositing a conductive material such as various metals on the surface of the silicon wafer 1 in a specific pattern by sputtering or the like.
a to 6a and the via 25a are electrically connected.

The fourth insulating layer 25 is formed by depositing an insulating material on the surface of the second wiring layer 24, and electrically connects the second wiring layer 24 and the second bonding pad 26. Insulate to. The second wiring layer 24 is provided at a specific position of the fourth insulating layer 25.
25a for electrically connecting the second bonding pad 26 with the second bonding pad 26
Are formed by a selective CVD method, metal plating, conductive paste, or the like.

The second bonding pad 26 is made up of the fourth insulating layer 2
5 is formed by sputtering a conductive material such as various metals in a specific pattern shape on the surface of 5.
a and the first bonding pad 1 of the global wiring layer 8 (FIG. 2)
6 and 6 are connected physically and electrically.

Although Al, Al alloy, Cu, Cu alloy or the like is used for the first and second wiring layers 14 and 24, any conductive material other than this may be used.

Similarly, the first to fourth insulating layers 13, 15, 2
A silicon oxide film, a silicon nitride film, polyimide, or the like is used for 3, 25, but other than this, any insulating material may be used.

Similarly, for the vias 13a, 15a, 25a, a conductive metal such as Cu is formed on the inner surface of the vias 13a, 15a, 25a by a selective CVD method or a conductive metal such as Cu is formed by plating. It is formed by a method of filling the vias 13a, 15a, 25a with a conductive paste mixed with metal powder and curing the same, but other than this, the conductive paste may be formed by an arbitrary method. Is also good.

Similarly, the first and second bonding pads 16, 26
Although Au or the like is used for this, any conductive material other than this may be used.

Next, the system LSI of the embodiment of the present invention
The manufacturing method of 10 will be described.

FIG. 4A is a front sectional view showing the first step of the global wiring layer 8 in the method of manufacturing the system LSI 10 according to the embodiment of the present invention, and FIG. 4B is a front sectional view showing the second step. 4C is a front sectional view showing a third step, FIG.
4D is a front sectional view showing the fourth step, FIG. 4E is a front sectional view showing the fifth step, FIG. 4F is a front sectional view showing the sixth step, and FIG. Front sectional view showing 7 steps, FIG.
[Fig. 11A] is a sectional view showing the eighth step.

The surface of the silicon wafer 11 shown in FIG. 4A is wet-etched after developing and exposing the pattern of the external connection terminals 9a by photolithography or the like as shown in FIG. 4B. The concave groove 11a is formed according to the pattern of the external connection terminal 9a.

Next, as shown in FIG. 4 (c), selective CVD
The conductor layer 9 is formed on the entire surface of the silicon wafer 11 by the method or metal plating method.

Next, as shown in FIG. 4D, the conductor layer 9 and the silicon wafer 11 are polished from the surface of the conductor layer 9 by using a lathe or the like, and the conductor layer 9 is provided only at the positions where the external connection terminals 9a are provided. Leave.

Next, as shown in FIG. 4 (e), after depositing the first insulating layer 13 on the surface of the conductor layer 9, the first insulating layer 13 is applied to a specific portion of the first insulating layer 13. A via 13a penetrating the insulating layer 13 to electrically connect the conductor layer 9 and the first wiring layer 14 to each other is formed.

Next, as shown in FIG. 4F, a conductive material such as Cu is sputtered on the surface of the first insulating layer 13, exposed and developed, and patterned into a specific shape to form the first wiring layer 14. To form.

Next, as shown in FIG. 4 (g), after the second insulating layer 15 is deposited on the surface of the first wiring layer 14, the second insulating layer 15 is provided with the second insulating layer 15 at a specific position. Second insulating layer 15
A via 15a that penetrates through the first wiring layer 14 and electrically connects the first bonding pad 16 to each other is formed.

Finally, as shown in FIG. 4H, the via 15
Sputtering a conductive material such as Au on the surface of a,
The global wiring layer 8 is completed by exposing and developing and patterning to form the first bonding pad 16.

FIG. 5A is a front sectional view showing the first step of the system LSI cell portion 7 in the method of manufacturing the system LSI 10 of the embodiment of the present invention, and FIG. 5B is a front sectional view showing the second step. FIG. 5C is a front sectional view showing the third step,
5D is a front sectional view showing the fourth step, FIG. 5E is a front sectional view showing the fifth step, FIG. 5F is a front sectional view showing the sixth step, and FIG. [Fig. 11] is a front cross-sectional view showing a seventh step.

The surface of the silicon wafer 1 shown in FIG. 5A is subjected to processing such as pattern formation, ion implantation, stepper processing, etc., as shown in FIG.
To form.

Next, as shown in FIG. 5C, a pad 2 which becomes an electrode by depositing a conductive material such as Au on a specific portion of the surface of the functional block circuits 2 to 6 by sputtering or the like.
a to 6a are formed.

Next, as shown in FIG. 5D, the silicon wafer 1 and the pads 2a to 6a of the functional block circuits 2 to 6 are formed.
The third insulating layer 23 is formed by depositing an insulating material on the surface of the region where the is not formed.

Next, as shown in FIG. 5E, a second wiring layer 24 is formed on the surface of the third insulating layer 23 by sputtering a conductive material into a specific shape.

Next, as shown in FIG. 5 (f), an insulating material is deposited on the surface of the second wiring layer 24 to form a fourth insulating layer 25, and then the fourth insulating layer 25 is formed. A via 25a is formed in a specific portion to penetrate the fourth insulating layer 25 and electrically connect the second wiring layer 24 and the second bonding pad 26.

Finally, as shown in FIG. 5G, the via 25
The system LSI cell portion 7 is completed by sputtering the conductive material on the surface of a to form the second bonding pad 26.

FIG. 6A is a front sectional view showing the first step of the method for manufacturing the system LSI 10 according to the embodiment of the present invention, FIG. 6B is a front sectional view showing the second step, and FIG. ) Is the third
FIG. 6D is a front sectional view showing the fourth step.

As shown in FIG. 6A, the system LSI cell unit 7 of FIG. 5G is turned over and transferred onto the global wiring layer 8 of FIG. 4H placed on a stage (not shown). Then, the first bonding pad 16 of the global wiring layer 8 and the second bonding pad 26 of the system LSI cell portion 7 are aligned so as to face each other by using a position confirmation means such as an imaging camera (not shown).

Next, as shown in FIG. 6 (b), the global wiring layer 8 and the system LSI cell portion 7 are overlapped with each other and pressed and heated from above and below.

Then, the first bonding pad 16 and the second bonding pad 26 are bonded to each other and are physically and electrically connected to each other.

Next, as shown in FIG. 6C, a silicon wafer 11 is formed from below the global wiring layer 8 using a lathe or the like.
Are polished to expose the conductor layer 9 on the surface.

Finally, as shown in FIG. 6D, the system wafer 10 is completed by completely removing the silicon wafer 11 by wet etching or the like to expose the entire conductor layer 9 on the surface. That is, each exposed conductor layer 9 becomes an external connection terminal 9a.

As described above, in the present embodiment, a processing method capable of fine processing such as photolithography and etching can be applied when forming the external connection terminal 9a of the system LSI 10. It becomes possible to manufacture finely and with high precision.

In the above-described embodiment, the method of manufacturing the system LSI 10 on a chip basis has been described in order to make the description easy to understand. However, a large number of global wiring layers 8 are continuously formed on a silicon wafer 11 on a plane, and silicon is formed. Wafer 1
A large number of system LSI cell parts 7 are continuously formed on a flat surface, and these silicon wafers 11 and 1 are bonded to each other to manufacture them as in the above-described embodiment, and then these are formed in each system L.
A large number of system LSIs 10 may be manufactured by dicing each SI 10 to separate them.

On the contrary, a large number of silicon wafers 11 and 1 are prepared in advance by dicing each of the silicon wafers 11 and 1 by dicing into chips, and the plurality of silicon wafers 11 and 1 of the above-described embodiment are formed on these silicon wafers 11 and 1. As described above, the global wiring layer 8 and the system LSI cell portion 7 may be respectively formed and bonded to each other to manufacture a large number of system LSIs 10.

In the above embodiment, the wiring layer 1 is formed in both the global wiring layer 8 and the system LSI cell section 7.
Although the layers 4, 24 and the insulating layers 13, 15, 23, 25 are formed, they may be formed on at least one of them.

Further, although the global wiring layer 8 and the system system LSI cell portion 7 are directly joined via the first bonding pads 16 and 26, the global wiring layer 8 and the system system LSI cell portion 7 are connected to each other. An adhesive such as a thermosetting resin or a photocurable resin may be supplied, cured, and bonded.

[0061]

By adopting the methods and means described above, the method for manufacturing a semiconductor device of the present invention exhibits the following effects.

The first point is that the external connection terminals can be manufactured with a very fine pitch and with extremely high precision, and the semiconductor device can be mounted at a higher density. The reason is that a processing method capable of fine processing such as photolithography or etching can be applied when forming the external connection terminal.

As a second point, there is an advantage that the external connection terminals can be formed in an arbitrary shape and the degree of freedom is high. The reason is that a processing method having a high degree of freedom in shape such as photolithography or etching can be applied when forming the external connection terminal.

[Brief description of drawings]

FIG. 1A is a system LSI according to an embodiment of the present invention.
10 is a plan view, and FIG. 10B is a sectional view taken along line I-I.

FIG. 2A is a system LSI according to an embodiment of the present invention.
10 is a plan view of the global wiring layer 8 in FIG.
It is an I-II line front sectional view.

FIG. 3A is a system LSI according to an embodiment of the present invention.
10 is a plan view of the system LSI cell unit 7 in FIG.
Is a front sectional view taken along line III-III.

FIG. 4A is a system LSI according to an embodiment of the present invention.
10 is a front sectional view showing the first step of the global wiring layer 8 in the manufacturing method of FIG. 10, (b) is a front sectional view showing the second step,
(C) is a front sectional view showing a third step, (d) is a front sectional view showing a fourth step, (e) is a front sectional view showing a fifth step,
(F) is a front sectional view showing a sixth step, (g) is a front sectional view showing a seventh step, and (h) is a front sectional view showing an eighth step.

FIG. 5A is a system LSI according to an embodiment of the present invention.
1 of the system LSI cell unit 7 in the manufacturing method 10
A front sectional view showing a step, (b) a front sectional view showing a second step, (c) a front sectional view showing a third step, (d) a front sectional view showing a fourth step, (e) showing A front sectional view showing a fifth step,
(F) is a front sectional view showing a sixth step, and (g) is a front sectional view showing a seventh step.

FIG. 6A is a system LSI according to an embodiment of the present invention.
10 is a front sectional view showing a first step of the system LSI 10 in the manufacturing method of FIG. 10, (b) is a front sectional view showing a second step,
(C) is a front sectional view showing a third step, and (d) is a front sectional view showing a fourth step.

[Simple explanation of symbols]

1 Silicon wafer 2-6 Function block circuit 7 System LSI cell section 8 Global wiring layer 9 Conductor layer 10 system LSI 11 Silicon wafer 13 First insulating layer 14 First wiring layer 15 Second insulating layer 16 First bonding pad 23 Third insulating layer 24 Second wiring layer 25 Fourth insulating layer 26 Second bonding pad

Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/3205 H01L 21/768 H01L 27/04 H01L 21/822 H01L 27/00

Claims (11)

(57) [Claims] 1. A concave groove having a specific pattern is formed on the surface of a first semiconductor wafer, a conductor layer is formed in the concave groove of the first semiconductor wafer, and wiring is formed on the surface of the first semiconductor wafer. A layer to form a global wiring layer, a semiconductor circuit is formed on the second semiconductor wafer to form an LSI cell portion, the wiring layer of the global wiring layer and the semiconductor circuit of the LSI cell portion Facing each other and bonded to each other, and removing the first semiconductor wafer of the global wiring layer to expose the conductor layer in the groove to serve as an external connection terminal of the LSI cell portion. Manufacturing method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein an etching process is performed when forming a groove having a specific pattern on the surface of the first semiconductor wafer. 3. The method of manufacturing a semiconductor device according to claim 1, wherein an etching process is performed when a conductor layer is formed in the groove of the first semiconductor wafer. . 4. The method according to claim 1, wherein, when a conductor layer is formed in the groove of the first semiconductor wafer, the conductor layer is polished and then etched. Manufacturing method of semiconductor device. 5. The etching process is performed when the first semiconductor wafer of the global wiring layer is removed to expose the conductor layer in the groove.
A method for manufacturing a semiconductor device according to any one of 1. 6. The etching process after the polishing process when the first semiconductor wafer of the global wiring layer is removed to expose the conductor layer in the groove. 5. The method for manufacturing a semiconductor device according to any one of 4 above. 7. The method of manufacturing a semiconductor device according to claim 1, wherein another wiring layer is further formed on the surface of the LSI cell portion. 8. The global wiring layer and the system L
The method for manufacturing a semiconductor device according to claim 1, wherein the SI cell portion is connected via a bonding pad. 9. The global wiring layer and the system L
8. The method for manufacturing a semiconductor device according to claim 1, wherein the SI cell portion is connected via an adhesive layer. 10. The global wiring layer and the LSI cell portion are manufactured by respectively manufacturing and pasting on a semiconductor wafer, and then cut into chips. Of manufacturing a semiconductor device of. 11. The global wiring layer and the LSI cell portion are manufactured by cutting a semiconductor wafer into chips in advance and then forming and bonding the chips on the separated chips, respectively. Claims 1-9
A method for manufacturing a semiconductor device as described above.