JP3496807B2 - Thermopile manufacturing method and structure - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to boron B (Boron)
TECHNICAL FIELD The present invention relates to a method and structure for manufacturing a thermopile using silicon formed by diffusing impurities such as phosphorus (P) and phosphorus (Phosphorous) into a Si (Silicon) substrate, and in particular, diffusing impurities to form a wiring thermopile contact. The present invention relates to a technique for accurately and easily producing a patterned shape of a Si layer.

[0002]

2. Description of the Related Art Conventionally, there are various types of thermopiles using Si in which impurities are diffused. Here, as an example, silicon (hereinafter referred to as silicon) in which boron B is highly diffused when used in a flow sensor is used. , P ^++- Si)
The thermopile using is explained.

In the thermopile, a plurality of thermocouples made of two kinds of materials, a silicon p ^++- Si layer formed by diffusing boron B or the like in a Si substrate at a high concentration and a metal thin film, are formed. A thermocouple group is formed by connecting each of these individual thermocouples.

The hot junction of the thermocouple group is formed on a thin diaphragm, and the cold junction is formed on the Si substrate side. This diaphragm is formed by using an insulating film as a substrate, a metal thin film wiring is formed on the front side of the diaphragm, and a p ^++- Si wiring is formed on the back side of the diaphragm, and a hot junction is formed by conducting the front and back sides. With such a configuration, due to the temperature difference between the hot junction and the cold junction,
Thermo-electromotive force is generated in the thermopile by the Seebeck effect.

Next, a part of the process for forming the thermopile will be described. FIG. 5 shows a process of forming the p ^++- Si wiring on the Si substrate 62. First, Fig. 5 (a)
At, the SiO ₂ film 72 is formed by oxidizing the front and back surfaces of the Si substrate 62. Next, in FIG. 5B, a window 73 is formed by masking by photolithography according to the desired shape of the p ^++- Si wiring, and then performing etching to selectively remove the SiO ₂ film 72.
To form. Then, from the upper surface of the Si substrate 62, the Si substrate 6
P ^{+ +} -S
The i layer 74 is formed.

[0006]

[Problems to be Solved by the Invention]
In thermopile, p⁺⁺-Si layer 74 is a Si substrate
In the process of forming on 62, as shown in FIG.
Sea urchin p⁺⁺-The boundary between the Si layer 74 and the Si substrate 62 is clear
Moreover, the diffusion of boron B is not limited to the depth direction.
Since it also extends laterally, it is adjacent to the point M as shown in Fig. 5 (c).
Contact p⁺⁺-Diffusion parts from the -Si layer 74 may intersect.
It Thus, the p formed at the adjacent position ⁺⁺-Si layer 7
When 4 intersect each other, an electrical leak occurs at the point M,
There is a problem that the function as a thermocouple cannot be fulfilled.
It Therefore, adjacent p⁺⁺-Set the spacing δ between Si layers to be wide
If this is done, the above problem will be solved, but this interval δ will be increased.
To do this, close the contact intervals of the thermopile hot junctions.
To increase contact density and increase thermopile output.
It will be contrary to the request.

Further, p ⁺⁺ -Si is not always dissolved in an etching solution, and in particular, the p ⁺⁺ -Si surface on which the SiO ₂ film is formed after the high concentration diffusion of impurities has a relatively high etching rate. Since it is fast, it will dissolve if it is etched for a long time. This phenomenon is caused by the p ⁺⁺ − generated SiO ₂ film.
It is considered that the Si surface is caused because the impurity concentration on the surface side is lowered due to the movement of impurities in Si. Further, the etching rate has a characteristic that the side surface of the p ^++- Si layer is relatively fast. Therefore, for example, in FIG.
On the Si substrate 51 on which the p ^++- Si layer 81 shown in FIG.
In the structure of p ⁺⁺ -Si in which the SiO ₂ film 82 is formed and the electric contact 81a with the metal thin film 83 is formed (that is, the structure of the hot junction shown in FIG. 3 described later), the etching for removing the Si substrate 51 is performed. Sometimes p ^++- Si layer 81 upper surface 81a
And the side surface 81b are melted for the above reason, and finally, as shown in FIG.
As shown in (b), there arises a problem that the electrical contact 81a is disconnected.

In order to prevent the occurrence of such a problem, it is necessary to properly and accurately select and adjust various conditions such as an impurity diffusion depth, a pattern line width, an etching solution type, an etching time and an etching temperature. is there. However, these settings are delicate, and always adjusting them accurately complicates the process, resulting in an increase in cost.

The present invention has been made in view of the above-mentioned problems, and p ^{+ +} -Si diffused with impurities can be simply and accurately formed into a desired shape, and the contact density of the thermocouple of the thermopile can be improved. It is an object to provide a method for producing a thermopile that can be increased, and a structure thereof.

[0010]

In order to achieve the above object, the present invention provides a thermopile in which wiring and electrodes are formed on a diaphragm by selectively performing diffusion, film formation, and etching on a Si substrate. In the manufacturing method, impurities are diffused on the surface of the Si substrate by diffusing impurities.
A layer is formed, the surface of the impurity-diffused Si layer is masked with a desired pattern and selectively removed by a dry etching method, and a side surface of the removed portion of the impurity-diffused Si layer removed by the dry etching method is included. Si by forming the etch stop film on the substrate surface, and to prevent the dissolution of the side surface of the impurity diffusion Si layer during the etching of the Si substrate. Thus, since the impurity-diffused Si layer is removed in a substantially vertical direction by dry etching to form the wiring and electrode patterns, a fine pattern can be accurately manufactured. In addition, by surrounding the side surface of the removed impurity diffusion Si layer with an etch stop film,
It is possible to prevent the side surface of the removed portion of the impurity diffusion Si layer and the contact surface with the etch stop film such as the SiO2 film from being excessively dissolved during the etching of the Si substrate such as when manufacturing the diaphragm, so that the desired wiring and electrode shape can be obtained. It can be processed with high precision.

Further, it is preferable that the pattern includes a hot junction of a thermocouple. Thus, the output of the thermopile can be improved by miniaturizing the hot junctions of the thermocouple and increasing the contact density without causing a short circuit in the wiring or a variation in the resistance value.

The above object can be achieved by the structure of the thermopile produced by any one of the above production methods. As described above, the structure of the thermopile using the silicon p ^++- Si in which the impurities are diffused can be manufactured with high accuracy by a simple process, and the function of the thermopile can be stably and more reliably exhibited. .

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, the structure of a thermopile according to an embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 is a plan view of a flow velocity sensor according to the embodiment of the present invention. The flow velocity sensor 1 includes a Si substrate 2 which is a support substrate,
A thin diaphragm 3 composed of a SiO ₂ film and a Si ₃ N ₄ film, a micro-heater 4 formed on the diaphragm 3 for heating a fluid substance, and a diaphragm 3 on the downstream side of the micro-heater 4 in the fluid flow, Downstream thermopile 5 formed excluding the cold junction forming portion on the reference temperature side
A power supply wiring 6 for supplying a driving current to the micro-heater 4 and output terminals 7a, 7b.
And the first output wiring 7 for outputting the signal output from the downstream side thermopile 5 to the outside through the output terminals 7a and 7b.
And an upstream side thermopile 8 formed on the diaphragm 3 except the cold junction forming portion and output terminals 9a and 9b on the upstream side of the microheater 4, and the upstream side thermopile 8
A second output wiring 9 for outputting the signal output from the output terminal 9a, 9b to the outside through the output terminal 9a, 9b.

In this flow velocity sensor, the upstream side thermopile 8 and the downstream side thermopile 5 have the same structure, so the downstream side thermopile 5 will be described. Next, a detailed configuration of the thermosensitive portion of the thermopile will be described. 2 is an enlarged plan view conceptually showing the structure of the thermopile, and FIG. 3 is a sectional view of the thermopile. As shown in FIG. 2, the thermopile has p ⁺⁺ -Si wiring formed by diffusing boron B in a Si substrate at a high concentration and Al thin film wiring formed by a vacuum deposition method or the like at the wiring end portions, respectively. A plurality of thermocouples are formed by electrically connecting to form the cold junction 5a and the hot junction 5b.

Further, as shown in FIG. 3, the thermopile 5
The cold junction 5a, which is the ambient temperature detection side, is provided in a portion of the Si substrate 2 (thickness: about 400 μm) where the diaphragm 3 is not formed, and the hot junction 5b, which is the temperature detection side of the thermopile 5, is made of SiO ₂ film and It is provided on the diaphragm 3 (thickness: about 1 μm) composed of a Si ₃ N ₄ film. Next, a thermopile manufacturing process will be described with reference to FIG. FIG. 4 shows a cross section taken along the line AA ′ shown in FIG. First, as shown in FIG. 4A, the p ⁺ -Si layer 10 is formed by diffusing a high concentration of boron B, which is a p-type impurity, into the Si substrate 2 by an ion implantation method or a thermal diffusion method.
To form. Next, as shown in FIG. 4B, the opening 11a is formed in the resist layer 11 on the upper surface of the p ^++- Si layer 10 by the photolithography method at the contact intervals of the hot contacts 5b shown in FIG.
To form.

Then, as shown in FIG.
Reactive ion etching (RI
E; Reactive Ion Etching) method, etc.
The p ^++- Si layer 10 below 1a is removed in a substantially vertical direction.
This etching is controlled to be terminated when the thickness of the p ^++- Si layer 10 is removed by time control.
By this process, the p ^++- Si layer 10 is directly formed into a desired pattern.

Next, the resist layer 1 on the p ^++- Si layer 10 is formed.
After removing 1, the desired pattern was formed on the surface p
^{+ +} -Si layer 10 and the exposed surface of Si substrate 2 and the back surface of Si substrate 2 are both oxidized by heat treatment or the like to form a SiO ₂ film, and further Si ₃ N ₄ film is subjected to CVD or the like. Formed by. Thereby, Si ₃ N ₄ / SiO ₂ 12 is formed. In addition, this Si ₃ N ₄ / SiO ₂ 12 is SiO ₂
Film, or it may be a single layer of _{Si 3 N 4, Si 3 N} 4 / S
SiO ₂ / S is further formed an SiO ₂ film on the upper surface of the iO ₂
It may be i ₃ N ₄ / SiO ₂ . The above Si ₃ N ₄ / Si
Since O ₂ 12 has a characteristic that the etching rate is significantly lower than that of Si, O ₂ 12 can selectively etch the Si substrate 2.

Next, as shown in FIG. 4E, resist layers 13 are formed on both upper and lower surfaces of the Si substrate 2. The upper surface of the substrate is exposed by forming a mask corresponding to the contact hole 13a, and the lower surface of the substrate is exposed by forming a mask corresponding to the diaphragm. Then, as shown in FIG. 4 (f), the upper surface of the substrate is covered with Si ₃ N _{4 in the} contact hole 13a.
/ SiO ₂ 12 is removed, and the Si ₃ N ₄ / SiO ₂ layer other than the diaphragm portion is removed from the lower surface of the substrate.

Then, as shown in FIG. 4 (g), an Al thin film 14 for wiring is formed by a vacuum deposition method or the like, and an unnecessary Al thin film is removed by photolithography and etching, leaving only the wiring portion. Although not shown, a thermopile electrode made of a Pt thin film is similarly formed by, for example, a vacuum vapor deposition method.

Further, with respect to the lower side of the Si substrate 2, Si
_The diaphragm 3 is formed by performing anisotropic etching from the lower side of the substrate using ₃ N ₄ / SiO ₂ as a mask to form a recess.
To form.

The anisotropic etching is, for example, hydrazine, TMAH (Tetra Methyl Ammonium Hydride),
An anisotropic etching agent such as potassium hydroxide (KOH) is used. These etching agents have the property of selectively etching the (100) plane of Si and exposing the (111) plane. Therefore, when performing such anisotropic etching, a Si wafer having a (100) plane is used. In addition, these etching agents have a high concentration of p ⁺⁺ -S.
The etch stop acts on i, and the p ^++- Si layer formed in the previous step remains without being removed. In the present embodiment, the p ^++- Si layer 10 is Si as an etch stop film.
_Since it is surrounded by ₃ N ₄ / SiO ₂ 12,
Dissolution of the low-concentration p ⁺ -Si portion and the side surface that are partially present is reliably prevented.

The etching treatment is not limited to anisotropic etching, and any etching method that causes an etch stop may be used. Also, as described above, not from the bottom side of the substrate,
By injecting an anisotropic etching agent from the upper side of the substrate and performing etching, the Si substrate 2 can be undercut to form the diaphragm 3 as shown in FIG. 4 (i). The thermopile 5 is formed by the above process. The thermopile 8 is also formed in the same manner. Incidentally, a SiO ₂ film or the like may be formed on the surface of the Si substrate 2 as a protective layer for preventing damage from the outside.

The method for producing a thermopile according to the present embodiment
According to Si₃N_Four/ SiO₂12 is p⁺⁺-Si layer 10
Since it is formed by surrounding the side surface of the
The side that is relatively fast is reliably protected, even if it is an etch
P ⁺⁺-Si layer 10 is removed
It can be prevented from leaving. For this reason
Pattern can be accurately formed, and
Easier to manage touch time, simplifying the process
The cost can be reduced. And this
The yield can be improved.

Further, in the present manufacturing method, p ⁺⁺ − is formed by the conventional method of diffusing the impurities only in the selected region.
As in the case of forming the Si layer 10, p ^++- Si having a shape according to the mask pattern due to the influence of diffusion other than the depth direction.
There is no regulation that a layer cannot be obtained or that the distance between adjacent mask holes is set to a predetermined distance or more to avoid this. Therefore, the pattern of the p ^++- Si layer can be miniaturized to the limit of the processing accuracy of the lithography technique and the dry etching technique. As a result, it is possible to shorten the contact interval of the thermocouple contacts of the thermopile without causing a short circuit of the wiring or a variation in the resistance value due to the diffusion state of impurities, etc., and increase the contact density of the thermocouple to increase the thermopile contact density. The output can be increased. Further, by miniaturizing the wiring and electrode pattern of the thermopile, the thermopile can be further downsized, and the application range of the thermopile itself can be further expanded.

Although the thermopile used for the flow velocity sensor has been described as an example of the thermopile as described above, the method for producing the thermopile according to the present invention is as follows.
The present invention is not limited to the flow velocity sensor of the above embodiment, and can be applied to, for example, a thermopile used for each sensor such as a flow sensor, an infrared sensor, and a gas sensor, and also to any other impurity-diffused silicon structure. Applicable. Further, the impurity-diffused Si layer in which the p-type impurity is diffused may be a layer in which an n-type impurity such as phosphorus P is diffused. Even in the case of n-type impurities, the same action and effect are obtained by the same process as above.

[0026]

According to the present invention, diffusion on a Si substrate,
In a method for manufacturing a thermopile in which wiring and electrodes are formed on a diaphragm by selectively performing film formation and etching, an impurity diffused Si layer is formed by diffusing impurities on the surface of a Si substrate, and the impurity diffused Si layer is formed. The surface of the mask is masked with a desired pattern and selectively removed by a dry etching method, and an etch stop film is formed on the Si substrate surface including the side surface of the removed portion of the impurity diffusion Si layer removed by the dry etching method. Therefore, the Si
The side surface of the impurity-diffused Si layer is prevented from being melted when the substrate is etched. As a result, the impurity diffusion S in the substantially vertical direction is performed.
Since the i layer is removed to form the wiring and the electrode pattern, a fine pattern can be accurately manufactured with high accuracy. Also, by including the side surface of the removed portion of the removed impurity diffused Si layer with the etch stop film, the side surface of the removed portion of the impurity diffused Si layer and the contact with the etch stop film such as a SiO2 film are formed at the time of manufacturing a diaphragm. The surface can be prevented from being excessively melted, and the desired wiring and electrode shapes can be accurately processed.

Further, the thermopile wiring and the electrode pattern can be accurately formed by a simple process without depending on the diffusion depth of impurities, and short-circuiting of the thermopile wiring and variation in the resistance value between contacts can be prevented. It is possible to further shorten the distance between the thermocouple contacts, especially the hot contacts. Therefore, the contact density of the thermopile is increased, and the output of the thermopile can be increased.

Even with a relatively simple semiconductor manufacturing apparatus, the manufacturing method according to the present invention can be easily applied, and the above effects can be obtained in the same manner. Furthermore, since the process of providing a mask for impurity diffusion is unnecessary, the procedure for producing the thermopile can be simplified and the production time can be further shortened.

[Brief description of drawings]

FIG. 1 is a plan view showing a structure of a thermopile according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a conceptual configuration of a thermopile thermocouple.

FIG. 3 is a cross-sectional view showing a configuration of a vertical cross section of the thermopile.

FIG. 4 is an explanatory diagram of a thermopile manufacturing process of the present invention.

FIG. 5 is an explanatory view showing a part of a conventional thermopile manufacturing process.

FIG. 6 is a cross-sectional view showing a state of a contact portion of a conventional thermopile.

[Explanation of Codes] 1 Flow Rate Sensor 2 Si Substrate 3 Diaphragm 5 Downstream Thermopile 5a Cold Junction 5b Hot Junction 8 Upstream Thermopile 10 p ^++- Si Thin Film 14 Al Thin Film

Claims (3)

(57) [Claims] 1. A method for producing a thermopile in which wiring and electrodes are formed on a diaphragm by selectively performing diffusion, film formation and etching treatment on a Si substrate, wherein impurities are diffused by diffusing impurities on the surface of the Si substrate. A Si layer is formed, the surface of the impurity diffused Si layer is masked with a desired pattern and selectively removed by a dry etching method, and the side surface of the removed portion of the impurity diffused Si layer removed by the dry etching method is removed. A method for producing a thermopile, comprising forming an etch stop film on a surface of an Si substrate including the layer to prevent dissolution of a side surface of the impurity diffusion Si layer during etching of the Si substrate. 2. The method for producing a thermopile according to claim 1, wherein the pattern includes a hot junction of a thermocouple. 3. A thermopile structure formed by the method for producing a thermopile according to claim 1 or 2.