JP3501804B2 - Laser gyro direct dither drive - Google Patents

Description

The present invention relates generally to laser gyros, and more particularly to methods and apparatus for directly digitally driving a laser gyro dither motor using a microcontroller in a closed loop system.

BACKGROUND OF THE INVENTION Laser angular velocity sensors, often called laser gyros, are well known. An example of a laser angular velocity sensor is Ha, which is incorporated herein by reference.
U.S. Pat. No. 4,751,718 issued to Nse et al. Today's laser angular velocity sensors include a thermally stable and mechanically stable laser block with a plurality of cavities formed to surround the void. At both ends of the cavity,
A mirror is arranged that reflects the laser beam and forms a closed loop optical path.

In connection with such sensors, there is an undesirable phenomenon known as lock-in, which has heretofore been recognized in the prior art. The prior art has dealt with the lock-in phenomenon by rotationally oscillating such a sensor, i.e. by dithering. Rotational vibrations are typically supported by dither motors. The conventional dither motor is
It typically has a suspension system that includes, for example, an outer rim, a central hub member, and a plurality of dither motor leads that project radially from the hub member and are coupled between the hub member and the rim. Traditionally, a set of piezoelectric elements that act as actuators have been coupled to a suspension system. When actuated by applying an electrical signal to the piezoelectric element, the suspension system acts as a dither motor, so that the block of sensors angularly vibrates at the natural mechanical resonance frequency of the suspension system. This dither motion is superimposed on the inertial rotation of the sensor in inertial space. Such dither motors may be used in connection with a single laser gyro, or may be used to dither multiple laser gyros. The prior art includes various schemes for recovering dither-free inertial rotation data.

SUMMARY OF THE INVENTION The present invention provides a direct digital dither driver for a laser gyro. The direct digital drive of the present invention comprises a low pass filter having at least three poles, a high pass filter having at least two poles, an output for providing a filtered signal, and an input for connecting to a pulse width modulated digital drive signal. And. The direct digital driver further comprises an amplifier coupled at the input side to the output of the low pass filter and amplifying the filtered signal from the low pass filter, the means for driving the dither motor in response to the amplified signal is Active pull-up means coupled to the output, the driving means including means for substantially eliminating current spikes in the power supply signal and providing dead zone operating characteristics to form a highly efficient driver with low power consumption. including.

One objective of the present invention is from 0% duty cycle
It is to provide a dither motor drive means that provides an output in the range of +150 to -150 volts in response to a pulse width modulated input over a range of 100% duty cycle.

Another object of the invention is to provide an improved dither driver circuit that consumes power only during the transitions of the pulse width modulated signal input.

Yet another object of the present invention is to provide an improved dither drive circuit that consumes a small amount of power when the capacitive drive load of the dither motor reaches steady state.

Other objects, features and advantages of the invention will be apparent to those skilled in the art from the description of the preferred embodiments, the claims and the drawings. In the drawings, the same reference numerals indicate the same elements.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 shows a block diagram of one embodiment of a laser gyro employing the novel features of the present invention.

FIG. 2 schematically shows a circuit diagram of an example of a dither pickoff circuit constructed according to the present invention.

FIG. 3 schematically illustrates a circuit diagram of one embodiment of a direct digital dither driver circuit provided by one aspect of the present invention.

FIG. 4 shows a detailed schematic diagram of another embodiment of a dither driver circuit provided in accordance with one aspect of the present invention.

FIG. 5 shows a high level schematic block diagram of a direct dither driver used in a laser gyro including a closed loop system.

FIG. 6 shows an interrupt timing diagram as a function of the output of the zero-crossing detector.

FIG. 7 shows a method for determining the 90 ° and 270 ° intersections of the dither cycle.

FIG. 8 shows a schematic diagram of the method and apparatus of the present invention used to order a single analog-to-digital converter among multiple other modular gyro functions.

FIG. 9 illustrates a method of monitoring a modular gyro with a monitor control loop.

FIG. 10 illustrates a method of processing a dither pickoff signal that has been digitized and converted from the dither pickoff.

FIG. 11 shows a schematic diagram of a method of handling A / D conversion when called by any of the driving process, the stripper process and the background process.

FIG. 12 shows a schematic diagram of an interrupt service routine associated with a software timer interrupt.

FIG. 13 illustrates the method of the invention used to predict the sample strobe.

FIG. 14 illustrates the method of the present invention utilizing multiple analog to digital converters.

FIG. 15 illustrates the method of the present invention for awaiting background analog-to-digital conversion.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference is now made to FIG. 1 which shows a block diagram of one embodiment of a modular laser gyro employing the novel features of the present invention. The present invention will be described by way of examples. Those skilled in the art having the benefit of this disclosure will understand that the examples provided herein are for purposes of illustrating the principles of the invention and not for purposes of limitation. The laser gyro 10 has a control device 100,
Laser gyro block 200 and active current controller 300
A dither pick-off amplifier 400, a direct digital dither driver 500, a path length control (PLC) device 600, a read-out unit 700, and a digital logic 800.

In one embodiment, the direct digital dither driver of the present invention is implemented with a microcontroller used as controller 100. Dither drive unit is dither pickoff 244A
, Dither pickoff amplifier circuit 400, and A / D converter 110
And a control device 100, a PWM1 115 output line 501B, a direct dither drive unit 500, and a dither motor 204B. The A / D converter 110 may be integral with the controller and may advantageously be a 10-bit A / D converter. The 10-bit A / D converter is based on U.S. patent application Serial No. 07 / 805,122 filed on December 11, 1992, and is the applicant's co-pending PCT application "LASER GYRO DITHER STRIPPER".
10-bit accuracy is shown for the dither stripper method and apparatus discussed in more detail in. The controller 100 may advantageously further include a microprocessor 120. The controller 100 has a core of a processor 120 with hardware peripheral support that provides highly reliable, cost effective and highly integrated control functions.

Briefly, in operation, the PLG block position represented by pickoff voltage 245A is first amplified by dither pickoff amplifier 400. The amplified dither pickoff signal 501A is sent to an A / D converter 110 and a comparator (not shown), where the comparator produces a square wave 501C, which limits the maximum frequency of interrupts. One shot for
Sent to 810. One-shot 810 is reset periodically at a rate of about 1000Hz. One shot output interrupts the controller at the positive zero crossing. The dither pickoff and driver method is shown in more detail in FIG. Based on the zero crossings of the laser block positions, the microprocessor calculates the dither period and predicts the sample time.
Next, the dither drive waveform shown in FIG. 6 in more detail is shown in FIG.
To sample by. This sampling process requires to drive the dither motor 244B
A phase shift of 90 degrees can also be obtained. After sampling, the A / D value is compared to the desired gain adjustment displacement criterion, the amount is multiplied with the gain factor, random noise is added, and the signal is sent to the pulse width modulator 115. Random noise may advantageously be Gaussian noise. To correct for variations in the pickoff scale factor, the displacement criterion is modified by adjusting the dither stripper gain. The reference displacement may be further adjusted at periodic intervals by a laser gyro direct dither drive system. The operation of the present invention is discussed in further detail below.

In one embodiment of the invention, the microcontroller 100 is an Intel
(Registered trademark) 80C196 KC Microcontroller. Microcontroller 100 includes three pulse width modulators used for various control functions in this embodiment of the invention. The pulse width modulator PWM1 115 is used to control the dither drive circuit. A number of software modules are associated with the default control of the microcontroller 100. The software program is a microprocessor 1 contained within the microcontroller 100.
Executed by 20. A 100% PWM signal corresponds to a -150 volt output, a 50% PWM signal corresponds to a 0 volt output, and a 0% PWM signal corresponds to a +150 volt output.

In one embodiment of the invention, the pulse width modulated signal is initially
Set to 50% duty cycle. Part of the dither driver circuit utilizes the amount of random noise introduced into the driver circuit. The dither driver random number generator is initialized at startup of the control system of the modular gyro 10.

The dither driver circuit is further initialized by initializing system variables. The system represents a reference voltage used to calculate the actual displacement of the laser generation system. The dither drive circuit generates a pickoff signal 245A, which is an approximation of a sine signal, by dither pickoff. The pickoff signal represents the angular displacement. The reference peak angle value is compared with the peak of the sine pickoff signal to determine the difference value that defines the error in the dither driver. Then, during system power up, the actual reference voltage is initialized.
The reference values are stored in EEPROM 102 and represent the voltage to displacement conversion.

In one embodiment of the invention, the dither driver defaults to 20
It takes 0 ms. The dither drive is started simultaneously with the laser or slightly prior to the laser.

In the embodiment of FIG. 1, the microcontroller 100 has a first timer and a second timer. The first timer is used for the sampling function. The second timer is used for the dither driving function and the dither stripping function. Both timers need to be synchronized. The onboard high speed output logic of the microcontroller 100 synchronizes the timer to perform functions such as A / D conversion during the dither stripping function. The on-board high-speed input logic grasps the external event occurring in real time and stores the count value of the first timer in the FIFO register. As a result, the microcontroller 100 can individually and asynchronously grasp external events.

The sample strobe DS ₁ is provided by the host inertial navigation system. DS ₁ represents the time at which all gyros of the inertial navigation system should be sampled. In order to eliminate the latency of modular gyro systems, it is necessary to predict the sample time. The sample strobe DS ₁ also synchronizes the gyros inside the INS.

In this embodiment of the invention, microcontroller 100 has multiple analog inputs that are multiplexed into a single analog to digital converter. Multiplexing a single A / D converter to address more than one analog input signal requires proper sampling time. The microprocessor system includes non-volatile memory, which in this embodiment is electrically erasable programmable read only ("E ² PROM"). Some system parameters, such as dither frequency and dither reference angle, are stored in the E ² PROM so that they can be restored after the system is powered on. Those skilled in the art will recognize that other non-volatile memory means may be used.

In the start-up initialization sequence, the dither driver is pulsed with 20 square wave pulses at the dither frequency. For example, when operating at a dither frequency of 500Hz, the duty cycle is 0% to 10 for 20 pulses.
Change to 0%. This cycling action supplies energy to the dither motor near its natural resonant frequency to start the dither motor.

Reference is now made to FIG. 2 which shows a circuit diagram of an example of a dither pickoff circuit constructed in accordance with the present invention. In one example, the dither pickoff device comprises at least first, second and third capacitors 402, 406, 412 and first to seventh resistors 404, 407, 4
10,414,422,424,426 and first and second amplification means 408,42
0 and. Also shown in this figure is dither pickoff 244A, symbolized by the intrinsic capacitance. The first capacitor 402 is connected to the first resistor 40 at the connection point 405.
It is connected in parallel with 4. The dither pickoff is also connected to connection point 405. The second capacitor 406 is connected at its first terminal to the connection point 405 and at its other terminal to the non-inverting input terminal of the first amplifier 408.
The first amplifier 408, the resistors 410, 414 and 426, and the capacitor 412 are connected in a suitable configuration to perform the first gain factor and phase compensation for the dither pickoff circuit. The output 418 of the first amplifier outputs a substantially sinusoidal signal 416 representing the dither pickoff to the microcontroller 1
Supply to the analog / digital input terminal of 00. The second amplifier 420 and the resistors 422 and 424 provide a substantially square wave signal 430 to the zero-crossing input terminal of the one-shot 810 in the digital logic 800, which ultimately feeds the controller 100. It is connected and arranged in a known manner for supplying.
Signal 430 also represents dither pickoff and forms the basic zero-crossing detection signal upon which the dither period is calculated. Oneshot 810 limits the maximum interrupt frequency to 1000Hz, thereby eliminating false interrupts during startup.

Reference is now made to FIG. 3, which shows a schematic diagram of one embodiment of a direct digital dither driver circuit 500 as provided by one aspect of the present invention. The direct digital dither driver 500 includes first to sixth capacitors 502,506,509,514,522 and 534.
And the first to ninth resistors 504,508,510,511,512,518,51
9,532 and 542 and first to third transistors 520,528
And 530, a diode 524, and an amplifier 516.

The first capacitor 502 is connected at its first terminal to the pulse width modulation output terminal 501 of the controller 100. The first capacitor 502 is connected at the second terminal to the first terminal of the first resistor 504. The second terminal of the resistor 504 is connected to the second capacitor 506 and the first terminal of the second resistor 508. The second terminal of resistor 508 is a third resistor 511.
And a first terminal of a third capacitor 509. The second terminal of the third resistor 511 is the fourth capacitor 5
Connected to the first terminals of the fourteenth and fourth resistors 512 and the non-inverting input terminal of the amplifier 516 and the resistor 510. The output terminal of the amplifier 516 is connected to the base of the first transistor 520 via the sixth resistor 518 and the seventh resistor 519 of the resistor divider. The fifth capacitor 522 is the amplifier 5
It acts as a compensation capacitance for 16 and increases the phase margin. The second terminal of capacitor 514 is connected to the collector of transistor 520 and the base of third transistor 530 and to the first terminal of eighth resistor 532. The collector of the third transistor 530 is connected to the second terminal of the eighth resistor 532 and to a voltage source which would be 300 volts in this embodiment of the invention.

The emitter of the third transistor 530 is connected to the base of the second transistor 528, and the collector of this transistor 528 is connected to the voltage source so that the transistors 530 and 528
Form a Darlington pair. Diode 524 is a low voltage diode connected in parallel with its Darlington pair, forming a dead zone. The second terminal of the fourth resistor 512 is connected to the first terminal of the sixth capacitor 534 and the emitter of the third transistor 528. Capacitor 534 is used to level shift the output of transistor 528 by 150 volts. The drive signal is AC coupled to the ninth resistor 542 via 534 and is also AC coupled to the dither motor 244B in the laser gyroblock 200. Resistor 542 provides a zero volt DC average to the dither motor.

In one embodiment of the invention, the first to third transistors may advantageously be model type MJD50 NPN transistors available from Motorola, USA. The amplifier is an Analog De, Massachusetts, USA.
It would be advantageous to have a bipolar operational amplifier such as the model OP-97 available from Vices. Some examples of element values are shown in FIG. Controller 100 is Intel Corporatio
It may be advantageous to have an n model 80C19KC microcontroller or equivalent.

In operation, the direct digital dither driver of the present invention in this illustrated embodiment directly converts a 5 volt pulse width modulated digital signal from controller 100 to an analog 300 volt peak to peak signal without the use of a converter. It is a circuit to do. Conventionally, converters have been found to be unreliable, and in order to avoid saturation when driving a dither motor capacitive load at a low frequency of about 500Hz, it is necessary to increase the core size. Controller 100
The pulse-width modulated output 501B from the controller is taken from a 12 MHz crystal 104 and has a 5-volt pulse width modulation (PW) from a controller with 512 steps of resolution from 0% to 100% PWM.
M) It would be advantageous to be a signal. The PWM signal is used only as a means for digital / analog conversion and should not be confused with the method of pulse width modulation at the dither frequency.

In the embodiment of the present invention shown in FIG. 3, when a 5.5 nF load which is a typical dither motor load is driven with a peak-to-peak amplitude of 500 arcsec and RMS random noise of 4 arcsec, the direct digital dither drive circuit has a transformer structure. Demands less than 300mW as opposed to 750mW required by. In a typical laser gyro system, 4 arcsec
Is equivalent to a standard deviation of about 1 sigma. The efficiency of the circuit arrangement of the present invention is that it filters PWM23.5KHz signals and yet has a transfer function of about (500Hz x 23.5KHz) ^1/2 = 3.6KHz giving rise and fall times of less than 200 microseconds. It is realized by arranging three low poles. When the driving frequency is f, the voltage required to drive the capacitive load is proportional to (V ² × f),
It is important to filter the PWM signal from the load to avoid wasting power.

The efficiency of the drive is further improved by the controller changing the PWM value only twice per dither cycle. The first change occurred at the positive peak of the dither pickoff, 2
The second change occurs at the negative peak. 5.5nF to 500Hz, 300
Power theoretical required to drive a bolt (full amplitude) is the formula: is given by ^{P = 2f (1 / 2CV 2} ) = 272mW. The AC power for one embodiment of the present invention is close to this theoretical limit. The DC bias power is about 81mW.

Another aspect of the invention is that it does not include PNP transistors
It includes a single power source structure that is a PN transistor. NPN transistors are available in a surface mount DPAK with the following parameters: V _CEO = 400VDC and V _CB = 500VDC The diode 524 forms a dead band to prevent transistors 520 and 528 from turning on at the same time.
The dead band eliminates current spikes in the power source and further improves efficiency.

To improve stability during the rising and falling transitions, the fourth capacitor 514 is connected at the output terminal to the base of transistor 530 rather than the emitter of transistor 528. In one embodiment of the present invention, fifth resistor 512 sets the DC operating point of the output at the emitter of transistor 528 at approximately +150 volts. Next, transistor 528
The output at the emitter of is level-shifted to the final output 540 by coupling capacitor 534. In this configuration, the 50% duty cycle PWM signal input is output 5
Corresponds to a 0 volt output at 40. A 0% duty cycle PWM signal corresponds to an output of 540 at about +130 volts. A PWM signal with 100% duty cycle is approximately −13 of output.
Equivalent to 0 volts. In the illustrated example, during power up of the laser gyro, the time to charge the coupling capacitor 534 is about 0.7 seconds.

In another aspect of the invention, the input is AC coupled by the first capacitor 502 to perform a symmetrical drive with no low frequency components. Capacitor 50 during laser gyro startup
In order to charge 2 to a given DC level, the controller has about 1
Output PWM signal with 50% duty cycle for 4ms. As mentioned earlier, the start-up initialization sequence begins by pulsing the dither driver with a square wave at 20 dither frequencies. The duty cycle varies from 0% to 100% for 20 pulses when the dither frequency is 500 Hz. This cycling action supplies energy to the dither motor near its natural resonant frequency to start the dither motor.

Reference is now made to FIG. 4, which shows a detailed schematic diagram of an alternative embodiment of a dither driver circuit as provided by one aspect of the present invention. The dither drive circuit of FIG. 4 has primary windings 460 and 464,
It is composed of a transformer having a secondary winding 462. The first diode 454 is connected via a winding 460 to a voltage source 480, which may be nominally ± 15 volts. Similarly,
The second diode 456 is connected to the voltage source 480 via the winding 464. The secondary winding 462 is coupled at its first leg to the dither driver 244B on the laser gyro block 200. The pair of transistors 450 and 452 are driven by the push-pull method by the first and second PWM signals 470 and 472. Transistors 450, 452 may advantageously be MOSFET type devices or equivalent devices.

Reference is now made to FIG. 5A, which shows a high level schematic diagram of the direct digital dither drive method and apparatus of the present invention showing the dither pickoff signal 245A from dither pickoff 244A to dither motor 244B. FIG. 5A shows the voltage 205 representing dither displacement.
2 shows an embodiment of a dither driving unit for converting the gain into a laser gyro count representing the inertial rotation of the gyro 200. All subsequent processing is performed using the count up to the generation of PWM signal 501.

The dither pickoff 244A is the dither pickoff signal 245A.
To the filter 202, which adjusts its dither pickoff signal 245A and provides an adjusted pickoff signal 203. The pickoff signal 203 is amplified by the amplifier 204 and sent to the 10-bit A / D converter 206. The A / D converter 206 converts the adjusted amplification dither pickoff signal 205 to the dither pickoff signal 2
It is converted into a digital signal 207A representing the voltage of 45A. Next, the digital signal 207A is gain-converted by the amplifier 215 into the count value 209A representing the angular displacement of the gyro block 200.

In the embodiment of FIG. 5A, the digital signal 207A is converted into a predetermined constant K
Convert to a count by multiplying by. One count is almost equal to the angular displacement of 1 arcsec. The constant K is in units of count / volt. K is the same constant used in the dither stripper to find the equivalent digital volt. The constant K is constantly updated by the dither stripper and represents the direct calibration correlation between the dither pickoff analog volt and the equivalent digital read count.

The predetermined reference displacement dither angle 213, expressed as a digital count, is stored in EEPROM 102.

The digital signal then proceeds to a digital gain amplifier 212 which provides the signal to a random noise injector 210 which introduces random noise 211 into the signal. Random noise 211 is provided to prevent the laser from undergoing the dynamic lock-in effect. There, the signal is input to the pulse width modulation limiter 214, which supplies the signal 215 to the pulse width modulator 216. The PWM signal is determined by the difference between the reference value and the measured displacement value of the block. The direct dither driver is shown in more detail in FIG.

Reference is now made to FIG. 5B, which shows another high level schematic diagram of the direct digital dither drive method and apparatus of the present invention showing the flow of dither pickoff signal 245A from dither pickoff 244A to dither motor 244B. In Figure 5B, all processing is PWM
5 illustrates one embodiment of a dither driver as performed using Volts up to the generation of signal 501.

In the alternative embodiment of the invention shown in FIG. 5B, the output of A / D converter 206 is provided to comparator 208 to generate a signal representing voltage rather than counting as in the case of FIG. 5A.

A predetermined reference displacement dither angle 213, represented as a digital count, is stored in EEPROM 102. In the embodiment of FIG. 5B, the reference displacement 213 is converted into digital volt by multiplying it by the reciprocal of a predetermined constant K. The rest of the processing in FIG. 5B proceeds in the same way as in the case of FIG. 5A.

Next, from dither pickoff 244A to dither motor 244B.
Dither pick-off signal 24 to Leg1 470 and Leg2 472
Please refer to FIG. 5C, which shows another high-level schematic diagram of the method and apparatus for direct digital dither driving of the present invention showing the flow of 5A.
As with the method and apparatus of the present invention according to FIG.
4 shows an embodiment of a dither driving unit that converts the voltage 205 representing the dither displacement into a laser gyro count representing the inertial rotation of the gyro 200. All subsequent processing is performed using counts up to the generation of the High Speed Output Content Referenceable Memory (HSO CAM) drive signals 470 and 472.

Also in FIG. 5C, the digital signal goes to a digital gain amplifier 212 that provides a signal to a pulse width modulation limiter 214, where the limiter 214 provides a pulse width modulation signal 215 to an HSO CAM driver 216 of the digital dither driver. As in the previous embodiment, the PWM signal is determined by the difference between the reference value and the measured displacement value of the block.

The fast output logic in this embodiment of the invention is INTEL
CORPORATION 80C196 KC Microprocessor H
It is formed by the SO unit. The fast output logic triggers an event at a given point in time. Events are coordinated by writing commands in what are called the HSO Command Register and HSO Time Register. Different events are possible with high speed outputs including A / D changes, timer resets, software flag resets and high speed output line switching. INTEL
For more detailed knowledge of high speed output logic, refer to CORPORATION's 80C196 KC User's Guide. For more information, see the HSO Command Register 80C196 KC Use
See Figure 10-1 of the r's Guide. Inputs to the dither driver directly come from the HSO CAM driver or the 80C196 KC microcontroller. The structure of the direct dither driver 500 is shown in more detail in connection with FIG.

The high speed output CAM driver 216 then provides a dither signal to drive Leg1 at 470 and Leg2 at 472.

FIG. 5D represents one embodiment of a dither driver such that all processing is performed using the voltage up to the generation of HSO CAM drive signals 470 and 472.

Reference is now made to FIG. 6, which shows a detailed interrupt timing diagram of the method of the present invention. The direct drive dither system in one embodiment of the present invention uses the output 430 of the zero crossing detector of FIG. 2 to trigger an interrupt. Signal 430 of FIG. 2 provides a train of waveforms similar to a timing clock. FIG. 6 shows the details of the waveform sequence as a group of square waves 604. The waveform train is shown as the output of signal line 430 as a function of time 602. Signal 604 indicates when gyro block 200 crosses the zero point in its cyclic dither motion, as indicated by gyro block position signal 620.
The zero crossings are indicated by 618A, 618B, 618C and 618D. The interrupts that have occurred are shown as interrupts 610A, 610B, 610C and 610D. Interrupts are points 605A, 605B, 605C and 60
It occurs at zero crossings 618A, 618B, 618C and 618D of block 200 corresponding to the low-to-high transition of output signal 430 at 5D.

By noting when the low-to-high transition occurs, the frequency of dither pickoff 244A can be calculated.
In FIG. 6, t ₀ represents the occurrence of transition 605A that generates interrupt 610A, t ₁ represents the occurrence of transition 605B that generates interrupt 610B, t ₂ represents the occurrence of transition 605C that generates interrupt 610C, and t ₃ represents the occurrence of transition 605D which generates interrupt 610D. This set of information for each interrupt divides the time difference (t ₁ −t ₀ ) into one cycle. That is, 1 / (t ₁
The frequency of dither can be calculated by finding −t ₀ ). With this set of information between two or more interrupts,
Dividing the time difference between interrupts 610A and 610D to (t ₃ -t ₀₎ to three cycles, i.e., can calculate the frequency of the dither by determining the _{3 / (t 3 -t 0)} .

In one embodiment of the direct dither method of the present invention, 90 ° and 27 °
It is necessary to measure the location of the 0 ° block cycle position. The 90 ° position is shown in Figure 6 as points 622A, 622B and 622C.
As shown. The position of 270 ° is point 624A, 62 in Fig. 6.
Shown as 4B and 624C.

Reference is now made to FIG. 7 which illustrates the direct digital dither driver method of the present invention for determining the 270 ° and 90 ° intersections of the dither cycle. The method begins with process block 9 showing an interrupt generated by zero-crossing detector output 430.
Starts with 02. The zero crossing detector is shown as signal 604 in the previous figures, FIGS. The interrupt signal from the zero crossing detector is known as the T2CAP interrupt in one embodiment of the method of the present invention. The process then proceeds to 904, which executes the T2CAP interrupt service routine. The T2CAP interrupt service routine is described in the process flow chart that follows. At 906, the time when the T2CAP interrupt is generated is grasped. The process then proceeds to 908 and stores the interrupt time Tn in a temporary register. The process then proceeds to 910 and calculates the change in time from the last interrupt. The first time this process is run, it approximates the initial time. The new time, DeltaT, is established as the difference between the current time and the previous interrupt time. The process then proceeds to 912 and divides the elapsed time between the two interrupts, i.e., the time difference, by 4. This procedure is performed to determine the quadrature involved in the time difference between interrupts. This number is accurate as the resolution of the digital system and represents the amount of time between zero crossings of the dither cycle. This quantity itself represents the actual dither frequency of the laser gyroblock.

Then proceed to process 914 to calculate phase lead compensation.
Phase lead compensation is established in the T2CAP interrupt shown in FIG. Phase lead is defined as Delta T divided by a constant K _PL . Delta T corresponds to the amount of time the laser block takes to dither one cycle.
That is, Delta T is equal to 360 °. The constant K _PL is a predetermined value based on the dither cycle and the analog delay.
For example, if the predetermined constant K _PL is equal to 32, the phase advance would be 360 ° / 32, or 11.25 °. The amount of phase lead time, defined as T _PL , will be calculated by multiplying Delta T by the phase lead ratio of the cycle. That is, T _PL = Delta * (11.25 ° / 360 °). The purpose of the phase advance is to provide a dither drive signal that matches the desired actual dither drive signal. This phase advance predicts the related delay in the processing circuit of the dither driver and the related delay in the software processing. The first quadrature Q1 corresponds to the actual displacement of the laser block at the 90 ° position. Phase lead quadrature Q1 _PL is defined as Q1-T _PL which represents the actual sample time associated with the fast output dither drive CAM 216 shown in FIG. The process of FIG. 7 then proceeds to 916, where midpoint Q2
Is determined to be twice the sum of the first quadrature (Q1 + Q1). The process then proceeds to 918 where the third quadrature Q3
Is defined as Q2 + Q1 _PL . Next, T2CAP in FIG.
The interrupt checks for background A / D conversion if necessary. The need for background A / D conversion currently schedules software timer flags and interrupts used by the execution ordering method of the present invention shown in FIG. 12 to solve the use of A / D conversion. Software timer flags and interrupts are scheduled using fast output logic. The process then proceeds to step 919 to order the A / D conversion associated with the dither drive and dither stripper along with the background A / D conversion. Process 919 is described in detail in connection with FIG.
The process ends at 920 and returns to the return modular gyro monitor control loop shown in FIG.

The monitor control loop 390 shown in FIG. 9 is the main process execution loop associated with the digital modular gyro 10. The monitor control loop waits for dither stripper A / D conversion to complete at step 300 before executing the process of the monitor control loop. A conversion complete flag, which when set, indicates that A / D conversion is complete, is included in the device of the present invention. The monitor control loop 390 first illustrates the execution of the dither stripper algorithm 302. Compensation of rotational inertial navigation data related to temperature bias drift and age occurs in the next step 304. In 306,
Monitor control loop 390 performs the system I / O setup. The process then proceeds to bias drift improvement and random drift improvement steps at 308. The process then proceeds to 310 to process the commands provided by the external system for the modular gyro. Process is 312
Perform a built-in test function at and process 314 checks for laser mode limits. Then the monitor control loop 390
Repeats this series of processes until the modular gyro 10 is shut down.

Reference is now made to FIG. 15, which illustrates a method of scheduling A / D background conversion. Scheduling of A / D background conversion occurs in a hardware system that has a predetermined set of A / D conversion events that can be queued. The number of A / D changes is predetermined. In one embodiment of the invention, the queue contains seven A / D conversions. By the monitor control loop shown in FIG. 9, the process of ordering those A / D conversions is first started at step 870 which checks the A / D background conversion done flag. The process then proceeds to 872 and checks the flag to see if the conversion done flag is set. If the flag is not set, the process exits the routine and returns to the monitor control loop at step 870. In this case, the A / D involved in the A / D conversion that was scheduled first
A / D conversion cannot be performed because the conversion has not yet been performed. If the conversion done flag is set, the process proceeds to step 874 and stores the current background A / D conversion in the background conversion A / D register. This currently correlates background A / D conversion with functions set up by another routine such as temperature measurement, PLC monitoring. Then the process is a step
Proceed to 878 to check the background A / D conversion multiplexer pointer. The process then proceeds to 880 to determine what to do after examining the pointer. If the pointer points to the previous background function, then in step 882 the queue is reset to point to the first function. If the pointer is not the previous background function pointer, the process increments at 884 to the next background function pointer. In either case, the process proceeds to step 886 to schedule another background conversion in the queue. The process then exits at 876 into the monitor control loop.

FIG. 8 illustrates a method of ordering a single analog-to-digital converter among multiple analog signals in a digital dither driven application of the method of the present invention.
Refer to. FIG. 8 shows a process flow diagram for the digital modular gyro 10 to transfer the dither stripper conversion time 702 to step 702. Conversion time HsiTime 1 is 1
Filed on December 11, 991, Name Laser GYRO DITHER STRIPP
Calculated from the dither stripper process described in Applicant's co-pending PCT application under ER's US Serial No. 07 / 805,122.

The process then flows to calculate the expected stripper time calculated from the two values sent in in process 702. The first value is HsiTime 1, which is the beginning of the dither stripper conversion time, and HsiDelta is also sent from the external system via process 702. The expected dither stripper sample time is the sum of HsiTime 1 and HsiDelta.
This time is called HsiTime 2. The process then proceeds to 706, where a window is created around HsiTime 2 to lock out the A / D converter involved in dithering. This is a dither driven A / D converter and a dither stripper A / D.
Prevents them from interfering with each other if the conversions occur simultaneously. The A / D converter in this embodiment of the invention is an asynchronous converter. The A / D conversion happens asynchronously to the process of setting up the A / D conversion. Process step 708 calculates whether the A / D conversion involved in dither driving occurs within the dither stripper window. The process then branches to either process step 712 or process step 710. Process step 710 sets up a high speed output content referable memory (HSO CAM) to schedule the phase compensated A / D conversion and software timer flags and interrupt for a particular dither drive. Process step 712 sets up the HSO CAM to schedule the software timer flag and interrupt for a particular dither drive to share the already scheduled dither stripper A / D conversion. The method of the present invention determines which type of action should be taken at a scheduled time, dither stripper transformation, dither driven transformation, dither stripper and dither driven shared transformation, or background transformation. , Check the status of the software time flag. Process step 708 provides a way to schedule a new A / D conversion or to share the scheduled conversion with the one that occurs. Implicit in the method of the present invention is that a single A / D conversion in the window is suitable for dither driven applications because the dither stripper A / D conversion always has the highest priority. Is the assumption. In process 712, a flag is set that indicates another routine, namely the dither drive routine and the dither stripper routine where A / D conversion is shared. In process step 710, the A / D conversion is scheduled and the result of the conversion is described below.
Send contents to 100 memory which can be referred. A / D conversion is scheduled at times Q1 and Q3, which are phase compensated as described above. The process then proceeds to 714, where A
The execution order designation of the / D converter is completed.

Reference is now made to FIG. 10 which illustrates a method of calculating a pulse width modulated drive signal from a dither pickoff analog to digital conversion. The method of the present invention embodied in the 80C196 KC Microcontroller 100 begins at process block 821 with an A / D conversion interrupt from the dither drive routine at 822. Step the reference displacement, which is the amount of angular displacement of the dither motor expressed in read counts that should be occurring
Read from memory at 824. In step 825, the dither angle reference count is converted to an equivalent analog pickoff signal in digital volts based on the dither stripper gain adjustment.

The process then proceeds to 826 where the error in dither motor displacement is calculated as the reference displacement minus the actual displacement. The process then proceeds to 828 where the calculated error is multiplied by a predetermined gain factor, which is 50 in one embodiment of the invention. The process then proceeds to 830, which introduces random noise into the system. In one embodiment of the present invention, which has no limiting meaning, the random noise distribution is a Gaussian distribution. The process then proceeds to 832 where the pulse width modulated signal output is limited to a maximum of 100% PWM and a minimum of 0% PWM to avoid register rollover. In this embodiment of the invention, the limit value is 0% or
0 or 255 representing 100% PWM. The process then proceeds to step 834, which provides the dither driver with the calculated drive level to bring the dither motor into the reference value adjusted by the introduced random noise. The process then ends at 836.

Reference is now made to FIG. 11, which shows a schematic diagram of the A / D conversion handler of the direct digital dither driver. In a modular gyro, A / D conversions are required for dither driven transformations, dither stripper transformations and background transformations as required to calculate the quadrature of dither. The process shown in FIG. 11 is a method of processing an A / D conversion depending on which process the A / D conversion requested. The method begins at 930 with an A / D conversion interrupt. At process block 932, the source of the A / D conversion comes from the dither driven process at 934, the dither stripper process at 936, the dither stripper and dither driven process 938, or the background process 940.
Determine if it occurs from. Stripper and drive step 938 indicates that a dither driven A / D conversion has occurred within the dither stripper A / D conversion window. The dither stripper window is also suitable for dithering, so the process proceeds to step 942 just as for a simple dither stripping operation. Digital drive 934, which requires A / D conversion, goes directly to 946 dither drive. The dither drive routine is described in further detail in FIG.

By the time the A / D conversion "occurs", we already know which process requested the A / D conversion. This is Figure 8
It was previously determined by the T2CAP interrupt shown in and the software timer interrupt.

If the dither stripper, or the dither drive and dither stripper, requests A / D conversion, the process proceeds to step 942 to read the A / D value in the stripper register.
Next, at 944, the A / D conversion complete flag is set to indicate that the stripper or stripper and drive most recent A / D conversion value is in the stripper register and was requested by the stripper and drive. Next, the process is run 94 if either drive or stripper and drive.
Proceed to 6 dither drive. In the case of background A / D conversion, the process proceeds to 940 where the A / D value is retrieved from the background register at 948 and the conversion done flag is set for background conversion at 950. In either case, the process ends at 952.

Next, a diagram showing an interrupt service routine of a software timer interrupt for scheduling either a dither only conversion, a shared conversion or a background conversion.
See 12. The process begins at 1000 by fetching the software timer flag from the special function register at step 1002. The process then checks to see if the software timer flag is set for dither driven A / D conversion. If so, the process proceeds to step 1020, where the microcontroller
Set the dither drive A / D conversion dedicated flag in the A / D priority register in the 100 scratchpad RAMs, then step 1
It ends with 022. If dither driven conversion is not indicated, the process proceeds to step 1006, where the process checks to see if the software timer flag is set for the drive and stripper conversions. If so, the process proceeds to step 1018 where the dither stripper and dither drive shared A / D are stored in the A / D priority register in the scratchpad RAM of the microcontroller 100.
The D conversion flag is set, and the process ends in step 1022. If no shared transform is indicated, the process is step 10.
Proceeding to 08, the method of the present invention checks if a dither stripper A / D conversion is in progress. Implicit in the method of FIG. 12 is the condition that if there is no shared or dither driven conversion, it must be a background conversion. The process then proceeds to step 1010 where the dither stripper is in a window defined as HsiTime + HsiDelta as described in step 702.
Check if A / D conversion occurs. If the conversion occurs within the window, the process ends at step 1022. If no conversion occurs in the window, the process proceeds to step 1014 and waits for the background conversion to complete. Background conversion occurs during a specified period, and in one embodiment of the invention, background conversion occurs within 20 microseconds. The process then proceeds to step 1016 where the converted value is converted to background A /
Store in D register. The process then ends at step 1022. It will be appreciated by those skilled in the art that the situation waiting for the completion of the background A / D conversion process can be interrupt driven as described in FIG. 11 or polled as described in FIG. Ah

FIG. 13 illustrates the method of the present invention used to calculate and predict the occurrence of the next system sample clock.
Refer to. The importance of predicting the sample clock is represented by the fact that the external inertial navigation system must acquire inertial navigation data that is synchronized to the uniform external clock throughout the inertial navigation system. Without this capability, inertial navigation data is supplied asynchronously, so
This will result in incorrect evaluation of inertial position. The process of Figure 13 begins by starting a counter at process block 150 when the process is first initialized. Next the process is process block 15
Proceeding to 2, note the edge of the sample clock from the system, which causes an interrupt at process block 154. The interrupt then initiates a process called interrupt loop 170. The interrupt loop schedules A / D conversion. At the time of the interrupt that was generated in process step 154, the counter value from the counter in step 150 is stored. The process then proceeds to 158 and reads from memory the last time the interrupt occurred. The process then proceeds to 160 and T-computes the time difference between the old and new interrupts as "delta t". Then the process is 162
Go to and set up the A / D conversion on the high speed output of the microprocessor. The new time at which high speed output should occur is the "new t" plus the "delta t". The process then proceeds to 164 where it sets up "old t" equal to "new t" and the process returns to process 152 to find the next sample clock. The method of FIG. 13 dynamically compensates for changes during the system sample clock period and dynamically tracks the movement of the system sample clock. At 162, the HSO logic sets up the A / D conversion for the dither stripper. A / D conversion is also possible by the dither driver described in Applicant's co-pending ring laser gyro direct dither driver.
Is used.

Reference is now made to FIG. 14, which illustrates the present method and apparatus for driving a laser gyro dither utilizing three analog to digital conversions. It will be appreciated by those skilled in the art that the method of the present invention could be applied to the device described in FIG.

In this embodiment, the first A / D converter 1212 provides a digital representation of the dither pickoff voltage that is appropriately timed for the dither stripper operation described above. The A / D conversion involving the dither stripper must occur when DS1 is active. Micro controller 100
Performs the dither stripping operation using the result of the A / D conversion and the output 1222 of the edge trigger read counter register 1220.

The second A / D converter 1214 provides a properly timed digital representation of the dither pickoff voltage for the dither driving operation described above. The A / D conversion involved in dithering must occur when the zero crossing detector 820 is active. The microcontroller 100 uses the A / D conversion result 1204 to perform the dither drive operation.

The third A / D converter 1216 provides a digital representation of background processes such as temperature measurements, RIM and LIM measurements, PLC monitoring. Background A / D conversion is enabled by the microcontroller via enable line 1218.

Corresponding hereto in order to provide the person skilled in the art with the information necessary to comply with the patent law of the present invention and to apply the new principles and to configure and use such specialized devices as required. Explained in detail. However, it should be understood that the invention may be specified and practiced by different equipment and devices, and that various variations can be realized in both the details of the equipment and the operating procedure without departing from the scope of the invention itself.

Front Page Continuation (72) Inventor Brent, Dale F United States 55441 Minnesota Plymouth Pineview Rain Nose 335 (56) References JP-A-58-70167 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G01C 19/68 H01S 3/083

Claims (38)

(57) [Claims] 1. A direct digital dither drive device for a laser gyro (10) having a dither gyro block (200) with a dither motor (244B) and a dither pickoff (244A), a. Connected to the dither pickoff (244A). It also has a dither pick-off output (245A) and a dither pick-off (244A).
A) means for sensing (402, 404, 406 and 407); b. Means for amplifying dither pickoff output (245A) (400) having amplified dither pickoff output (501A); c. Amplified dither pickoff output (501A); An analog / digital conversion means (110) having a digital dither signal output (207A); and d. A digital dither signal output (207A) having a pulse width modulation signal output (501C). Digital control means (100) for generating a pulse width modulation signal in proportion to the output obtained by subtracting the reference displacement and adding a predetermined amount of random noise; and e. Having a dither drive signal connected to a dither motor (244B). Dither motor (244B) in response to a pulse width modulated signal
And a means (500) for driving the direct digital dither driving device. 2. The direct digital dither driver according to claim 1, wherein the random noise has a Gaussian distribution. 3. The direct digital dither driver according to claim 1, wherein the random noise has a normal distribution. 4. Means (50) for driving a dither motor (244B) further comprising a power source (544) for providing a power supply signal.
0) is: a. Low-pass filtering means (504, 506, 508 and 509) having an output providing a filtered signal and an input (501) connected to a pulse width modulated drive signal; b. Low-pass filtering at the input side. Coupled to the output of the means,
Amplified signal output, low-pass filtering means (504,50
6,508 and 509), and means (516,510 and 522) for amplifying the filtered signal; c. The dither drive signal is responsive to the amplified signal output and the drive means (500) is means for providing a dead zone operating characteristic. A direct digital dither driver as claimed in claim 1 including active pull-up means (524, 528, 530 and 532) including (524). 5. Active pull-up means (524, 528, 530 and 53)
The direct digital dither driver (500) of claim 4, wherein 2) substantially eliminates current spikes in the power supply signal so as to reduce power consumption. 6. An active pull-up means (546) comprises: a. First transistor means (530) having a base, collector and emitter; b. Second transistor means (528) having a base, collector and emitter. Wherein the collectors of the first transistor means (528) and the second transistor means (530) are connected to a voltage source (544), and the emitter of the first transistor means (530) is the second transistor means. (52
Second transistor means connected in a Darlington configuration to the base of 8); c. Connected to the emitter of the second transistor means (528) at the first terminal and first at the second terminal A direct digital dither driver according to claim 4, comprising diode means (524) connected to the base of said transistor means (530). 7. A means (50) for driving a dither motor (244B).
0) is +150 in response to a pulse width modulated input ranging from 0% duty cycle to 100% duty cycle
The direct digital dither driver of claim 1 which provides an output in the range of volt to -150 volts. 8. The direct digital dither driver according to claim 1, wherein the analog-to-digital conversion is phase-compensated for time delay in analog signal propagation and digital signal processing. 9. The dither crosses points of zero magnitude periodically every dither period, and the analog-to-digital conversion of the dither drive signal is a quarter of the path through the dither period called the 90 ° dither period sample time. The direct digital dither driver of claim 1 which occurs on one third and three quarters of the path through the dither period called the 270 ° dither period sample time. 10. The direct digital dither driver as claimed in claim 1, wherein the digital control means is a micro controller (100). 11. The direct digital dither driver according to claim 10, wherein the microcontroller (100) comprises a monolithic integrated circuit. 12. A means for sensing a dither pickoff (244A) includes: a. A first capacitor (402) having a first terminal and a second terminal in parallel with the dither pickoff (244A); b. A first resistor (404) connected between the first and second terminals and in parallel with the dither pickoff (244A) and the first capacitor (402); c. Filtering dither output ( 409) and a second capacitor (406) for ac coupling the dither pickoff (244A) to the first terminal and to the input of the first amplifier (408); d. Analog dither pickoff An output (418), a first input (409) and a second input (411), the first input being connected to the filtering dither output and the second input being connected in parallel. The analog dither pick-off is output via the second resistor (410) and the fourth capacitor (412). Connected to (418), a second input and the third resistor (42
First amplifier means (408) for amplifying the filtered dither output connected to ground via 6); e. Dither zero crossing detector output (430) and first input (41).
8) and a second input (419), the first input being connected to the analog dither pickoff output (418) and the second input (419).
Input (419) is connected to the dither zero-crossing detector output (430) through a fifth resistor (422) and a second input (419)
Direct digital according to claim 1, characterized in that it comprises a second amplifier means (420) for amplifying the analog dither pickoff output (418), which is also connected to ground via a sixth resistor (424). Dither drive. 13. The dither driven software interrupt is generated by the transition of the zero crossing detector output (430).
Direct digital dither drive described. 14. The direct digital dither driver of claim 13, wherein the frequency of the dither motor is calculated by dividing the number of zero crossing detector transitions by the duration of the zero crossing detector transitions. 15. The control means (100) supplies a first pulse width modulation dither drive signal (470) and a second pulse width modulation dither drive signal (472), and means for driving the dither motor is: a. having a first gate, a first source and a first drain, the first gate connected to a first pulse width modulated dither drive signal (470) and the first drain connected. A first transistor means (450) connected to the point; b. A second gate, a second source and a second drain, the second gate having a second pulse width modulation; Second transistor means (452) connected to the dither drive signal (472) and having a second drain connected to ground; c. A first coil with a first terminal and a second terminal. (46
2) and second coils (460) and (464) having third and fourth terminals and a center terminal, the first terminal (462) being connected to the dither drive signal (462), The second terminal is connected to ground and the central terminal is the voltage source means (480)
A first inducing means (480) connected to the first source, the third terminal being connected to the first source and the fourth terminal being connected to the second source; d. A direct digital according to claim 1, comprising a first diode (454) connected between the second diode (456) and e. A second diode (456) connected between the fourth terminal and the center terminal. Dither drive. 16. A dither gyro block (200) with a dither motor (244B) and a dither pickoff (244A).
In the direct digital dither driving method of the laser gyro (10) having: a. A step of sensing the actual displacement of the gyro block; b. A step of reading the reference displacement of the gyro block previously stored in the memory; c. The step of calculating the difference between the reference displacement and the actual displacement; d. The step of forming a digital drive signal by adding a random noise of a predetermined distribution to the difference; e. The pulse width modulation of the digital drive signal. A direct digital dither driving method comprising the steps of: converting into a signal; 17. The direct digital dither driving method according to claim 16, wherein the error is adjusted by multiplying the error by a gain coefficient. 18. The direct digital dither driving method according to claim 16, wherein the pulse width modulation signal is limited to prevent rollover. 19. A dither gyro block (200) with a dither motor (244B) and a dither pickoff (244A).
In a direct dither drive of a laser gyro (10) having: a. Amplification means (202) connected to the dither pickoff (204A) and having an analog dither signal output (203); b. (207) means (206) for converting; c. Means (215) for converting the digital dither signal into a digital count signal by multiplying the digital dither signal by a predetermined scale factor; Means (208) for subtracting the reference displacement count to generate a differential displacement signal; e. Means for introducing random noise into the differential displacement signal to generate a digital drive signal (210); f. Digital drive signal Means (216) for converting the pulse width modulated signal (501) into a pulse width modulated signal (501); g.
44B) means (500) for driving a direct dither driving device. 20. The direct dither driver of claim 19, wherein the pulse width modulated signal is limited to prevent rollover. 21. The direct dither drive signal of claim 19, wherein the differential displacement signal (209A) is gain adjusted to the magnitude of random noise. 22. The direct dither driver according to claim 19, wherein the random noise has a Gaussian distribution. 23. The direct dither driver according to claim 19, wherein the random noise has a normal distribution. 24. A means (500) for driving a dither motor, further comprising a power source for providing a power supply signal, comprising: a. An output for providing a filtered signal and a pulse width modulated drive signal (501). Low-pass filtering means (504, 506, 508 and 509) having an input; and b. Having an amplified signal output, which is coupled at the input side to the output of the low-pass filtering means and amplifies the filtering signal from the low-pass filtering means A dither drive signal responsive to the amplified signal output, the drive means comprising active pull-up means (524) including means (524) for providing a deadband operating characteristic. Drive. 25. The direct dither driver according to claim 24, wherein the active pull-up means (546) substantially eliminate current spikes in the power supply signal so as to reduce power consumption. 26. An active pull-up means (546) comprises: a. A first transistor means (530) having a base, a collector and an emitter; b. A second having a base, a collector and an emitter. Transistor means (528) of the first transistor means (530) and the collector of the second transistor means (528) are connected to a voltage source (544), and the emitter of the first transistor means (530) A second transistor means connected in a Darlington configuration to the base of the second transistor means (528); c. Connected to the emitter of the second transistor means (528) at a first terminal, The diode means (52) connected to the base of the first transistor means (530) at the second terminal
25. The direct dither driving device according to claim 24, further comprising: 27. Means (500) for driving a dither motor (204B) provide an output in the range of +150 volts to -150 volts in response to a pulse width modulated input over the range of 0% duty cycle to 100% duty cycle. 20. The direct dither driving device according to claim 19. 28. The direct dither driver of claim 19, wherein the analog-to-digital conversion is phase compensated for time delays in analog signal propagation and digital signal processing. 29. The dither crosses a point of zero magnitude periodically every dither period and includes an analog / digital drive signal.
20. The direct conversion of claim 19 wherein the digital conversion occurs on a quarter of the path through the dither period called 90 ° dither period sample time and three quarters of the path through the dither period called 270 ° dither period sample time. Dither drive. 30. The direct dither driver according to claim 19, wherein the digital control means is a microcontroller (100). 31. Amplifying means (400) connected to a dither pickoff (244A) comprises: a. Having a first terminal (405) and a second terminal (403) and in parallel with the dither pickoff (244A). A first capacitor (402); b. Connected between the first terminal (405) and the second terminal (403) and in parallel with the dither pickoff (244A) and the first capacitor (402). A first resistor (404); c. Having a filtering dither output, and a first terminal (40
5) and a second capacitor (406) connected to the input (409) of the first amplifier (408) to ac couple the dither pickoff (244A); d. The analog dither pickoff output (418); A second resistor (410) having one input (409) and a second input (411), the first input being connected to the filtering dither output and the second input being connected in parallel. And a filtering dither output connected to the analog dither pickoff output (418) via a fourth capacitor (412) and a second input connected to ground via a third resistor (426). Amplifier means (408) for amplifying
And; e. Dither zero-crossing detector output (430) and first input (41
8) and a second input (419), the first input being connected to the analog dither pickoff output (418) and the second input (419).
Is connected to the dither zero-crossing detector output (430) via a fifth resistor (422) and the second input is connected to the sixth
Is also connected to the ground via a resistor (424),
A second amplifying analog dither pickoff output (418)
20. The direct dither driver of claim 19, further comprising: amplifier means (420) of 32. The dither driven software interrupt is generated by the transition of the zero crossing detector output (430).
The direct dither drive described. 33. The direct dither driver of claim 32, wherein the frequency of the dither motor is calculated by dividing the number of zero crossing detector transitions by the duration of the zero crossing detector transitions. 34. A high speed means for driving a dither motor for driving a first dither leg with a first pulse width modulated signal and a second dither leg with a second pulse width modulated signal. 20. The direct dither driver according to claim 19, further comprising output logic means (216). 35. Means (10) for converting a digital drive signal.
0) supplies the first pulse width modulation dither drive signal (470) and the second pulse width modulation dither drive signal (472),
Means for driving the dither motor include: a. Having a first gate, a first source and a first drain, the first gate being connected to a first pulse width modulated dither drive signal (470). And a first drain having a first transistor means (450) connected to ground; b. A second gate, a second source and a second drain, and a second gate A second transistor means (452) connected to a second pulse width modulated dither drive signal (472) and a second drain connected to ground; c. First and second terminals. With the first coil (46
2) and a second coil (460) and (464) with a third terminal and a fourth terminal and a center terminal, the first terminal (462) being connected to the dither drive signal (462) The second terminal is connected to the ground point, and the center terminal is the voltage supply means (48
0), the third terminal is connected to the first source and the fourth terminal is connected to the second source; and d. The third terminal and the central terminal. 20. A direct dither driver according to claim 19, comprising a first diode (454) connected between the second diode (456) and e. A second diode (456) connected between the fourth terminal and the center terminal. . 36. A direct dither drive device for a laser gyro having a dither gyro block with a dither motor and a dither pickoff, comprising: a. Amplification means having an analog dither signal output (205) and connected to the dither pickoff (244A). (202) and (204)
And; b. A means (206) for converting an analog dither signal into a digital dither signal (207A); and c. A count reference displacement signal in digital volt reference by multiplying the digital dither signal (207A) by a predetermined scale factor. Means for converting to a displacement signal (215); d. Means for subtracting the digital volt reference displacement signal from the digital dither signal to generate a differential displacement signal (208); e. Introducing random noise to the differential displacement signal. Means for generating a digital drive signal (210); f. Means for converting the digital drive signal into a pulse width modulated signal (216); g. Means for driving a dither motor in response to the pulse width modulated signal (500 ) And a direct dither drive. 37. Means (500) for driving a dither motor
Drives the first dither leg (470) with the first pulse width modulated signal and drives the second dither leg (472) to the second.
37. The direct dither driver of claim 36, further comprising high speed output logic means (216) for driving with the pulse width modulated signal of. 38. Means (10) for converting a digital drive signal.
0) supplies the first pulse width modulation dither drive signal (470) and the second pulse width modulation dither drive signal (472),
And means for driving the dither motor include: a. Having a first gate, a first source and a first drain, the first gate being connected to a first pulse width modulated dither drive signal (470); A first transistor means (450) having a first drain connected to ground; and b. A second gate, a second source, and a second drain. A second transistor means (452) whose gate is connected to a second pulse width modulated dither drive signal (472) and whose second drain is connected to ground; c. First terminal and second The first coil with the terminals of (46
2) and second coils (460) and (464) with third and fourth terminals and a center terminal, the first terminal (462) being connected to the dither drive signal, The second terminal is connected to the ground point, the center terminal is connected to the voltage supply means (480), the third terminal is connected to the first source, and the fourth terminal is connected to the second source. A first inducing means (480); d. A first diode (454) connected between the third terminal and the central terminal; and e. A first diode connected between the fourth terminal and the central terminal. 37. A direct dither driver according to claim 36, comprising two diodes (456).