JP3501872B2 - Plasma etching method for semiconductor substrate - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for plasma etching a semiconductor substrate. 2. Description of the Related Art In order to form an element pattern of a silicon micromachining type sensor such as a pressure sensor which is a semiconductor chip, only a portion where a concave portion is desired is opened on a surface to be etched of a silicon wafer which is a semiconductor substrate. The formed etching mask is formed of a chrome film or the like, and only the silicon whose opening is exposed is removed by etching to form a desired concave portion. Among these etching methods, plasma etching which is anisotropic and has a good selectivity is widely used. In plasma etching, high-frequency power is applied to a reaction gas in a reaction vessel to generate a plasma of the reaction gas, and active species and reactive ions (hereinafter referred to as active species and the like) in the plasma and physical chemistry of silicon. The etching is performed by a reactive reaction. FIG. 5 shows an external view of a silicon wafer to be etched, in which a silicon wafer 1 having a diameter of, for example, about 100 mm is coated with an etching mask 2 on a surface to be etched. Silicon wafer 1 is a number
Except for a peripheral edge having a width of mm, the area is a semiconductor chip formation area where a plurality of semiconductor chips are formed. The periphery is susceptible to dust, and part of the periphery is covered with a locking member for fixing a silicon wafer to a processing chamber of a film forming apparatus or the like, which is not suitable for forming a semiconductor chip. From the semiconductor chip non-forming region. A part of the edge of the wafer forms an orientation flat (hereinafter, referred to as an orientation flat) forming portion 11 necessary as a guide for alignment in a lithography process or the like. The etching mask 2 is provided on a portion covering the semiconductor chip formation region by a concave pattern to be obtained by etching.
The openings corresponding to the wafer shape are repeatedly formed vertically and horizontally at a chip interval of several mm, and a large number of semiconductor chips are formed from one silicon wafer. In order to improve the yield by aligning the device characteristics of a large number of semiconductor chips, it is necessary to make the amount of etching in the wafer uniform, and to reduce the variation in the amount of etching, and hence the etching rate in the wafer,
They are working hard. For example, etching conditions such as the degree of vacuum in the reaction vessel, the distance between electrodes for applying high-frequency power, the composition of the reaction gas, and the applied power have been studied and improved, and the etching conditions are based on the inspection results of the silicon wafer after etching. This is reviewed so that the variation in the etching rate within the wafer does not increase. FIG. 8 shows a typical in-wafer distribution of an etching rate in a semiconductor chip formation region when a silicon wafer is etched by plasma etching, and the periphery of the semiconductor chip formation region tends to be higher in all radial directions. Even if the above etching conditions are examined,
The fact was that it varied by 5%. The above isotropic tendency is
Since the reaction gas flows along the peripheral wall of the reaction vessel, the density of active species and the like in the plasma increases around the silicon wafer, and the high-frequency electric field between the electrodes concentrates around the silicon wafer and the surface of the silicon wafer of the active species and the like It is caused by a large impact on Japanese Patent Application Laid-Open No. 3-266473 discloses that the problem that the thickness of a silicon wafer is reduced due to over-etching at the outer peripheral portion of a semiconductor substrate having a high etching rate and the strength of the silicon wafer is reduced is described as an opening area of an etching mask having a larger opening area. Focusing on the fact that the etching rate is reduced, the opening of the portion of the etching mask that covers the outside of the silicon wafer is made larger by reducing the etching rate and preventing the strength of the silicon wafer from being reduced. Is disclosed. As a measure to alleviate the tendency of the etching rate in the wafer to suppress the variation in the etching rate, as shown in FIG. 6, an opening of the etching mask 2 covering the silicon wafer 1 is formed on the entire surface including the outer peripheral portion. Then, a surplus amount of the reaction gas flowing along the peripheral wall of the reaction vessel and flowing into the wafer is consumed in the chip non-formation region (hereinafter, referred to as an overall etching method), or an etching mask as shown in FIG. A method of disposing an electric field correction ring 8 made of a material such as quartz having a similar component to the silicon wafer around the silicon wafer coated with the silicon wafer 2 and keeping the concentration of the high-frequency electric field away from the periphery of the silicon wafer to the outside (hereinafter, referred to as the , Electric field correction method). FIG. 9 shows the distribution of the etching rate in the semiconductor chip formation region in the wafer when the above-described entire surface etching method is performed, and FIG. 10 shows the distribution in the wafer when the above-described electric field correction method is performed. Although the difference in the etching rate between the inside of the wafer and the outside of the wafer is clearly reduced from the figure, the radial direction perpendicular to the orientation flat forming portion is shown in FIG.
(B), as shown in FIG. 10 (B), there is a tendency that the etching rate is higher at a position closer to the orientation flat forming portion, and in the countermeasure by the electric field correction method, the etching speed is at a position closest to the orientation flat forming portion. It has dropped sharply and is not a satisfactory measure. As described above, the conventional measures have a certain effect on the isotropic tendency of the etching rate distribution, but as described above, the anisotropic tendency due to the influence of the orientation flat forming portion and the like. Was not a sufficient measure. Accordingly, the present invention provides a plasma etching method capable of controlling the etching rate in each part of the semiconductor substrate to reduce the anisotropic tendency in the semiconductor substrate and to reduce the variation in the etching rate in the semiconductor substrate. The purpose is to provide. [0009] The present invention SUMMARY OF THE INVENTION As shown in FIG. 1, one surface of the semiconductor substrate 1, upon covered with an etching mask 2 having a plurality of openings for the plasma etching, the A semiconductor chip non-forming region surrounding the periphery of the semiconductor chip forming region together with the semiconductor chip forming region of the semiconductor substrate 1 is covered with the etching mask 2, and a part of an outer peripheral portion of the etching mask covering the semiconductor chip non-forming region. , the peripheral edge of the semiconductor substrate 1 Oriente - in part or near the corresponding Deployment flat forming portion 11, the semiconductor substrate by forming a slit 21
The opening area is enlarged as compared with the other part of the peripheral edge of the semiconductor chip, and the etching rate of the peripheral part of the semiconductor chip formation region corresponding to the above part is reduced . In the plasma etching method for a semiconductor substrate according to the present invention, as shown in FIG. 2, active species of plasma P contributing to etching enter the many openings of the etching mask 2 and are exposed. The substrate 1 is removed by etching to form a concave portion. At this time, a part 2B of the outer peripheral portion of the etching mask 2 covering the semiconductor chip non-formation region, the opening area of which is enlarged, is the surface area of the semiconductor substrate 1 which is more exposed than the other unexpanded outer peripheral portion 2A. Because of this, the consumption rate of the active species and the like is relatively high, and the density of the active species and the like decreases in the part 2B where the opening area is enlarged, and accordingly, many active species and the like flow from the surrounding 2A. I do. Therefore, the density of the active species and the like in the surrounding area 2A also decreases. As a result, the etching rate at the peripheral portion of the chip forming region, which is a part of the peripheral portion 2A of the peripheral portion of the semiconductor chip forming region, which corresponds to the portion having the enlarged opening area, decreases. FIG. 3 is a schematic view of a parallel plate type dry etching apparatus of the anodic bonding type used in the embodiment of the present invention. A high-frequency application electrode (cathode) 4 is provided near the center in the reaction vessel 3.
And a high frequency is applied to the high frequency applying electrode 4 from a high frequency power supply 5. A reaction gas inlet 6 is connected to the upper end of the high frequency application electrode 4, and the reaction gas introduced into the reaction vessel 3 through the introduction port 6 is supplied to a gas outlet 41 provided on the bottom surface of the high frequency application electrode 4. More shower
It blows out like a shape. A substrate installation electrode (anode) 5 is disposed on the bottom surface of the reaction vessel 3 so as to face the high-frequency application electrode 4, and the substrate installation electrode 5 is grounded. The semiconductor substrate 1 is placed on the upper surface of the substrate mounting electrode 5 with the surface to be etched facing upward. An etching surface of a semiconductor substrate 1 is covered with an etching mask 2. A reaction gas exhaust port 7 is provided on the bottom surface of the reaction vessel 3, and the inside of the reaction vessel 3 is maintained at the set pressure of the gate valve by a gate valve (not shown) and a vacuum exhaust system communicating therewith. . The reaction gas is introduced into the reaction vessel 3 by a flow controller (not shown), and a high frequency power is applied from a high frequency power supply 5 to generate a plasma P. Then, the semiconductor substrate 1 from which many openings of the etching mask 2 are exposed,
Etching is removed by a physicochemical reaction between the active species of the plasma P and the like to form a desired concave portion. Using the above apparatus, the etching method of the present invention was carried out. For comparison, the entire surface etching method and the electric field correction method were performed. The effect of reducing the tendency of the etching rate to become higher toward the orientation flat due to the influence of the orientation flat forming portion was examined. The semiconductor substrate subjected to the etching of the present invention is a silicon wafer 1 having a diameter of 101 mm (4 inches) as shown in FIG. A region having a diameter of about 94 mm was defined as a semiconductor chip formation region, and the periphery thereof was defined as a semiconductor chip non-formation region. After the etching mask 2 covering the surface to be etched is coated with chromium by sputtering film formation,
Approximately 1,000 openings were arranged and formed at equal intervals vertically and horizontally on the entire surface. Orientation flat forming part 1 around etching mask 2
0.3mm width, 30mm length, radius of curvature 4
An arc-shaped slit 21 of 7.5 mm was formed along the semiconductor chip formation region to increase the opening area. The etching mask 2 was manufactured by a film forming process and a lithography process in the same manner as an etching mask used in ordinary plasma etching. At this time, in the lithography process, the pattern transfer of the slit, which is a means for enlarging the opening area, was performed by the same exposure with a single exposure mask together with the pattern transfer of the element pattern of the semiconductor chip. . An electric field correction ring is provided around the silicon wafer 1. It is made of quartz and has an outer diameter of 120 mm and an inner diameter of 1 mm.
The inner shape is 01 mm, and is shaped according to the orientation flat forming portion 11 of the silicon wafer 1. The semiconductor substrate subjected to the etching by the whole surface etching method is a silicon wafer having the same specification as that of the present embodiment, and is coated with chromium as an etching mask by sputtering in the same manner as in this embodiment. Are arranged and formed at equal intervals in the vertical and horizontal directions. The semiconductor substrate subjected to the etching by the electric field correction method is a silicon wafer having the same specification as that of the present embodiment, and is coated with chromium as an etching mask by sputtering in the same manner as in this embodiment. Openings are arranged and formed at equal intervals vertically and horizontally only in the portion covering the chip formation region, as in the present embodiment. At the time of etching, an electric field correction ring was provided around the silicon wafer. It is made of quartz and has an outer diameter of 120 mm, an inner diameter of 101 mm, and an inner shape formed in accordance with the orientation flat forming portion of the silicon wafer. Including the present embodiment, a mixed gas of sulfur hexafluoride (SF ₆ ) and oxygen (O ₂ ) (mixing ratio SF ₆ : O ₂ = 65: 3) is commonly used for the three types of etching.
5) using a gas flow rate of 10 sccm per liter of the reaction vessel,
Deep digging with an etching amount of 300 μm or more was performed at a gas pressure of 0.3 torr and an applied power of 1.8 W / cm ² per unit area of the electrode, and the etching rate distribution in the semiconductor chip formation region was measured. FIG. 4 shows the etching result of the present invention. FIG. 4B shows the distribution of the etching rate in the direction perpendicular to the orientation flat forming portion in comparison with FIG. 9B showing the result when the entire surface etching method is performed. It is relaxed and uniform.
In addition, when FIG. 4B is compared with FIG. 10B which shows the result when the above-described electric field correction method is performed, the tendency of the orientation flat to become higher is clearly reduced. At the same time, the characteristic characteristic of the electric field correction method in which the etching rate sharply decreases at the position closest to the orientation flat forming portion has been alleviated. This is considered to be an effect of not synergizing with the action of lowering the etching rate at the position. In addition, FIG. 9A shows the result of the above-described overall etching method for the etching rate distribution in the direction parallel to the orientation flat forming portion, and FIG. 9A shows the result of the above-described electric field correction method. Compared to 10 (A), the etching rate distribution in the direction parallel to the orientation flat has no adverse effect. At this time, the in-wafer variation of the etching rate of the present invention was ± 1.5%. From this fact, the etching rate tends to be higher on the orientation flat side because the etching rate tends to be higher on the orientation flat side, by forming the arc-shaped slit in a portion corresponding to the orientation flat forming portion, the active species on the orientation flat forming portion side of the chip forming region. It can be seen that there is an effect of lowering the density of the wafer and lowering the etching rate to reduce the variation in the etching rate in the wafer. In this embodiment, slits are formed on the outer periphery of the etching mask on the left and right sides of the orientation flat forming portion.
According to the tendency of the etching rate in the wafer in the chip formation region, the semiconductor chip formation region may be formed at a portion corresponding to a portion where the etching rate is to be reduced. For example, since the above etching conditions are limited by the demand for prevention of surface roughness of the silicon wafer and suppression of side etching, etc., when there is an anisotropic tendency of the etching rate in the wafer and there is a height difference, What is necessary is just to form in the part corresponding to the said high etching rate part. In this embodiment, as a means for expanding the opening area, the slit is formed in an arc shape, but the shape may be a straight line or a polygon, or a plurality of small openings may be arranged along the arc of the semiconductor substrate. . Alternatively, instead of forming the slits and the like, the side wall of the opening at that position may be retracted to make the opening area larger than the opening at another position. The production of the etching mask is not limited to the production method described in this embodiment, and the slit and the element pattern of the semiconductor chip may be separately transferred.
The transfer of the element pattern of the semiconductor chip may be performed by reduction projection exposure or the like. As described above, according to the present invention, when performing plasma etching, the opening area is enlarged at a part of the outer peripheral portion of the etching mask covering the semiconductor chip non-forming region, and the chip formation corresponding to the above part is formed. It is possible to reduce the etching rate in the peripheral portion of the region, thereby reducing the variation in the etching rate in the wafer.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a view for explaining an etching method of the present invention. FIG. 2 is a diagram illustrating the operation of the etching method of the present invention. FIG. 3 is a schematic view of an etching apparatus used to carry out the etching method of the present invention. FIG. 4A is a graph showing the distribution of the etching rate in the radial direction parallel to the orientation flat forming portion when the etching method of the present invention is used, and FIG. It is a graph which shows distribution in a perpendicular radial direction. FIG. 5 is a diagram illustrating a conventional etching method. FIG. 6 is a diagram illustrating another conventional etching method. FIG. 7 is a diagram illustrating still another conventional etching method. FIG. 8 is a graph showing a distribution of an etching rate in a wafer when a conventional etching method is used. FIG. 9A is a graph showing a distribution of an etching rate in a radial direction parallel to the orientation flat when another conventional etching method is used, and FIG. 9B is a graph showing a diameter perpendicular to the orientation flat; It is a graph which shows distribution of a direction. FIG. 10A is a graph showing the distribution of the etching rate in the radial direction parallel to the orientation flat when another conventional etching method is used, and FIG. 10B is a graph showing the distribution perpendicular to the orientation flat; It is a graph which shows distribution in a radial direction. [Description of Signs] 1 Silicon wafer (semiconductor substrate) 11 Orientation flat forming part 2 Etching mask 21 Slit

──────────────────────────────────────────────────続 き Continuing on the front page (72) Muneo Yorinaga, 14 Iwatani, Shimowasumi-cho, Nishio-shi, Aichi Japan (72) Inventor Takeshi Fukada 1-1-1, Showa-cho, Kariya-shi, Aichi Japan Japan (56) References JP-A-3-266473 (JP, A) JP-A-64-55826 (JP, A) JP-A-60-201632 (JP, A) (58) Fields investigated (Int .Cl. ⁷ , DB name) H01L 21/3065 H01L 29/84

Claims (1)

(57) one side of the Claims 1 semiconductor substrate, when coated with an etching mask having a large number of openings for the plasma etching, the semiconductor chip with the semiconductor chip formation regions of the semiconductor substrate a semiconductor chip non-forming region surrounding the periphery of the formation area covered with the etching mask, a part of the etching mask outer peripheral portion that covers the semiconductor chip non-forming region, Oriente peripheral edge of the semiconductor substrate - Deployment flat forming portion in corresponding parts or near the other peripheral edge of the semiconductor substrate by forming a slit
A plasma etching method for a semiconductor substrate, characterized in that an opening area is enlarged as compared with a portion and an etching rate of a peripheral portion of a semiconductor chip formation region corresponding to the portion is reduced.