JP3515328B2 - Wafer check method - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a wafer checking method.
With regard to the
The present invention relates to a wafer check method for a black computer.

[0002]

2. Description of the Related Art Looking at a recent one-chip microcomputer, there is an increasing tendency to incorporate an EEPROM (flash memory) instead of a mask ROM as a non-volatile memory for storing program data. this is,
This is because the EEPROM has characteristics that the mask ROM does not have. For example, when the function of the one-chip microcomputer is changed, if a mask ROM is used, a new mask has to be designed and manufactured, which causes a problem that the development cost becomes high and the development period becomes long. On the other hand, if the EEPROM is used, new program data can be written by using a PROM writer or the like after electrically erasing old program data, so that development cost can be suppressed and development period can be shortened.

FIG. 6 is a diagram showing a structure of a cell portion (for example, 2 bits) of the EEPROM having the above characteristics. 6, 1 and 2 are M with a floating gate
It is an OS transistor. The MOS transistor 1,
Reference numerals 2 correspond to 1-bit cells, the gates are connected to the word lines WL1 and WL2, the drains are commonly connected to the bit lines BL, and the sources are commonly connected to the source lines SL (always 0 volt). 3 is a sense amplifier, which compares the reference current with the current of the bit line BL,
It outputs a logical value "1" or "0".

For example, the control voltage V is applied to the word line WL1.
When H (for example, 4 V) is applied, the cell current flows through the MOS transistor 1 and the current of the bit line BL becomes larger than the reference current, so that the sense amplifier 3 outputs the logical value “1”. On the other hand, when the control voltage VH is applied to the word line WL1, the MOS transistor 1 is turned off if it is in the programmed state, the cell current does not flow through the MOS transistor 1, and the current of the bit line BL becomes smaller than the reference current. , The logical value “0” is output from the sense amplifier 3. The MOS transistor 2
Works similarly. That is, if the selected MOS transistors 1 and 2 are in the erased state, each bit value is the logical value "1".
When the MOS transistors 1 and 2 are in the programmed state, each bit value becomes EEPR
The OM is configured.

The technique relating to the one-chip microcomputer described above is disclosed in Japanese Patent Application No. 9-55 filed by the present applicant.
It is described in the specification attached to No. 169. Less than,
The pad arrangement of the one-chip microcomputer will be described with reference to FIG. FIG. 7 is a diagram showing a layout of the above-described 1-chip microcomputer, 5 is a core circuit block on the microcomputer side, and 6 is a core circuit block on the non-volatile memory (EEPROM and mask ROM) side. A large number of pads 7 are arranged on four sides of the peripheral portion surrounding the core circuit block 5 on the microcomputer side and the core circuit block 6 on the nonvolatile memory side, and each pad 7 has terminals for nonvolatile memory and The microcomputer terminals are randomly arranged.

The wafer check by the LSI tester in the shipping inspection of the one-chip microcomputer described above will be described below. The wafer check process is performed in a conventionally well-known procedure, so a brief description will be given. First, the first
In the measurement step, the data of the non-volatile memory is judged using the logic tester. Then, after passing through a baking process for a data retention acceleration test, in the second measurement process, the logic data tester is used to determine the data retention state of the nonvolatile memory and the function of the microcomputer. It was

[0007]

[Problems to be Solved by the Invention]
When a non-volatile memory is judged by using the logic tester in the first measurement step, as described above, at the time of wafer check by the SI tester, there is a memory specific measurement, and if it is judged by the logic tester, the measurement time There was a problem that was very long. Further, when the determination is performed using only the memory tester, there is a problem that complicated measurement peculiar to the microcomputer cannot be performed.

Therefore, at the sacrifice of shortening the measurement time, the measurement by the logic tester is performed in both the first and second measurement steps. Further, as shown in FIG. 7, the nonvolatile memory terminals and the microcomputer terminals are randomly arranged on the four-direction pads, so that it is impossible to simultaneously measure a plurality of chips. That is, as shown in FIG. 8, the pad 7 to which the non-volatile memory terminal is connected
Is indicated by a pad 7A, for example, since the pad 7A is randomly arranged on a pad in four directions, it is necessary to associate the needle 8A of the probe card with each pad 7A arranged in four directions. On the other hand, only one chip could be measured, a plurality of chips could not be measured simultaneously, and the measurement time could not be shortened.

Therefore, the present invention provides a pad arrangement method for realizing the rationalization of the measurement method capable of simultaneously measuring a plurality of chips in the measurement method of the one-chip microcomputer.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional drawbacks, and is a pad arrangement method for a one-chip microcomputer incorporating a nonvolatile memory composed of an EEPROM capable of rewriting data as a program memory. In the above, by arranging the pads for the non-volatile memory on the two opposite sides and arranging the pads for the microcomputer on the other two opposite sides, it is possible to simultaneously measure a plurality of chips.

Further, in order to carry out a retention test of the data programmed in the non-volatile memory, when performing the wafer check twice, in the first measuring step, the data determination in the non-volatile memory is performed using the memory tester. After the baking step for the retention acceleration test, in the second measurement step, the data in the nonvolatile memory is determined using the logic tester as in the conventional case, and the function determination of the microcomputer is performed. By using a memory tester instead of the logic tester used in the conventional first measurement process, the total measurement time can be shortened.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION A general one-chip microcomputer incorporating a nonvolatile memory to which the present invention is applied will be described below with reference to the drawings. First, Fig. 1
Is a non-volatile memory (E
EPROM), and the EEPROM 11 has a program area 1 as shown in FIG.
2, composed of a data area 13 and a control circuit 14, 1
Reference numeral 5 denotes a core unit including, for example, a CPU and an I / O port.

FIG. 2 shows a plurality of EEPROMs 17 and 1 independent of the one-chip microcomputer shown in FIG.
8, a first EEPROM 17 has a program area 19 and a control circuit 20, and a second EE
The PROM 18 has a configuration including a data area 21 and a control circuit 22, and 23 is a core section. Further, FIG. 3 has an EEPROM 24 as a first non-volatile memory and a mask ROM 25 as a second non-volatile memory, and the EEPROM 24 has a first program area 26,
With the configuration including the data area 27 and the control circuit 28, the mask ROM 25 becomes the second program area 29.
0 is a core part.

The EEPR is stored in the mask ROM 25.
A data rewriting program for the OM 24 is stored. Further, only the data rewriting program of the EEPROM 24 required by all users is installed in the mask ROM 25, and rewriting by the users is impossible. The pad arrangement method of the present invention applied to the above-described one-chip microcomputer will be described below with reference to the drawings.

FIG. 4 is a diagram showing the layout of the one-chip microcomputer of the present invention. Reference numeral 31 is a core circuit block on the microcomputer side, and 32 is a core circuit block on the nonvolatile memory side. The nonvolatile memory included in the core circuit block 32 on the nonvolatile memory side includes the above-mentioned EEPROM 11 (see FIG. 1), the first and second EEPROMs 17 and 18 (see FIG. 2), and the first nonvolatile memory. An EEPROM 24 as a memory and a mask ROM 25 (see FIG. 3) as a second non-volatile memory. A large number of pads 33 are arranged on four sides of the peripheral portion surrounding the core circuit block 31 on the microcomputer side and the core circuit block 32 on the nonvolatile memory side.

The pad arrangement method of the present invention is characterized in that the pads 33 are arranged on four sides of the peripheral portion surrounding the core circuit block 31 on the microcomputer side and the core circuit block 32 on the non-volatile memory side. The pads 33A arranged on the two opposite sides are pads for the non-volatile memory terminals, and the pads 33B arranged on the other two opposite sides are pads for the microcomputer terminals.

As described above, according to the present invention, the pad 33A for the non-volatile memory terminal and the pad 33B for the microcomputer terminal are separately arranged on the two opposite sides. As described above, according to the present invention, the non-volatile memory terminal pad 33A and the microcomputer terminal pad 33B are arranged on two opposing sides, respectively, so that a plurality of chips are arranged at the same time as shown in FIG. The measurement can be performed, and the measurement time per chip can be shortened. Incidentally, 34 is a window of the probe card, and 35 is a needle of the probe card, through which signals are exchanged with the LSI tester. Therefore,
Depending on the size of the window 34 of the probe card described above, it is possible to perform simultaneous measurement up to the allowable size (FIG. 5 shows the simultaneous measurement state of data in the nonvolatile memory by a memory tester (not shown) for two chips. ing.).

The wafer check by the LSI tester in the shipping inspection of the above-mentioned one-chip microcomputer will be described below. First, in the first measurement step, data determination of the nonvolatile memory is performed using the memory tester. continue,
After the baking process for the data retention acceleration test, in the second measurement process, the data retention of the above-mentioned nonvolatile memory is determined using the logic tester and the function of the microcomputer is determined.

As described above, in order to carry out the retention test of the data written in the non-volatile memory, when performing the wafer check twice, in the first measurement step, the memory tester as shown in FIG. 5 is used. The data of the nonvolatile memory is determined by using the logic tester (not shown) in the same manner as the conventional method in the second measurement step after the baking step for the retention acceleration test. By determining the function of the microcomputer, the total measurement time can be shortened by using the memory tester dedicated to the memory instead of the logic tester used in the conventional first measurement process. Note that the chip shown in FIG.
It is possible to measure a plurality of chips at the same time by performing the measurement in a state where the chips are rotated once.

[0020]

As described above, according to the present invention, 1
In the pad arrangement method of the chip microcomputer, by arranging the pads for the non-volatile memory on the two opposite sides and arranging the pads for the microcomputer on the other two opposite sides, simultaneous measurement of a plurality of chips is possible. Therefore, the measurement time per chip can be shortened.

Further, in order to perform the retention test of the data written in the non-volatile memory, when performing the wafer check twice, the first measurement step uses the memory tester to judge the data in the non-volatile memory. After the baking process for the holding acceleration test, in the second measurement process, the data in the nonvolatile memory is determined using the logic tester as in the conventional case, and the function of the microcomputer is determined. By using a memory tester instead of the logic tester used in the conventional first measurement process, and by simultaneously measuring a plurality of chips, the total measurement time can be shortened.

[Brief description of drawings]

FIG. 1 is a diagram showing a general one-chip microcomputer to which the present invention is applied.

FIG. 2 is a diagram showing a general one-chip microcomputer to which the present invention is applied.

FIG. 3 is a diagram showing a general one-chip microcomputer to which the present invention is applied.

FIG. 4 is a diagram showing a pad layout of the one-chip microcomputer according to the embodiment of the present invention.

FIG. 5 is a diagram showing a wafer check state of the one-chip microcomputer according to the embodiment of the present invention.

FIG. 6 is a diagram showing a structure of an EEPROM applied to a conventional one-chip microcomputer.

FIG. 7 is a diagram showing a pad layout of a conventional 1-chip microcomputer.

FIG. 8 is a diagram showing a wafer check state of a conventional one-chip microcomputer.

─────────────────────────────────────────────────── ─── Continued Front Page (51) Int.Cl. ⁷ Identification Code FI H01L 21/822 G01R 31/28 V 21/8247 H01L 27/04 E 27/04 27/10 434 27/10 461 27/115 ( 72) Inventor Katsumi Tachikawa 2-5-5 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd. (56) Reference JP 61-97957 (JP, A) JP 4-23354 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/66 G01R 31/28 G06F 15/78 510 H01L 21/822 H01L 21/8247 H01L 27/04 H01L 27/10 461 H01L 27 / 115

Claims (2)

(57) [Claims] 1. A one-chip memory incorporating a non-volatile memory.
In the wafer checking method of black computer,
Memory pads are placed on two opposite sides of the chip
The pad for the microcomputer facing the chip.
Place it on the other two sides and use a memory tester to
First measurement step for measuring the data determination of the memory
And then baking for accelerated data retention test
Process, and then using the logic tester
Measure the data retention judgment of the memory and
The second measurement engineer that measures the function judgment of the black computer
And in the first or second measurement step,
Non-volatile memory of multiple chips using probe card
Or, it is characterized by measuring the microcomputer simultaneously
Wafer check method. 2. The non-volatile memory is an EEPROM.
The method for checking a wafer according to claim 1, wherein
Law.