JP3515374B2 - Serial data transfer device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a serial data transfer device for serially transferring data in synchronization with a clock, and more particularly, to transmitting a command to a plurality of controlled circuits simultaneously. The present invention relates to a serial data transfer device in which the transfer time is shortened when adding. 2. Description of the Related Art A TV receiver or a home VTR has a plurality of ICs therein, and these ICs may be controlled by a single controller (microcomputer). There are serial and parallel control methods, but the serial method is often adopted because the number of lines is small. In the serial method, a start signal, a slave address signal, transfer data, a stop signal, and the like are created using a combination of logical values of “H” and “L” of data and a clock, and one cycle includes the plurality of signals. To use repetitive signals. Various information is added to the transfer data. FIG. 2 shows data and a clock of such a serial data transfer device of the serial type. FIG. 2A shows the data in FIG.
(B) shows a clock. Time t1 indicates a start point, and time t2 indicates a stop point. During this time, necessary transfer data exists. [0003] A start point is when data changes from "H" to "L" when the clock is "H". The stop point is when the data is "L" when the clock is "H".
It is time to change to "H". Then, by reading the value of the data at the falling edge of the clock (for example, t3), the data is captured. When one transfer data ends, a stop signal is generated to notify the end of the data transfer. Then, when the next start signal arrives, the next transfer data is sent. However, the serial method has a problem that it takes a long time to send an instruction to a plurality of ICs at the same time because it is serial. For example, in a home VTR, a plurality of ICs (for example, a main YC signal processing IC, a head amplifier IC,
Although there is an equalizer IC), the instructions are executed after all the instructions arriving at each IC arrive. However, in such a case, since the timing of the latest one is used as a reference for the whole, the transfer takes a long time as a result. SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and is a serial data transfer device for transferring data serially, wherein first and second serial data are applied. An input terminal, a first temporary memory for temporarily storing first serial data from the input terminal, a first memory for storing data from the first temporary memory, and the input terminal. A second temporary memory for temporarily storing second serial data from the second memory, a second memory for storing data from the second temporary memory, and the first serial data from the input terminal. A first transfer state detection circuit that generates a first control signal indicating that transfer to the first temporary memory is in progress, and the second serial data from the input terminal is transferred to the second temporary memory. During transfer A second control signal for generating a second control signal indicating that
A transfer state detecting circuit for determining whether the first control signal has not arrived when a vertical synchronizing signal in a video signal has arrived, and transferring data from the first temporary memory to the first memory. And a control circuit for determining that the second control signal has not arrived when the vertical synchronization signal has arrived, and for transferring data from the second temporary memory to the second memory. Wherein the first serial data is the first serial data in response to the vertical synchronization signal.
, And the second serial data is transferred to the second memory. FIG. 1 shows a serial data transfer device according to the present invention, wherein 1 is an input terminal to which serial data is applied, and 2 is a device for temporarily storing serial data from the input terminal 1. A first temporary memory for temporarily storing data from the first temporary memory 2; a second temporary memory for temporarily storing serial data from the input terminal 1; A memory 5 is a second memory for storing data from the second temporary memory 4, a reference numeral 6 is a first control signal A1 indicating that serial data from the input terminal 1 is being transferred, and A first transfer state detection circuit for generating a second control signal B1 indicating that data transfer has been completed; and a third control signal indicating that serial data from the input terminal 1 is being transferred. A2,
A second transfer state detection circuit for generating a fourth control signal B2 indicating that the transfer of the serial data has been completed;
Reference numeral 0 denotes a synchronization separation circuit that separates a vertical synchronization signal from a video signal from a terminal 9. Reference numeral 8 denotes the first and third control signals A1, A when the vertical synchronizing signal from the synchronizing separation circuit 50 arrives.
2 is determined not to have arrived, the data from the first temporary memory 2 is transferred to the first memory 3, and the data from the second temporary memory 4 is transferred to the second memory 5. A control circuit for transferring data, 10 is a switch that opens and closes according to the output signal of the control circuit 8, 11 is a switch that opens and closes according to the output signal of the control circuit 8, and 12 is a home VT
Equalizer I used for recording / reproducing processing of R video signal
Reference numerals C and 13 denote YC signal processing ICs used for recording and reproducing video signals of a home VTR. In the apparatus shown in FIG. 1, the mode of the equalizer IC of the home VTR and the mode of the YC signal processing IC are switched according to the Cyril data. The serial data in that case has a form as shown in FIG. That is, the data D2 includes the YC signal processing I
The C information and the data D1 include equalizer IC information. Mode information such as recording and reproduction is included as data commonly included in the data D1 and D2. When this mode is switched, a switch composed of a transistor or the like in the IC is switched, so that DC fluctuation is likely to occur. Then, the DC fluctuation appears in the video signal as noise. Therefore, in the present invention, data transfer is performed, and a vertical synchronization signal period not displayed on the screen is used as the transfer period. A horizontal synchronization signal period may be used as long as the period is not displayed on the screen. During this period, even if noise occurs, it does not appear on the screen. The input terminal 1 of FIG.
(A) Serial data is applied. The serial data is stored in the first temporary memory 2 and the second temporary memory 4 serially. The serial data is applied to the first transfer state detection circuit 6 and the second transfer state detection circuit 7. The first transfer state detection circuit 6 decodes the serial data and applies a pulse A1 (FIG. 3B) indicating that the data D1 is being transferred to the first temporary memory 2. Then, the first temporary memory 2 starts storing the serial data from the input terminal 1. The first transfer state detecting circuit 6 decodes the serial data and applies a pulse B1 indicating that the data transfer is completed to the first temporary memory 2. Then, the first temporary memory 2 stops storing the serial data from the input terminal 1. The second transfer state detection circuit 7 performs the same operation, and applies the pulse A2 shown in FIG. 3 (c) to the second temporary memory 4. Then, the second temporary memory 4 stores the input terminal 1
To start storing the serial data. Further, the second transfer state detection circuit 7 decodes the serial data and applies a pulse B2 indicating that the data transfer is completed to the second temporary memory 4. Then, the second temporary memory 4 stops storing the serial data from the input terminal 1. The first transfer state detection circuit 6 and the second transfer state detection circuit 7 decode incoming serial data, and can determine to which block the contents are transferred. Therefore, when data D1 arrives,
The first temporary memory 2 operates so that the data is transmitted to the equalizer IC 12, and when the data D2 arrives,
Secondly, the data is transmitted to the YC signal processing IC 13.
The temporary memory 4 operates. In this manner, the data D1 and D2 transferred serially are stored in the first temporary memory 2 and the second temporary memory 2.
Is temporarily stored in the temporary memory 4. It is assumed that a video signal including a vertical synchronizing signal arrives at the terminal 9 from this state. This vertical synchronizing signal is transferred from the temporary memory to the original memory (the first memory 3 and the like). The vertical synchronizing signal is asynchronous in timing with the data D1 and data D2. Therefore, a transfer command is issued while the serially transferred data D1 and data D2 are being written to the first temporary memory 2 and the second temporary memory 4. First temporary memory 2 and second temporary memory 4
If the transfer is performed while data is being written to the data, data information is lost. Therefore, in the present invention, when the vertical synchronizing signal arrives in the control circuit 8, it is confirmed that the data transfer period is not in progress, and then the temporary memory is transferred to the original memory (for example, the first memory 3). Transferring. Specifically, the vertical synchronizing signal shown in FIG. 3 (f) is applied to the control circuit 8, and inside thereof,
(G) and (h) pulses are created. In the “H” level period of the pulse of FIG. 3H, it is detected whether the pulse A1 of FIG. 3B is at the “H” level. FIG. 4 shows a specific example of the control circuit 8 of FIG. The vertical synchronization signal shown in FIG. 3F is applied to the terminal 20 shown in FIG. The system control circuit 21 generates a control pulse shown in FIG. 3 (h) and a detection pulse shown in FIG. 3 (g) according to the vertical synchronization signal. The detection pulse includes the first and second pulses.
Transmission or interruption is performed by opening and closing the switches 22 and 23. When the detection pulse is transmitted, the contents of the memory are transferred. The first and second switches 22, 23
The first and second latch discriminating circuits 2 switch the opening and closing of the latch.
4, 25. FIG.
FIG. 3B shows a state in which the control pulse shown in FIG.
It is determined whether the pulse A1 is at the “H” level or the “L” level. The second latch determination circuit 25 is configured as shown in FIG.
When the control pulse of (h) is at the “H” level, FIG.
It is determined whether the pulse A2 is at the “H” level or the “L” level. Now, assuming that the pulse of FIG. 3 (h) is in the “H” level period T1, the pulse A1 in that period is “H”.
Cannot transfer because it is level. Therefore, a control signal for opening the switch 22 is generated from the first latch determination circuit 24. Then, the detection pulse is not transmitted. Further, during the same period T1, the pulse A2 is at the "L" level, so that it can be transferred. Therefore, a control signal for closing the switch 23 is generated from the second latch determination circuit 25. Then, FIG.
The pulse of (j) is transmitted. For this reason, the switch 10 opens according to the control signal from the control circuit 8, and the switch 1
1 closes. If the switch 10 is open as shown, there is no transfer from the temporary memory to the original memory (for example, the first memory 3). At this time, the data immediately before the data D2 is transferred to the second memory 5. Next, when a vertical synchronizing signal at the next timing of FIG. 3 (f) is applied to the control circuit 8, the pulse (period T2) of FIG. 3 (g) detection pulses are created. This figure 3
In the “H” level period of the pulse (period T2) of (h), the pulse A1 in FIG. 3B and the pulse A2 in FIG.
Is at "H" level. In this case, the pulse A1 in FIG. 3B is at the "L" level, and the pulse A2 in FIG. 3C is at the "H" level. Therefore, the first switch 22 is closed and the second switch 23 is opened by the latch determination circuit. for that reason,
3 (i) and 3 (j) are generated from the control circuit 8, and the switch 10 is closed and the switch 11 is opened according to the control signal. Next, when a vertical synchronizing signal at the next timing of FIG. 3F is applied to the control circuit 8, the pulse (period T3) of FIG. 3 (g) detection pulses are created. This figure 3
In the “H” level period of the pulse (h) (period T3), the pulse A1 in FIG. 3B and the pulse A2 in FIG.
Is at "H" level. In this case, since the pulse A1 in FIG. 3B and the pulse A2 in FIG. 3C are both at the "L" level, it is clear that the transfer is not in progress. Therefore, the first and second switches 22 and 23 are closed by the latch determination circuit, and the control signals of FIGS. 3 (i) and 3 (j) are generated from the control circuit 8, and the switches 10 and 11 are turned on in accordance with the control signals. close. When the switches 10 and 11 are closed, the stored data is transferred from the temporary memory to the original memory (for example, the first memory 3). Therefore, the first memory 3 and the second memory 5
Will be transferred. As described above, according to the present invention, the transfer time can be shortened when an instruction is simultaneously applied to a plurality of controlled circuits. In particular, according to the present invention, data cannot be transferred to the original memory during data transfer to the temporary memory, so that data can be transferred reliably. Further, according to the present invention, data can be transferred to each IC by using the vertical synchronizing signal period, and even if mode switching causes switching noise, the screen is not affected.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a serial data transfer device of the present invention. FIG. 2 is a waveform chart for explaining a conventional serial data transfer. FIG. 3 is a waveform chart for explaining the serial data transfer of the present invention. FIG. 4 is a specific circuit diagram of the control circuit 8 of the present invention. [Description of Signs] (1) Input terminal (2) First temporary memory (3) First memory (4) Second temporary memory (5) Second memory (6) First transfer state detection circuit (7) Second transfer state detection circuit (8) Control circuit

Claims (1)

(57) Claims 1. A data a serial data transfer device for transferring serially, an input terminal to which the first and second serial data is applied, first from input terminal A first temporary memory for temporarily storing one serial data; a first memory for storing data from the first temporary memory; and a second memory for temporarily storing second serial data from the input terminal. A second temporary memory for storing data from the second temporary memory; a second memory for storing data from the second temporary memory; and a second memory for storing the first serial data from the input terminal .
A first transfer state detecting circuit for generating a first control signal indicating a way forward to one temporary memory, the second serial data from the input terminal the first
A second transfer state detecting circuit for generating a second control signal indicating that transfer to the temporary memory is in progress, and the first control signal arriving when a vertical synchronization signal in the video signal arrives Is determined, the data from the first temporary memory is transferred to the first memory, and when the vertical synchronization signal arrives, the second
And a control circuit for determining that the control signal has not arrived and transferring the data from the second temporary memory to the second memory .
1 is transferred to the first memory, and
The second serial data is transferred to the second memory.
Serial data transfer device being characterized in that as that.