JP3547999B2 - Serial data transfer device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a serial data transfer device for serially transferring data in synchronization with a clock, and particularly to a serial data transfer device in which transfer timings are made equal when a same instruction is simultaneously applied to a plurality of controlled circuits. Equipment related.
[0002]
[Prior art]
A TV receiver or a home VTR has a plurality of ICs therein, and the plurality of ICs may be controlled by a single controller (microcomputer). There are serial and parallel control methods, but the serial method is often adopted because the number of lines is small. In the serial method, a start signal, a slave address signal, transfer data, a stop signal, and the like are created using a combination of logical values of “H” and “L” of data and a clock, and one cycle includes the plurality of signals. To use repetitive signals. Various information is added to the transfer data.
FIG. 2 shows data and a clock of such a serial data transfer device of the serial type. FIG. 2A shows data and FIG. 2B shows a clock. Time t1 indicates a start point, and time t2 indicates a stop point. During this time, necessary transfer data exists.
[0003]
The start point is when data changes from “H” to “L” when the clock is “H”. The stop point is when data changes from "L" to "H" when the clock is "H". Then, by reading the value of the data at the falling edge of the clock (for example, t3), the data is captured.
[0004]
When one transfer data ends, a stop signal is generated to notify the end of the data transfer. Then, when the next start signal arrives, the next transfer data is sent.
[0005]
[Problems to be solved by the invention]
However, the serial method has a problem that it takes a long time to send an instruction to a plurality of ICs at the same time because the instruction is serial.
[0006]
For example, in a home VTR, it is necessary to simultaneously switch a plurality of ICs (for example, a main YC signal processing IC, a head amplifier IC, and an OSD IC) to a reproduction mode or a recording mode. In this case, there is a problem that a plurality of ICs cannot be operated at the same time if the mode change information is transmitted serially.
[0007]
At present, the mode is formally switched after the mode switching is completed in all ICs.
[0008]
[Means for Solving the Problems]
The present invention has been made in view of the above points, and is a serial data transfer device that serially transfers data, wherein an input terminal to which serial data including first serial data and second serial data is applied, A first temporary memory for temporarily storing first serial data from the input terminal, a first memory for storing data from the first temporary memory, and a second serial data from the input terminal. A second temporary memory for temporarily storing, a second memory for storing data from the second temporary memory, and a first memory indicating that the first serial data from the input terminal is being transferred. A first transfer state detection circuit for generating a control signal; a second transfer state detection circuit for generating a second control signal indicating that the second serial data from the input terminal is being transferred; When the pulse signal for determining the timing arrives, it is determined that the first and second control signals have not arrived, the data from the first temporary memory is transferred to the first memory, and the A control circuit for transferring data from the second temporary memory to the second memory, so that the serial data is simultaneously transferred to the first memory and the second memory in response to the pulse signal. It is characterized by having done.
[0009]
Further, the present invention has been made in view of the above points, and is a serial data transfer device for transferring data serially, wherein an input terminal to which serial data including first serial data and second serial data is applied is provided. A first temporary memory for temporarily storing first serial data from the input terminal, a first memory for storing data from the first temporary memory, and a second serial memory from the input terminal. A second temporary memory for temporarily storing data, a second memory for storing data from the second temporary memory, and a second memory indicating that the first serial data from the input terminal is being transferred. A first transfer state detection circuit for generating a first control signal and a second control signal indicating that the transfer of the first serial data has been completed, and a second transfer of the second serial data from the input terminal. A second transfer state detection circuit for generating a third control signal indicating that the transfer is in progress, and a fourth control signal indicating that the transfer of the second serial data has been completed, and a pulse signal for determining transfer timing Arrives, it is determined that the first and third control signals have not arrived, the data from the first temporary memory is transferred to the first memory, and the data is transmitted from the second temporary memory. And a control circuit for transferring the data to the second memory, wherein the data is simultaneously transferred to the first memory and the second memory in accordance with the pulse signal.
[0010]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 shows a serial data transfer device of the present invention, wherein 1 is an input terminal to which serial data is applied, 2 is a first temporary memory for temporarily storing serial data from the input terminal 1, Reference numeral 3 denotes a first memory for storing data from the first temporary memory 2, 4 denotes a second temporary memory for temporarily storing serial data from the input terminal 1, and 5 denotes a second temporary memory. A second memory 6 for storing data from the fourth terminal 4 has a first control signal A1 indicating that serial data from the input terminal 1 is being transferred, and a second memory 6 indicating that the transfer of the serial data has been completed. A first transfer state detection circuit 7 for generating the second control signal B1; a third control signal A2 indicating that serial data from the input terminal 1 is being transferred; and a transfer end of the serial data. Octopus A second transfer state detecting circuit for generating a fourth control signal B2 indicating a vertical synchronizing signal from a video signal from a terminal 9; Arrives, it is determined that the first and third control signals A1 and A2 have not arrived, the data from the first temporary memory 2 is transferred to the first memory 3, and the A control circuit for transferring data from the temporary memory 4 to the second memory 5 described in the table e4e44f, a switch 10 for opening and closing in response to an output signal of the control circuit 8, and a switch 11 for opening and closing in accordance with the output signal of the control circuit 8 A switch 12, a luminance signal processing block used for recording / reproducing video signals of a home VTR, and a reference numeral 13 denotes a chroma signal processing block used for recording / reproducing processes of a video signal of a home VTR. That.
[0011]
In the apparatus shown in FIG. 1, the control start timings of the luminance signal processing block and the chroma signal processing block of the home VTR are simultaneously set according to the serial data. For example, when changing from the recording mode to the reproduction mode, it is necessary to transfer the information whose mode has been switched and the information (image quality adjustment information) accompanying the information. The serial data in that case has a form as shown in FIG.
[0012]
That is, the data D2 includes chroma information (information on switching modes and image quality adjustment information), and the data D1 includes luminance information (information on switching modes and image quality adjustment information).
[0013]
When the mode is switched as described above, a switch composed of a transistor or the like is switched, so that DC fluctuation is likely to occur. Then, the DC fluctuation appears in the video signal as noise. Therefore, in the present invention, data transfer is performed in parallel, and a vertical synchronization signal period not displayed on the screen is used as the transfer period. A horizontal synchronization signal period may be used as long as the period is not displayed on the screen. During this period, even if noise occurs, it does not appear on the screen.
[0014]
The serial data of FIG. 3A is applied to the input terminal 1 of FIG. The serial data is stored in the first temporary memory 2 and the second temporary memory 4 serially. The serial data is applied to the first transfer state detection circuit 6 and the second transfer state detection circuit 7. The first transfer state detection circuit 6 decodes the serial data and applies a pulse A1 (FIG. 3B) indicating that the data D1 is being transferred to the first temporary memory 2. Then, the first temporary memory 2 starts storing the serial data from the input terminal 1.
[0015]
Further, the first transfer state detection circuit 6 decodes the serial data and applies a pulse B1 indicating that the data transfer is completed to the first temporary memory 2. Then, the first temporary memory 2 stops storing the serial data from the input terminal 1.
[0016]
The second transfer state detection circuit 7 performs the same operation, and applies the pulse A2 shown in FIG. 3C to the second temporary memory 4. Then, the second temporary memory 4 starts storing the serial data from the input terminal 1. Further, the second transfer state detection circuit 7 decodes the serial data and applies a pulse B2 indicating that the data transfer is completed to the second temporary memory 4. Then, the second temporary memory 4 stops storing the serial data from the input terminal 1.
[0017]
The first transfer state detection circuit 6 and the second transfer state detection circuit 7 decode incoming serial data, and can determine to which block the contents are transferred. for that reason,
When the data D1 arrives, the first temporary memory 2 operates so that the data is transmitted to the luminance signal processing block 12, and when the data D2 arrives, the data is transmitted to the chroma signal processing block 13. The second temporary memory 4 operates.
[0018]
In this way, the serially transferred data D1 and data D2 are temporarily stored in the first temporary memory 2 and the second temporary memory 4.
[0019]
Assume that a video signal arrives at the terminal 9 from this state. Then, a vertical synchronization signal is generated from the synchronization separation circuit 20. The vertical synchronizing signal of the video signal sets the timing of transfer from the temporary memory to the original memory (such as the first memory 3).
[0020]
The vertical synchronizing signal of this video signal is asynchronous in timing with the data D1 and data D2. Therefore, a vertical synchronizing signal of a video signal comes while the data D1 and data D2 transferred serially are being written to the first temporary memory 2 and the second temporary memory 4.
[0021]
If the transfer is performed while data is being written to the first temporary memory 2 and the second temporary memory 4, data information will be lost.
[0022]
Therefore, in the present invention, when a vertical synchronizing signal of a video signal arrives in the control circuit 8, after confirming that the data transfer period is not in progress, the temporary memory is transferred to the original memory (eg, the first memory 3). Transferring.
[0023]
Specifically, the vertical synchronizing signal shown in FIG. 3F is applied to the control circuit 8, and the pulses shown in FIGS. 3G and 3H are created therein. In the “H” level period of the pulse of FIG. 3H, it is detected whether the pulse A1 of FIG. 3B is at the “H” level.
[0024]
FIG. 4 shows a specific circuit example of the control circuit 8 of FIG. The vertical synchronization signal shown in FIG. 3F is applied to the terminal 20 shown in FIG. The system control circuit 21 generates a control pulse shown in FIG. 3 (h) and a detection pulse shown in FIG. 3 (g) according to the vertical synchronization signal. This detection pulse is transmitted or cut off when the switch 22 opens and closes. When the detection pulse is transmitted, the contents of the memory are transferred.
[0025]
It is a latch determination circuit 23 that switches the opening and closing of the switch 22. The latch determination circuit 23 determines whether the pulse A1 in FIG. 3B and the pulse A2 in FIG. 3C are at the “H” level or “L” during the period in which the control pulse in FIG. Determine if it is a level.
[0026]
Assuming that the pulse A1 is in the "H" level period T1 in FIG. 3H, the pulse A1 in that period is at the "H" level, so that transfer cannot be performed. Therefore, a control signal for opening the switch 22 is generated from the latch determination circuit 23. Then, the detection pulse is not transmitted.
[0027]
For this reason, the switches 10 and 11 are opened as shown in response to a control signal from the control circuit 8. If the switches 10 and 11 are open as shown, there is no transfer from the temporary memory to the original memory (for example, the first memory 3).
[0028]
Next, when a vertical synchronization signal at the next timing of FIG. 3F is applied to the control circuit 8, the pulse (period T2) of FIG. 3H and the corresponding FIG. ) Is generated. In the “H” level period of the pulse (period T2) in FIG. 3H, it is detected whether the pulse A1 in FIG. 3B and the pulse A2 in FIG. 3C are at the “H” level. .
[0029]
In this case, since both the pulse A1 in FIG. 3B and the pulse A2 in FIG. 3C are at the “L” level, it is clear that the transfer is not in progress. Therefore, the switch 22 is closed by the latch determination circuit 23, and the control signal of FIG. 3I is generated from the control circuit 8, and the switches 10 and 11 are closed according to the control signal. When the switches 10 and 11 are closed, the stored data is transferred from the temporary memory to the original memory (for example, the first memory 3).
[0030]
Therefore, data is simultaneously transferred to the first memory 3 and the second memory 5, and the data is simultaneously transmitted to the luminance signal processing block 12 and the chroma signal processing block 13 during the vertical synchronization signal period. It becomes possible.
[0031]
【The invention's effect】
As described above, according to the present invention, when the same instruction is simultaneously applied to a plurality of controlled circuits, the transfer timings can be equalized.
[0032]
In particular, according to the present invention, data cannot be transferred to the original memory during data transfer to the temporary memory, so that data can be transferred reliably.
[0033]
Further, according to the present invention, data can be transmitted to the luminance signal processing block and the chroma signal processing block during the vertical synchronizing signal period, and the switching noise does not appear on the screen.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a serial data transfer device of the present invention.
FIG. 2 is a waveform chart for explaining a conventional serial data transfer.
FIG. 3 is a waveform chart for explaining the serial data transfer of the present invention.
FIG. 4 is a specific circuit diagram of the control circuit 8 of the present invention.
[Explanation of symbols]
(1) Input terminal (2) First temporary memory (3) First memory (4) Second temporary memory (5) Second memory (6) First transfer state detection circuit (7) Second Transfer state detection circuit (8) Control circuit

Claims (3)

A serial data transfer device for serially transferring data,
An input terminal to which serial data including first serial data and second serial data is applied;
A first temporary memory for temporarily storing first serial data from the input terminal;
A first memory for storing data from the first temporary memory;
A second temporary memory for temporarily storing second serial data from the input terminal;
A second memory for storing data from the second temporary memory;
A first transfer state detection circuit for generating a first control signal indicating that the first serial data from the input terminal is being transferred;
A second transfer state detection circuit that generates a second control signal indicating that the second serial data from the input terminal is being transferred;
When the pulse signal that determines the transfer timing arrives, it is determined that the first and second control signals have not arrived, and the data from the first temporary memory is transferred to the first memory. A control circuit for transferring data from a second temporary memory to the second memory,
A serial data transfer device, wherein the serial data is simultaneously transferred to the first memory and the second memory in response to the pulse signal . A serial data transfer device for serially transferring data,
An input terminal to which serial data including first serial data and second serial data is applied;
A first temporary memory for temporarily storing first serial data from the input terminal;
A first memory for storing data from the first temporary memory;
A second temporary memory for temporarily storing second serial data from the input terminal;
A second memory for storing data from the second temporary memory;
First transfer first serial data from said input terminal to generate a second control signal indicating a first control signal indicating that the middle of transfer, said first serial data transfer is completed A state detection circuit;
A third control signal indicating that the second serial data from the input terminal is during transfer, a second transfer said second serial data transfer to generate a fourth control signal indicating the end A state detection circuit;
When a pulse signal that determines transfer timing arrives, it is determined that the first and third control signals have not arrived, and data from the first temporary memory is transferred to the first memory. A control circuit for transferring data from a second temporary memory to the second memory,
A serial data transfer device, wherein data is simultaneously transferred to the first memory and the second memory in response to the pulse signal . A serial data transfer device for serially transferring data,
An input terminal to which serial data including first serial data and second serial data is applied;
A first temporary memory for temporarily storing first serial data from the input terminal;
A first memory for storing data from the first temporary memory;
A second temporary memory for temporarily storing second serial data from the input terminal;
A second memory for storing data from the second temporary memory;
A first transfer state detection circuit for generating a first control signal indicating that the first serial data from the input terminal is being transferred;
A second transfer state detection circuit that generates a second control signal indicating that the second serial data from the input terminal is being transferred;
A system control circuit that generates a control pulse in accordance with a state change of a pulse signal that determines transfer timing and generates a detection pulse whose generation timing is later than the control pulse in accordance with a state change of the pulse signal ;
A latch discriminating circuit for discriminating that the first and second control signals have not arrived during the generation period of the control pulse from the system control circuit;
A switch for passing or blocking the detection pulse in accordance with a determination output signal of the latch determination circuit, and storing data from the first temporary memory in the first memory in response to the detection pulse from the switch. A serial data transfer device for transferring data from the second temporary memory to the second memory while transferring the data.

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